NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 4-Channel DG509A DG509A (Diff) DG529 DG529 (Diff, Latch) 8-Channel DG508A DG508A DG507A DG507A (Diff) DG528 DG528 (Latch) 16-Channel DG506A DG506A 4-Channel DG409 DG409 (Diff) DG429 DG429 (Diff, Latch) 8-Channel DG408A DG408A DG407 DG407 (Diff) DG428 DG428 (Latch) 16-Channel DG406 DG406 (Low Power) 2-Channel DG534A DG534A (Latch) 4-Channel DG459 DG459 (Diff) DG485 DG485 (8-Channel Serial Control) 4-Channel DG534A DG534A (Diff, Latch) 8-Channel DG458 DG458 DG884 DG884 (8 x 4 Video Crosspoint) 8-Channel DG538A DG538A (Latch) 16-Channel DG535 DG535 (Low Power) DG536 DG536 (Low Power) DG894 DG894 (RGB ... | Original |
1 pages, |
DG529 DG409 DG428 DG485 DG506A DG507A DG509A DG528 DG407 DG429 DG508A DG408A DG406 DG534A DG538A DG509A abstract |
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| Abstract: /Information HEF, HEC HEF4508B HEF4508B MSI Dual 4-bit latch Product specification File under Integrated Circuits , latch January 1995 2 Philips Semiconductors Product specification HEF4508B HEF4508B MSI Dual 4-bit latch January 1995 3 Philips Semiconductors Product specification HEF4508B HEF4508B MSI Dual 4-bit latch January 1995 4 Philips Semiconductors Product specification HEF4508B HEF4508B MSI Dual 4-bit latch January 1995 5 Philips Semiconductors Product specification ... | Original |
9 pages, |
HEF4508B HE4000B HE4000B abstract |
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| Abstract: /Information HEF, HEC HEF4511B HEF4511B MSI BCD to 7-segment latch/decoder/driver Product specification File , BCD to 7-segment latch/decoder/driver January 1995 2 HEF4511B HEF4511B MSI Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver January 1995 3 HEF4511B HEF4511B MSI Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver January 1995 4 HEF4511B HEF4511B MSI Philips Semiconductors Product specification BCD to 7-segment latch ... | Original |
9 pages, |
HEF4511B HE4000B 7-segment" driver 7segment 7.segment 7-segment 7 segment 7segment HE4000B abstract |
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| Abstract: TTL MSI Chip with Latch, Decoder, and Driver Constant-Current Drive for Light-Emitting Diodes PIN ASSIGNMENTS FOR BOTH TYPES 0 040 NOM. * (See note B) Pin 1 Latch Output Os (Binary Weight 2) Pin 2 Latch Output Qc (Binary Weight 4) Pin 3 Latch Output Qd (Binary Weight 8) Pin 4 Latch Output Qa (Binary Weight 1) Pin 5 Latch Strobe Input Pin 6 Latch Data Input C (Binary Weight 4) Pin 7 Latch Data Input D (Binary Weight 8) Pin 8 Ground Pin 9 No Internal Connection Pin 10 Latch Data Input B (Binary Weight 2 ... | OCR Scan |
1 pages, |
introduction of bcd 7 segment 7 segment display 13 pin TTL display 7 binary to led display decoder sevensegment 745-0008 seven segment 8 pin datasheet abstract |
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| Abstract: CXD1095Q CXD1095Q (3/3) 30 - 32, D0 - D7 35 - 39 8 (DATA BUS) 8 8 LATCH 8 54-56, 8 59-63 PA0 - PA7 (PORT A) 8 LATCH 8 3 - 9, 8 64 PB0 - PB7 (PORT B) 8 LATCH 8 11 - 18 PC0 - PC7 (PORT C) 8 8 LATCH 4 4 LATCH CLR 40 DATA SELECT A2 A1 A0 WR RD CS RST 48 47 46 43 44 45 41 CONTROL 20 - 24, 8 27 - 29 PD0 - PD7 (PORT D) 49, 50, 4 52, 53 PX0 - PX3 (PORT X) ... | Original |
3 pages, |
CXD1095Q CXD1095Q abstract |
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| Abstract: /Information HEF, HEC HEF4043B HEF4043B MSI Quadruple R/S latch with 3-state outputs Product specification File , Quadruple R/S latch with 3-state outputs January 1995 HEF4043B HEF4043B MSI 2 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs January 1995 3 HEF4043B HEF4043B MSI Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs January 1995 4 HEF4043B HEF4043B MSI Philips Semiconductors Product specification Quadruple R/S latch ... | Original |
5 pages, |
HEF4043B HE4000B HE4000B abstract |
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| Abstract: LT I L I N E M O D U L E C O N N E C T O R S SERIES 8073 35 / Plug Shroud/Latch 42 35 , In planning TYPE 1 TYPE 2 In planning Latch Ordering Code 818073000XXX007 818073000XXX007 M U LT I L I N E M O D U L E C O N N E C T O R S SERIES 8073 TYPE 3/TYPE 4 / Plug Shroud/Latch Latch Ordering Code 818073000XXX007 818073000XXX007 Cable Connectors 80738071 8073 80735 3456 Series 8073 cable connector is used through the shroud with latch of the same series in order to ... | Original |
3 pages, |
datasheet abstract |
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| Abstract: 2.00mm LAtCH HeADeR .079" [2.00] CenterlIne Adam Technologies, Inc. 2Mhr SerIeS 2MHr , ] .079 [2.00] 2MHR-34-VUAS 2MHR-34-VUAS .079 [2.00] B A B .079 [2.00] .079 [2.00] LATCH DIMENSIONS X Y LONG LATCH .775 [19.70] SHORT LATCH .665 [16.90] A = .079 [2.00] X No. of , [2.00] .079 [2.00] LATCH DIMENSIONS X Y LONG LATCH .775 [19.70] .452 [11.50] SHORT LATCH .665 [16.90] .342 [8.70] A = .079 [2.00] X No. of Spaces + .697 [17.70] B = .079 ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: Timing Diagram for PWM Mode s Usage Note 2 Do not set "0000 16" to Timer A or Timer B latches. Reason , "L" output setting), it is necessary "write to both timer and timer latch at the same time". Do not "write to timer latch only". VFor this purpose, Timers X and Y have the write control bits that let you select "write to both timer and timer latch at the same time" or "write to timer latch only". Reason: If the timer value is updated with "write to timer latch only," the PWM output waveform may have an ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: (Mates with Shrouded Eject Latch Header Latch 1) None (Mates with Shrouded Eject Latch Header Latch 2) Low Profile (Mates with Shrouded Eject Latch Header Latch 1) Latching (Mates with Low Profile Headers , low profile headers s QuickieTM Shrouded eject latch headers Page 8 14 16 Packaging Tubes , Strain Relief Latching Strain Relief For Low Profile Header Low Profile Strain Relief ... | Original |
2 pages, |
BUS-12-095 LR46923 idc shrouded header datasheet abstract |
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| /* Transparent High Latch * D_LATCH.V * Xilinx HDL Synthesis Design Guide for FPGAs * June 1995 */ module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin if (GATE = 1'b1) Q www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/d_latch/d_latch.v |
Xilinx | 30/05/1995 | 0.31 Kb | V | d_latch.v |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/52728641-985501ZC/wcd00ea6.zip (d_latch.v) |
Xilinx | 12/02/1999 | 7683.96 Kb | ZIP | wcd00ea6.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/1770998-985499ZC/wcd00ea4.zip (d_latch.v) |
Xilinx | 12/02/1999 | 3545.64 Kb | ZIP | wcd00ea4.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/10929841-987152ZC/wcd02ea4.zip (d_latch.v) |
Xilinx | 13/07/1998 | 7683.96 Kb | ZIP | wcd02ea4.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/67714387-987154ZC/wcd02ea6.zip (d_latch.v) |
Xilinx | 13/07/1998 | 3545.64 Kb | ZIP | wcd02ea6.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/74691760-985949ZC/wcd010c9.zip (d_latch.v) |
Xilinx | 13/07/1998 | 7683.96 Kb | ZIP | wcd010c9.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/46632123-985931ZC/wcd010bf.zip (d_latch.v) |
Xilinx | 13/07/1998 | 62.46 Kb | ZIP | wcd010bf.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/8931125-985945ZC/wcd010c7.zip (d_latch.v) |
Xilinx | 13/07/1998 | 3545.64 Kb | ZIP | wcd010c7.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/53521490-985935ZC/wcd010c1.zip (d_latch.v) |
Xilinx | 13/07/1998 | 126.32 Kb | ZIP | wcd010c1.zip |
| //////////////////////////////////////////// // D_LATCH.V Version 1.0 // // Example of a behavioral description of // // a transparent latch. // // HDL Synthesis Design Guide for FPGAs // // May 1997 // //////////////////////////////////////////// module d_latch (GATE, DATA, Q); input GATE; input DATA; output Q; reg Q; always @ (GATE or DATA) begin: LATCH if (GATE = 1'b1) Q www.datasheetarchive.com/download/19978565-988332ZC/wcd036cd.zip (d_latch.v) |
Xilinx | 12/02/1999 | 3545.64 Kb | ZIP | wcd036cd.zip |