NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Signetics Logic Products 7404, LS04, S04 Inverters Hex Inverter Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7404 10ns 12mA 74LS04 74LS04 9.5ns 2.4mA 74S04 74S04 3ns , unit load (ul) is understood to be 40/iA l]H and -1.6mA Iil, a 74S unit load (Sul) is 50^A ltH and -2.0mA l|L, and 74LS unit load (LSul) is 20mA l(H and -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC , 853-0504 81501 Signetics Logic Products Product Specification Inverters 7404, LS04, S04 ABSOLUTE MAXIMUM ... | OCR Scan |
3 pages, |
pin configuration 74LS04 NOT gate 74LS04 N74S04D N74S04N 74LS04 NOT gate ttl family 7404 7404 ttl inverter 74LS 7404 74LS04 74LS04 Hex Inverter definition l504 7404 hex inverter 7404 TTL 74LS04 abstract |
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| Abstract: Signetics 7404, LS04, S04 Inverters Hex Inverter Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7404 10ns 12mA 74LS04 74LS04 9.5ns 2.4mA 74S04 74S04 3ns , unit load (ul) is understood to be 40/jA l|H and -1.6mA l)L, a 74S unit load (Sul) is 50pA Iih and -2.0mA l|L, and 74LS unit load (LSul) is 20/uA lIH and -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL , 853-0504 81501 Signetics Logic Products Product Specification Inverters 7404, LS04, S04 ABSOLUTE ... | OCR Scan |
3 pages, |
74LS04 PIN LOGIC 7404 7404 signetics 7404 ttl inverter 74LS04 fan-out 7404 TTL TTL 7404 signetics 74ls04 7404 ls ttl family 7404 7404 inverter pin configuration pin configuration of 7404 7404 not 74LS04 74S04 74LS04 abstract |
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| Abstract: Symbol Function (16) - NC Not Connected (15) - E2 Enable 2 for EA 7404 (14) 1 VSS Ground (+5V for , +49-89-8541721 · lcd-module.de EA 9700-TXT 9700-TXT FUNCTIONAL DESCRIPTION EA 9700-TXT 9700-TXT is a text controller with a , text. The maximum number of different texts depends on the display size and is limited to 256 at small displays (8 select lines -> 256 texts). For larger displays it is calculated using the following formula , at $0400 is displayed leftmost in the first line of the display as long as TEXT 0 is selected (TC0 ... | Original |
4 pages, |
27C64 VK-2240 VK-2140 2X20 VK-2005 VK-2003 7404 ea 7401 VK-2420 cd 7404 7404 not VK-2014 not 7404 9700-TXT VK-2000 9700-TXT abstract |
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| Abstract: is not a dimensional value that exists alone. It is indicated as shown below. b x M Maximum-body condition.Indicates that the value is based on limit dimensions where the body is maximum. , error margin for the lead center position (Abstract from EIAJ standard ED-7404) An increasing number of , permissible error margin is related to the interval in a straight line between leads (true geometric position) and lead width. The permissible error margin for the QFP lead center position is outlined below ... | Original |
2 pages, |
ED-7404 ED-7404 abstract |
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| Abstract: initialised for 2 lines operation (duty 1:16) by the power-on reset routine. DIP B is not used for selection , 33h cursor not blinking Set cursor position ESC 3Dh r c The cursor is moved to the position , (ONLY WITH EA 7404) EA 9700-A2 9700-A2 EA 9700-B2 9700-B2 EA 9700-C1 9700-C1 LOCHHAMER SCHLAG 17 · D- 82 166 GRÄFELFING , 9700-B2 9700-B2 and EA 9700-C1 9700-C1 the attached display module is initialised according to DIP-switch B. The , ! THREE VERSIONS ARE AVAILABLE: EA 9700-A2 9700-A2 Serial transmission is possible with HANDSHAKE or ... | Original |
8 pages, |
not 7404 ea 7401 BD192 2X16 lcd module 9700-C1 lcd hd 44780 VK-2000 9700-A2 9700-B2 VK-2000 abstract |
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| Abstract: NUMBER THIRD ANGLE PROJECTION DO NOT SCALE DRAWING DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE , DATE REV ECN APP'D. BY 10-17-05 A2 7346 TRM 2-1 --06 A3 7404 JM .605 [15.24] MAX - STEWART PATENTED SÏÏÎÎÎ1 -.450 [11.43]- ci tsi m -Q 1T 3t 5 T ' & ï^ NOTES: 1. CONNECTOR MATERIALS: HOUSING: THERMOPLASTIC UL94- UL94- V-0 CONTACTS: COPPER ALLOY CONTACT PLATING: SELECTIVE GaD IN , DF BEL STEWART CONNECTOR AND SHALL NOT BE REPRODUCED, COPED, OR USED IN ANY MANNER WITHOUT PRKK ... | OCR Scan |
1 pages, |
pa 605 not 7404 SS-640810-NF c.i 7404 ci not 7404 CI 7404 datasheet abstract |
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| Abstract: clock about the VSS level is particularly critical. If the VSS - 1 VOH is not maintained, at all times , the 7404 because of the inductance, L. This exceeds the total output current swing so it is , DS0026 DS0026 Dual High-Speed MOS Driver General Description Features DS0026 DS0026 is a low cost , is intended for applications in which the output pulse width is logically controlled; i.e., the output pulse width is equal to the input pulse width. The DS0026 DS0026 is designed to fulfill a wide variety ... | Original |
9 pages, |
TTL 7404 national semiconductor 7404 not AN-76 CIRCUIT DIAGRAM 7404 DM7440 DS8830 M08A not 7404 MUA08A MU08A LOGIC 7404 functional DIAGRAM 7404 logic diagram of 7404 DS0026 DS0026 DS0026 abstract |
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| Abstract: critical. If the VSS - 1 VOH is not maintained, at all times, the information stored in the memory could be , time of the clock is high enough to completely isolate the clock transient from the 7404 because of , DS0026 DS0026 Dual High-Speed MOS Driver General Description Features DS0026 DS0026 is a low cost , is intended for applications in which the output pulse width is logically controlled; i.e., the output pulse width is equal to the input pulse width. The DS0026 DS0026 is designed to fulfill a wide variety ... | Original |
8 pages, |
DS8830 DS0026 DM7440 AN-76 DS0026CN DS0026 abstract |
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| Abstract: level is particularly critical. If the VSS - 1 VOH is not maintained, at all times, the information , DS0026 DS0026 Dual High-Speed MOS Driver General Description Features DS0026 DS0026 is a low cost , is intended for applications in which the output pulse width is logically controlled; i.e., the output pulse width is equal to the input pulse width. The DS0026 DS0026 is designed to fulfill a wide variety , other systems is included in the application note AN-76 AN-76. n n n n n Fast rise and fall times ... | Original |
8 pages, |
DS0026 AN-76 datasheet 7404 ttl DM7440 MOS Clock Driver LOGIC 7404 functional DIAGRAM 7404 DS8830 7404 recommended operating conditions DS0026CN SILVER-MICA TTL 7404 national semiconductor datasheet 7404 DS0026 abstract |
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| Abstract: of the clock about the VSS level is particularly critical. If the VSS - 1 VOH is not maintained, at , the 7404 because of the inductance, L. This exceeds the total output current swing so it is , DS0026 DS0026 Dual High-Speed MOS Driver General Description Features DS0026 DS0026 is a low cost , is intended for applications in which the output pulse width is logically controlled; i.e., the output pulse width is equal to the input pulse width. The DS0026 DS0026 is designed to fulfill a wide variety ... | Original |
8 pages, |
not 7404 MM5262 functional DIAGRAM 7404 DS8830 DM7440 circuit diagram of 7404 DS0026CN DS0026 AN-76 DS0026 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| * # Contains Proprietary Information * # Which is The Property of * # SYMMETRY OR ITS LICENSORS * #* template irf7404 d g s # MODPEX model for PowerMOS irf7404 # Model generated on Apr 23, 96 # Model : # The voltage-dependent capacitances are # not included. Other default values are: # LD=0 CBD=0 CBS=0 CGBO=0 spm.model mm=(type=_p, level=1,is=1e-32,rd=1e-6, , cgso=1.22651e-05,cgdo=1.00004e-11) spd.model md=(is=2.34977e-08,rs=0.0309331,n=1 www.datasheetarchive.com/download/28599382-285476ZC/wcd00219.zip (irf7404.sin) |
International Rectifier | 18/09/1998 | 311.96 Kb | ZIP | wcd00219.zip |
| * # Contains Proprietary Information * # Which is The Property of * # SYMMETRY OR ITS LICENSORS * #* template irf7404 d g s # MODPEX model for PowerMOS irf7404 # Model generated on Apr 23, 96 # Model : # The voltage-dependent capacitances are # not included. Other default values are: # LD=0 CBD=0 CBS=0 CGBO=0 spm.model mm=(type=_p, level=1,is=1e-32,rd=1e-6, , cgso=1.22651e-05,cgdo=1.00004e-11) spd.model md=(is=2.34977e-08,rs=0.0309331,n=1 www.datasheetarchive.com/files/international-rectifier/docs/wcd0000b/wcd00b64.sin |
International Rectifier | 18/09/1998 | 1.93 Kb | SIN | wcd00b64.sin |
| .SUBCKT irf7404 1 2 3 * * Model Generated by MODPEX SOFTWARE * * Contains Proprietary Information * * Which is The Property of =100u * Default values used in MM: * The voltage-dependent capacitances are * not included. Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-1 D IS=2.34977e-08 RS=0.0309331 N=1.5 BV=20 +IBV=0.00025 EG=1 XTI=3.26302 TT=0.0001 +CJO=1.53447e-09 www.datasheetarchive.com/download/5169070-285474ZC/wcd00217.zip (irf7404.spi) |
International Rectifier | 18/09/1998 | 292.83 Kb | ZIP | wcd00217.zip |
| .SUBCKT irf7404 1 2 3 * * Model Generated by MODPEX SOFTWARE * * Contains Proprietary Information * * Which is The Property of =100u * Default values used in MM: * The voltage-dependent capacitances are * not included. Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-1 D IS=2.34977e-08 RS=0.0309331 N=1.5 BV=20 +IBV=0.00025 EG=1 XTI=3.26302 TT=1e-07 +CJO=1.53447e-09 www.datasheetarchive.com/files/spicemodels/misc/models/irf7404.spi |
Spice Models | 01/09/2003 | 1.7 Kb | SPI | irf7404.spi |
| * * *# .SUBCKT PBSS4560PA PBSS4560PA PBSS4560PA PBSS4560PA 1 2 3 * Q1 1 2 3 PBSS4560PA PBSS4560PA PBSS4560PA PBSS4560PA D1 2 1 DIODE * * Diode D1 is dedicated to improve modeling of reversemode * operation and does not reflect a physical device. * .MODEL PBSS4560PA PBSS4560PA PBSS4560PA PBSS4560PA NPN + IS = 1.437E-012 437E-012 437E-012 437E-012 + NF = 0.956 + ISE = 5.283E-014 283E-014 283E-014 283E-014 + NE = 1.354 + BF = 513 + IKF = 3 = 1.11 + XTI = 3 + CJE = 7.404E-010 + VJE = 0.7269 + MJE = 0.3563 + TF = 9.5E-010 5E-010 5E-010 5E-010 + XTF + TR = 6E-009 6E-009 6E-009 6E-009 + CJS = 0 + VJS = 0.75 + MJS = 0.333 + FC = 0.98 .MODEL DIODE D + IS = 1.513E www.datasheetarchive.com/download/28222960-596966ZC/41781.zip (PBSS4560PA.prm) |
NXP | 23/10/2012 | 188.74 Kb | ZIP | 41781.zip |
| are not shared function pins (like 555) anymore. A 27512 (64K bytes) is shown in the reference arrangement on the connector is not a standard. System designer is encouraged to reference VESA's FPDI II may or may not need a 'contrast adjustable voltage' which is in the range of 0V to VDD. The reference usually connected to Y0:7 and VP8:15 is usually connected to UV0:7. This is not a strict rule since inside source. PCLK pin is not used. If video interface is not used. All input signals can be left open or www.datasheetarchive.com/download/49805886-262311ZC/or69k.zip (Using the 69K reference design .doc) |
Intel | 01/04/1999 | 807.99 Kb | ZIP | or69k.zip |
| , 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00, 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */ _NOT contributed to this * project. * * This program is free software; you can redistribute it and/or * modify ; either version 2 of * the License, or (at your option) any later version. * * This program is this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330 _EXT_LED (unsigned char *) (0x10000000 + 12) # define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13) #define _NOT www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (IAD210.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| .SUBCKT irf7404 1 2 3 * * Model Generated by MODPEX SOFTWARE * * Contains Proprietary Information * * Which is The Property of =100u * Default values used in MM: * The voltage-dependent capacitances are * not included. Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-1 D IS=2.34977e-08 RS=0.0309331 N=1.5 BV=20 +IBV=0.00025 EG=1 XTI=3.26302 TT=0.0001 +CJO=1.53447e-09 www.datasheetarchive.com/files/international-rectifier/docs/wcd0000a/wcd00a7e.spi |
International Rectifier | 18/09/1998 | 1.7 Kb | SPI | wcd00a7e.spi |
| maximum Torque w Efficiency is not optimized w Motor is oversized In this application note, the flux loading conditions of the motor are such that the voltage controller is not able to set the motor at the or not, and TCKM is the period of the clock master. In the case described, when the number of is to show how to perform the slip control of an AC three- phase induction motor with ST52x420, in improvement by voltage control is obtained by reducing the applied voltage when- ever the torque requirement www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7230-v1.htm |
STMicroelectronics | 18/07/2000 | 34.88 Kb | HTM | 7230-v1.htm |