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Part Manufacturer Description Datasheet BUY
ISL6218CVZ-T Intersil Corporation Single Phase IMVP-IV Controller for Intel Pentium M; QFN40, TSSOP38; Temp Range: 0° to 70° visit Intersil
ISL6218CRZ Intersil Corporation Single Phase IMVP-IV Controller for Intel Pentium M; QFN40, TSSOP38; Temp Range: 0° to 70° visit Intersil
ISL6218CVZA-T Intersil Corporation Single Phase IMVP-IV Controller for Intel Pentium M; QFN40, TSSOP38; Temp Range: 0° to 70° visit Intersil
ISL6216CAZ-T Intersil Corporation PWM Controller for Intel Pentium M; QSOP28; Temp Range: 0° to 70° visit Intersil
ISL6218CRZ-T Intersil Corporation Single Phase IMVP-IV Controller for Intel Pentium M; QFN40, TSSOP38; Temp Range: 0° to 70° visit Intersil
ISL6218CVZ Intersil Corporation Single Phase IMVP-IV Controller for Intel Pentium M; QFN40, TSSOP38; Temp Range: 0° to 70° visit Intersil

intel+8255

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Abstract: Telephony IC Cross Reference Sames SA541 SA5414 SA545 SA585 SA587 SA588 SA589 SA2531 GPS MA541 MA5414 MA545 MA585 MA587 MA588 MA589 - STM M3541 - AMS AS2531 Telecom IC Cross Reference Sames Part # SA2030 SA9030 SA9101 SA3488 SA9202 SA9203 SA9204 SA9205 * = Not pin compatible Equivalent Part # PEB2030 FAU30.3 PEB2035 (PCM 30 ONLY) M3488 8255* 8255* 8255* 8255* Supplier Siemens Siemens / SGS Thompson Siemens SGS Thompson Intel Intel Intel Intel - -
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intel ic 8255 ic 8255 8255 ic 8255 intel 8255 intel FAU30.3
Abstract: .1 8255 Programmable Peripheral Interface Applications 8080 CPU MODULE INTER FA C E , INTERFACE. 10 8255 To Peripheral Hardware Interface.10 8080 CPU Module To 8255 In te rfa c e . 10 Mode 0 Interface S o f tw a re , PRINTER IN T E R F A C E . 15 CPU Module To 8255 Interface. 15 8255 To Peripheral Interface. 15 Mode 1 Software D r i v e r -
OCR Scan
INTEL SDK-80 8255 intel microprocessor architecture lm 7407 buffer chip intel 8080 intel 8080 assembly language lt 302d AP-15 MCS-073-0576/30K
Abstract: CFI2550B 8255 CFI2550B GENERAL DESCRIPTION: INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE CFI2550B is compatible with Intel 8255. It is also compatible in I/Os except for the fact that each bidirec tional data bus is separated into two signals. However, the user can make it fully compatible with 8255 , Logic Corporation 1989,1990 238 CFI2550B PIN DESCRIPTION: INPUT 8255 CFI2550B DI WRN , Float 6 9 TWOB WR = 1 to OBF = 0 16 TAOB ACK = 0 to OBF = 1 12 239 CFI2550B 8255 12 17 20 17 -
OCR Scan
intel 8255 8255 pin diagram intel 8255 pin diagram 8255 a pin diagram 8255 programmable peripheral interface 8255 input output in all mode CFI25S0B
Abstract: Parallel digital communication Interface to electromechanical and solid-state relays 8255 emulation , starting a new transfer. You can specify an ACK pulse delay. 8255 Emulation This protocol emulates the strobed protocols implemented by the 8255 and 82C55 PPI chips ­ chips that are used, for example, on , the use of FIFO buffering, 8255 emulation mode offers much higher data transfer rates than with an actual 8255 chip. Burst Mode The PXI-6533 sends or receives a clock signal to or from the peripheral National Instruments
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8255 PPI INTEL DAQDIO 8255 PPI Chip Peripheral interface 8255 8255 pci or dma PPI 82C55 430FX
Abstract: DATA FROM ' 8080 TO 8255 \ JT yr -*ak- / -< >â'" DATA FROM PERIPHERAL TO 8255 DATA FROM 8255 TO PERIPHERAL NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is , 8255 TO 8080 WRITE AO-I. CS 3t X XJ X READ X X DATA BUSv/twt/Z HIGH IMPEDANCE VALID -
OCR Scan
I8255A block diagram of intel 8255 chip Peripheral interface 8255 notes 8255 application 8255 application note microprocessor 8255 application VEXT-75011 AFN-00863A
Abstract: 10mA Intel 8254 MSM82C55A-2 5V 8mA Intel 8255 MSM82C59A-2 5V 5 mA -
OCR Scan
intel 8288 8255 interface with 8086 Peripheral 8253 Programmable Interrupt Controller 8155 programmable peripheral interface interface 8254 with 8086 intel 8253 MSM80C85AH MSM80C86A-10 SM80C88A-10 MSM81C55-5 MSM82C12 MSM82C37B-5
Abstract: Synchronous/Asynchronous Receiver/Trans mitter". AP-16. "8255 Programmable Peripheral Interface Applications , SBC 80/10 contains 48 programmable parallel I/O lines implemented using two IntelB 8255 Pro grammable , . Interrupt requests may originate from six sources. Two from the 8255's, two from the 8251 and two from user , bidirectional port. % The 8255's can generate interrupts when a byte of information is ready to be , : one via the system bus and the other via the I/O edge connector. The two interrupts from the 8255 -
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intel 8251 USART SBC 8251 intel 8251 CT5002 Fluke 8375 schematic diagram of scada system AP-26 PL/M-80 ICE-80
Abstract: Experiment On 8255 PPI chip Objectives : To study how 8255 PPI chip works. After completing this experiment, you should know the different operation modes of an 8255 PPI chip and how to configure the chip , Apparatus : 8051 evaluation board and 8255 evaluation board Reference : H-P. Messmer, "The indispensable , III, Pentium 4 Architecture, Programming, and Interfacing", 6th Ed, Chapter 11, Section 3. 8255 datasheet AT89S8252 datasheet (instruction set) Background The 8255 PPI chip is a general purpose -
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8255 interfacing with 8086 8255 interface with 8051 ppi 8255 PPI 8255 interface with 8086 8255 PPI Control word 8255 PPI 8255/CC/EIE
Abstract: 8253 compatible timer 8255 compatible PIO port Bus control logic Clock generation logic DRAM control , compatible timer, and 8255 compatible peripheral I/O port. It also includes logic for bus control, DRAM -
OCR Scan
digital clock using 8086 8253 interface with 8086 Peripheral interfacing of 8237 with 8086 intel 8086 8086 interface 8255 interface of 8086 with 8255 T-52-33-Q5 FE2011 80C86 1920K FE201T W159110/87
Abstract: Parallel digital communication Interface to electromechanical and solid-state relays 8255 emulation , each protocol can communicate. 8255 Emulation This protocol emulates the strobed protocols implemented by the 8255 and 82C55 PPI chips ­ chips that are used, for example, on DIO-24 and DIO-96 devices , wider data path, and the use of 8255 6.67 4 4 FIFO buffering, 8255 emulation Emulation mode offers much higher data Level ACK 3.33 2.5 2.5 transfer rates than with an actual 8255 chip National Instruments
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PCI-DIO-32HS AT-DIO-32HS 8255 Chip R6850-D1 8255 operating modes PCI-DIO pcidio32hs NT/95 NT/95/3 440FX
Abstract: PERIPHERAL TO 8255 0DATA FROM 8255 TO PERIPHERAL \ NOTE Any sequence where WR occurs before ACK Intel
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8255 intel microprocessor block diagram 8080 intel microprocessor pin diagram microprocessor 8255 application s MD2147H Intel 8080 interface Intel 8255 electrical data MIL-STD-883B MR2I28 MR2147H MR2I48H MR2167 MR2164
Abstract: 8255 programmable ^peripheral interface. Handshake operation with the 8255 i$ ¿pntroBedtfy Inverting , the 8255 Strobe. The internal control register of the 8255 should be set in MODE 1 for the port used. If the 8255 IBF flag is low and the ADC-7109 is in handshake mode, the next word will be strobed into the port. The strobe will cause IBF (of the 8255) to go high (SEND goes low), which will keep the enabled byte outputs active. The 8255 win genirifetie/sin intertijpt which when executed will result in -
OCR Scan
Peripheral interface 8255 with ADC ADC 7109 ADC7109 intel 8055 7109 adc 8255 intel microprocessor 02048-1194/TEL 339-3000/TLX174388/FAX 339-3000/TLX 174388/FAX
Abstract: 48 channels of Digital (TTL) I/O (8255 compatible). 3 Counter/Timer channels 283-1907 PCI-DIO , /Timers 24 channels of Digital I/O (8255 compatible). 283-1913 PCI-WDT Power supply monitor , arranged as 6 x 8 bit ports (Intel 8255 compatible) at TTL I/O levels Pull-ups or pull-downs on all I/O lines (user option) Interrupts may be generated from 8255 mode 1 and 2 operation Timer Section RS Components
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8255 pci 16C550 EN50082-2 intel 8254
Abstract: 10/100M LAN (RTL8100CL/8255 1ER) USB 0~3 5X2Pin 2.0mm Box Header AC-Link BIOS PLCC 4M Advantech
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PCA-6780 PCA-6780F-S0A1E 15PIN lpt 8255 ISA 16 bit 2.54mm pin Header lcd LVDS 40pin to 50pin adapter RJ-45 852GM 10/100B PC104 ATA-100/66/33
Abstract: connected to the I/O data port. The 8255 has two additional address line to select the internal , wr_to_8255(unsigned char reg, unsigned char val) { _outp(CTRL, reg | D8255_WR ); /* write to control */ _outp(DATA, val ); /* write to data port */ _outp(CTRL, reg | D8255_DL ); /* idle 8255 */ } inline unsigned char rd_from_8255(unsigned char reg) { unsigned char read; _outp(CTRL, reg | D8255_DL , Reset_Board() { wr_to_8255(D8255_CC, D82_BCO); /* put 8255 in output mode */ wr_to_8255(D8255_PA, D8x_DLE Analog Devices
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EE-158 ADSP-2181 ADSP2181 ADSP-2183 d8255c i8255 memory interface 8255 C2000HS datasheet+intel+IC+8255 ADSP-218 ADDS-2181-EZ-
Abstract: Requires , Temp DC/DC CAN 8255 HCS 08 OPTO Diodes Power I2C CAN CAN I/O 8255 I/O , for 8255 I/O 64-pin header for PC/104 Ordering Information: MCB58 MCB58-ET HC(s)08 , (Requires 58OPT12) 58OPT22 1 Ch CAN, 16 DIO, I2C 58OPT24 8255 â'" 24 TTL DIO 58OPT30 Extended VDC Micro/sys
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dk58 NT/2000/XP 5-30VDC 98/NT/2000/XP MPC116 MPC132 MPC148
Abstract: - PACKAGING INFORMATION .325 MAX. (8.255) .010 TYP. (0.254) 16-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D -
OCR Scan
BPK70 VMOS Transistor vmos bubble memory intel 8085 INTEL 7250 CPU12 AFN-01359A
Abstract: Controller, 8254 Interval Timer, 8255 Peripheral Interface, 8288 Bus Controller, 8259 Interrupt Controller , -channel programmable in-terval timer; the parallel peripheral interface and the 8255 programmable interrupt controller , Timer (8253) 060-063 PIO (8255) 081-083 DMA page registers 0A0 NMI mask registers 100-1FF Reserved PIO is equivalent to 8255 but it must be configured in a fixed way for the system to be IBM PC/XT -
OCR Scan
interfacing of 8237 with 8085 8255 Programmable Interrupt Controller A5E224M interfacing of 8253 devices with 8085 intel 8237A DMA Controller 8255 keyboard interfacing 377747S GC100 T-5Z-33-05 E5530 000DDL
Abstract: through parallel communication with handshaking (8255-compatible). All necessary parameters, such as bar , Even I Data Bits 7 or 8 1 Stop Bits 1 1 * Intel 8255 Mode 1-compatible (parallel output 1 is available -
OCR Scan
DL3-01 datalogic sr11 datalogic p10 8255 PIO 8255c 8255 Programmable Input-Output Port Datalogic D00Q130 DL60-00/01 DL5310/5312 DL3-02
Abstract: List 82.55 100.33 * All the specifications and photos are subjected to be changed without -
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VT82C694T 82C686B SBC82630VE-4M sbc82630 sbc82630 manual LVDS 30 pin hirose connector LVDS Asiliant 69030 2 x USB Ports SBC82630 SBC82630 PCI/104 512MB PK95000-24
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