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CD4049UBM Texas Instruments CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125
CD4049UBF Texas Instruments CMOS Hex Inverting Buffer/Converter 16-CDIP -55 to 125
CD4049UBF3A Texas Instruments CMOS Hex Inverting Buffer/Converter 16-CDIP -55 to 125
CD4049UBM96 Texas Instruments CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125
CD4049AFB Texas Instruments CMOS Hex Inverting Buffer/Converter 16-CDIP -55 to 125
CD4049UBDRE4 Texas Instruments CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125

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Part : IC404A Supplier : Black Box Manufacturer : Newark element14 Stock : 14 Best Price : $1,092.8001 Price Each : $1,092.8001
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ic 4049

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: M E C H A N IC A L D A T A (dimensions in mm) Dual in-line ceramic package for HCC 4049 U B D and H , itncn ! HCC/HCF 4049 UB a-, 41C SC H E M A T IC D IA G R A M S 1 of 6 identical units For 4049 , L L O A D S H IG H -T O -L O W L E V E L L O G IC C O N V E R S IO N Q U IE S C E N T C U R R E N T S P E C IF IE D TO 20V F O R H C C D E V IC E H IG H " S I N K " A N D " S O U R C E " C U R R E N T C A P A B IL IT Y 5V, 10V A N D 15V P A R A M E T R IC R A T IN G S -f IN P U T C U R R E N T O F -
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4049UB 4050B IC 4049 ub HC 4050 N 742537 4049 bf 4049UB/4050B
Abstract: values are re fe rre d t o V s s p in volta g e O R D E R IN G NUM BERS: HCC 4049 UBD fo r dual in -lin e ceram ic package HCC 4049 UBF fo r dual in -lin e ceramic package, HCC 4049 UBK fo r ceramic , C A P A B IL IT Y â'¢ â'¢ 5V, 10V A N D 15V P A R A M E T R IC R ATIN G S INPU T C U R R E N , A R D S P EC IFIC ATIO N S FOR DESCRIPTIO N OF " B " SERIES CMOS D E V IC E S " The HCC 4049U B , o n o lith ic integrated circuits available in 16-lead dual in -lin e plastic or ceramic package -
OCR Scan
Abstract: /4050B B1R (P lastic Package) F1R (C eram ic Package) M1R (M icro Package) C1R (C hip C , immunity and a stable output. Input protection circuits are different from those of the high speed CMOS IC , M 54/M 74HC 4049/4050 CIRCUIT SCHEMATIC (Per Gate) HC4049 HC4050 CHIP CARRIER H C4049 > O O O , 74HC 4049/4050 PIN DESCRIPTION (H C 4 0 4 9 ) PIN No 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 13, 16 8 , MCBmmETFBWIlKB* 1075 M 54/M 74HC 4049/4050 RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vi Vo Top tr, tf -
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4049 CMOS Inverter CMOS 4049 internal circuit 4049 CMOS operation of ic 4049 LC12480 iC 4049 14 pin 54/74HC 4049B/4050B 74HCXXXXC1R M54/74HC4049 M54/74HC4050 M54/75HC4049
Abstract: h a f r f r is S E M IC 0N D U C T0R February 1998 Features · Typical Propagation Delay: 6ns at , VIEW 4049 V cc TY 1A 2Y 2A 3Y 3A GND 4050 V cc E 1Y \2_ 1A ^ 2Y ^ 2A ^ 3Y Q [ 3A ^ GND Q [ -U -4050 16] NC 15] 6Y 14] 6A 13] NC 12] 5Y Ï Ï ] 5A ÏÏÏ] 4Y ][]4 A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A C AUTIO N : These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling , Functional Diagram 4050 4049 4049 4050 Vcc 1Y 1Y 6Y 6Y 2Y 2Y NC 3Y 3Y -
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ic 4050 pin diagram 4049 logic gate 4049 PC 4049 pin diagram cd74hc4050 hct 4049 CD74HC4049 CD74HC4050 D74HC4049E D74HC4050E CD74HC4049M CD74HC4050M
Abstract: Ordering number:ENN1773 Thick Film Hybrid IC STK7560 Series Chopper Type Parallel 2 , terminals, portable VTRs. unit:mm 4049 [STK7560 Series] 64.0 55.6 8.5 18 2.54 17×2.54=43.18 , Case Outline No.4049 No.4050 No.4050 No.4050 No.4051 Case Outline No.4049 No.4050 No , STK7563F STK7563G STK7563J STK7563L Case Outline No.4049 No.4050 No.4050 No.4050 No.4051 Type No. *STK7565A *STK7565F Case Outline No.4049 No.4050 * New product Specifications SANYO Electric
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SIP18 STK7562J STK7563 EI-26 STK7573B stk7573a 4049 application note
Abstract: , layout May 21, 2007 APPLICATION NOTE 4049 MAX8660/MAX8661 PCB Layout Guide Abstract: The , to the IC. r Place C11 between PV1(36) and PG1(34) as close as possible to the IC. r Place C15 between PV2(14) and PG2(16) as close as possible to the IC. r Place C18 between PV4(3) and PG4(5) as close as possible to the IC. r The step-down converter input bypass capacitors are the most critical , . Install the input capacitors on the same side of the PCB as the MAX8660/MAX8661 IC in order to minimize Maxim Integrated Products
Original
MAX8660 AN4049 APP4049 IC 4049 DATASHEET ic 4049 pinout RADIATING AREA INDUCTORS 4049 comparator applications of 4049 integrated circuit pcb thermal Design guide pcb trace MAX8660- MAX8660EVKIT
Abstract: SOIC PKG. NO. E16.3 E16.3 M16.15 M16.15 Pinout CD74HC4049, C D74HC4050 (PDIP, SOIC) TOP VIEW 4049 VCC 1Y 4050 V ccE U 4050 16] NC 15] 6Y 1 ^ 6A 13] NC 4049 NC 6Y 6A NC 5Y 5A 4Y 4A 1A 2Y 2A 3Y 3A , devices are sensitive to electrostatic discharge. Users should tollow proper IC Handling Procedures , 4050 4049 4049 4050 1Y 1Y 6Y 6Y 2Y 2Y NC 3Y 3Y 5Y Logic , 5 35 - 4. CpD is used to determ ine the dynam ic power consumption, per gate. 5. PD = Vqq2 -
OCR Scan
A104Y CD74HC4049E CD74HC4050E IS09000 1-800-4-HARRIS
Abstract: CD74HC4049, C D74HC4050 (PDIP, SOIC) TOP VIEW 4049 4050 4050 16] NC 15] 6Y 14] 6A 13] NC 12] 5Y 5A 10] 4Y ^ ]4 A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A Vcc 1Y 1A 2Y 2A 3Y 3A GND vcc [T 1Y [7 1A 2Y [7 2A [7 3Y ^ , proper IC Handling Procedures. Copyright © Harris Corporation 1997 , File Number 1543.2 CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 V CC 16 15 4049 NC 4050 1Y 1Y 1A , 2. CpD is used to determ ine the dynam ic power consumption, per gate. 3. PD = V q q 2 fj (CpD + C|_ -
OCR Scan
D74HC4049 CD54HC4049H CD54HC4050H D54HC4049W
Abstract: high-speed Si-gate C M O S device and is pin compatible with the " 4049 " of the "4000B " series. It is specified in compliance with JE D E C standard no. 7 A. The 7 4 H C 4049 provides six inverting buffers with , = 5 V SYM BO L PARAMETER C O N D IT IO N S HC 8 3.5 14 T Y P IC A L SSI U N IT ns pF PF , [ T V1/V2 W],c. 4049 77] 5Y Tl~] 5 A To] 47 ~9~| 4 A 7Z9375 V 1/V2 V1/V2 2A [ T 5 Y J jT , 6.0 March 1988 867 74HC4049 SSI DC C H A R A C T E R IS T IC S FO R 74HC Voltages are -
OCR Scan
7Z93756
Abstract: 4049 CMOS HC 4050 H C D E V IC E *Table 1. Supply Examples NOTE: To determine the noise , MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 54/74H C 4049 M C 54/74H C 4050 H ex B uffers , '¢ Chip Complexity: 36 FETs or 9 Equivalent Gates (4049) 24 FETs or 6 Equivalent Gates (4050) ORDERING , Output Current, per Pin ±25 mA ic c DC Supply Current, ±50 mA PD Power , = V |H °rV |_ |lout| < 4.0 mA Moutl ^ 5 2 mA â in ic c V Maximum Input Leakage -
OCR Scan
MC54/74HC4050 MC14049UB MC14050B 751B-05
Abstract: . E16.3 E16.3 M16.15 M16.15 Pinout CD74HC4049, CD74HC4050 (PDIP, SOIC) TOP VIEW 4049 VCC 1Y 1A 2Y , 10 4Y 9 4A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 1543.3 1 CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 VCC 2 1Y 1Y 3 1A 4 2Y 2Y 5 2A 6 3Y 3Y 7 3A 8 GND 12 5Y 13 NC NC 14 6A 15 6Y 6Y 4049 NC 4050 1 16 11 5A 5Y 10 4Y 9 Harris Semiconductor
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CI 4049 ISO9000
Abstract: IC A L SSI U N IT · IcC cateSory: SSI G E N E R A L D E S C R IP T IO N The 74H C 40 49 is , B " series. It is specified in com pliance w ith JE D E C stan dard no. 7A. The 74H C 4049 provides , G ND = 0 V; T am b = 25 °C; t r = t f = 6ns Note 1. C p o is used to determ ine th e dyna m ic , . V 1 /V 2 vcc [ X ,v [T 14 ÜL 2Y [ T u V 1 /V 2 77] 6 A ü ]« 4049 1?| 5 Y V 1 /V 2 , . December 1990 865 74HC4049 SSI Fig. 5 1npu t p ro te c tio n fo r HC4Q49, Single sided th ic k o -
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TL 4049
Abstract: P ro d u c t - |c lc 20 m A dc - 20 m A dc - M M 4049, M RF534 M RF536 4 .0 G H z ( M in } « , N I M M C 4049 I M M 4049 M R F 63 4 M R F 53 6 I n i ÎH ÎII M A X IM U M R A T IN G , V dc, l£ 01 'CBO - - nAdc ON CHARACTERISTICS D C C u r r e n t G a in (IC 25 m A , dc, l£ 0, f _ pF FUNCTIONAL TESTS M a x im u m A v a ila b le G ain (I q dC {IC 15 m A d c , ) 1.0 GHz) M R F534 M M 4049 MR F536 MAG 10 11.5 8.5 12 13 10 - - dB - FIGURE 1 - -
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MM4049 MMC4049 MRF534 MC4049 mrf536 hfe 4049 MRF536
Abstract: CD74HC4049, CD74HC4050 h a f r f r is S M 0N U T0R E IC D C High Speed CMOS Logic Hex , obtain the variant in the tape and reel. Pinout C D74HC4049, CD74HC4050 (PDIP, SOIC) TOP VIEW 4049 Vcc TŸ 4050 Vcc - u - 4050 4049 E 16] NC NC \2_ 15] 6Y 6Y , AUTIO N : These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling , Functional Diagram 4050 4049 404! 4050 Vcc 1Y 1Y 6Y 2Y 2Y NC 3Y 3Y 5Y -
OCR Scan
Abstract: CD74HC4049, CD74HC4050 h a f r f r is S M 0N U T0R E IC D C High Speed CMOS Logic Hex , obtain the variant in the tape and reel. Pinout CD74HC4049, CD74HC4050 (PDIP, SOIC) TOP VIEW 4049 Vcc 4050 -u - 4050 4049 16] NC Vcc E NC TŸ 1Y \2_ 15 , C AUTIO N : These devices are sensitive to electrostatic discharge. Users should follow proper IC , , CD74HC4050 Functional Diagram 4050 4049 404! 4050 Vcc 1Y 1Y 6Y 2Y 2Y NC 3Y -
OCR Scan
Abstract: OUTPUT BUFFER 6 VOLT REGULATOR CR 3 IN 4 4 5 4 OUF 002 U3 4049 TTL L O DA TA C O M P PL LETE - ) k - í OUTPUT BUFFER U3 4049 12 T TL H=>EN ABLE W R IT E START ENABLE DELAY U3 4049 IN TER N A L W R IT E ' CLO C K (1/2 RA TE OF IN P U T CLOCK) OUTPUT BUFFER CMOS P H A S E ENCODED W R I T E DATA IN' I IS P O S I T I V E T R A N S I T I O N REQUIRED SPECIFICATIONS . TM _ ^ , e m a r C o m p u t e r D e v ic e s , in c . SC A LE DRAWN B Y A PPRO VED BY j p n o p rflT i -
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TA 4049
Abstract: , TSSOP) TOP VIEW 4049 VCC 1Y 1A 2Y 2A 3Y 3A GND 4050 VCC 1 1Y 2 1A 3 2Y 4 2A 5 3Y 6 3A 7 GND 8 4050 16 NC 15 6Y 14 6A 13 NC 12 5Y 11 5A 10 4Y 9 4A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2000,Texas Instruments Incorporated 1 CD54/74HC4049, CD54/74HC4050 Functional Diagram 4050 4049 VCC 2 1Y 1Y 3 1A 4 2Y 2Y 5 2A 6 3Y 3Y 7 3A 8 GND 12 5Y 13 NC NC 14 6A 15 6Y 6Y 4049 NC 4050 1 16 Texas Instruments
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SCHS205B CD74H C4050 CD54HC4049F3A CD54HC4050F3A CD74HC4050PW
Abstract: CD74HC4049, CD74HC4050 (PDIP, SOIC) TOP VIEW 4049 4050 4050 16] NC 15] 6Y 14] 6A 13] NC 12] 5Y TT| 5A 1ÏÏ] 4Y J \4 A Vcc TY 1A Vcc H -u - 4049 NC 6Y 6A NC 5Y 5A 4Y 4A 1Y [ T , sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. C opyright © Harris , -5 V . ±25m A DC V c c or Ground Current, ic e or , a g e . SO IC P ackage -
OCR Scan
Abstract: Gates (4049) 24 FETs or 6 Equivalent Gates (4050) MC54/74HC4049 MC54/74HC4050 J SUFFIX CERAMIC CASE , ±20 ±25 ±50 750 500 - 6 5 to +150 260 300 Unit V V V mA mA mA mW °C °C Vin Vout 'in 'out ic e , n f o r m a t i o n o n t y p ic a l p a r a m e t r i c v a lu e s c a n b e f o u n d in C h a p t , a p a c i t a n c e . Figure 2. Te st C irc u it M O T O R O L A H IG H SPEED C M O S L O G IC , > HC4060 - O - ' TY P IC A L A PPLIC A TIO N S LSTTL to Low-Voltage -
OCR Scan
74hc4049m MC14000-series MC14000- HC4049I 74HCT04
Abstract: MODEL 7908 DTMF RECEIVER ¿Ã'S£ÏÏ0M£ m CORPORATION DESCRIPTION The 7908 is a complete DTMF receiver designed in a 24 pin Dip hybrid I.C. package. No external components are required for operation as a hexadecimal output coded receiver. This unit is capable of detecting all 16 standard DTMF , modified to interface with a Pulse Dialer. The 4049 is used to transform 12V outputs of the 7908 to 5V swings required for the MK5099 Pulse Dialer. TOUCH TONE TO ROTARY CONVERTER 4049 4556 MK 5099 24 21 -
OCR Scan
hl941 Model 7908 b941 IC 4556 L9852 tone Dialer H/B28
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