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ic for jk flip flop 8-pin

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Abstract: are inhibited. A jo in t (JK) input is provided fo r all flip -flop s in this fam ily. The com mon , . This operation is represented sym bolically by AND gates in the logic symbol for each flip -flop . , . definitions PIN NAMES JK Jn, Kn, Jn, Kn CP Cd Sd Q, G DESCRIPTION JK Input Data Inputs Clock Pulse Input , Cd Q p-9 V cc - Pin 14 G N D = Pin 7 V cc = Pin 16 G N D = Pin 8 9001 , JK. 9022 , to satisfy the storage requirem ents of a lo g ic system. All are master/slave JK designs and have ... OCR Scan
datasheet

7 pages,
396.7 Kb

toggle type flip flop ic RS flip flop IC JK flipflop 9001 ic 9022 9022 JK flip flop IC TEXT
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Abstract: PO74G112A PO74G112A www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET , negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation. Logic Block Diagram Pin , NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Maximum Ratings , www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise , DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz ... Potato Semiconductor
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datasheet

6 pages,
1452.08 Kb

JK flip flop IC diagram PO74G112A TEXT
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Abstract: Latch with 5 - D Flip Flop - D Flip Flop with R {reset) - D Flip Flop with S(set) - D Flip Flop with R - D Flip Flop with S - D Flip Flop with R and S - D Flip Flop with R and S - D Flip Flop with 1 clock - JK Flip Flop - JK Flip Flop with R (reset) · JK Flip Flop with S (set) - JK Flip Flop with R - JK Flip Flop with S - JK Flip Flop with S and R - JK Flip Flop with S and R - RS Flip Flop with NAND - RS Flip Flop with NOR 1-3 MA 0250/0400/0800/1200 MACROCELL S e q u e n tia l L o g ic F u n c ... OCR Scan
datasheet

9 pages,
679.38 Kb

toggle type flip flop ic sentry RS FLIP FLOP LAYOUT hc 7400 4017 equivalent internal structure of ic 4017 RS flip flop IC 0250-MA 0800-MA TEXT
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Abstract: slave flip flop Dual J-K flip-flop with clear Dual J-K pos. edge trig. flip flop with preset.+clear Dual J-K Neg edge triggered flip flop with preset and clear Dual J-K Neg edge triggered flip flop , Quad 2-input NOR gate with N-input JK-master-slave flip flop with 2J and K inputs and N-input on slave section JK-master-slave flip flop with N-input on master slave section JK-master-slave flip flop with N-input on master slave section Dual JK-master-slave flip flop with set and reset inputs ... Electro Value
Original
datasheet

5 pages,
68.83 Kb

ic D flip flop 7474 74hc4000 FZH205 SIEMENS siemens FZJ105 FZJ115 7490 Decade Counter 0-99 FZJ125 FZH195 FZL145S FZJ105 74LS104 FZH265B Multiplexer IC 74151 74INTEGRATED FZH205 74INTEGRATED FZH115 74INTEGRATED FZJ111 74INTEGRATED FZK105 74INTEGRATED FZH131 74INTEGRATED fzh261 74INTEGRATED FZH115B 74INTEGRATED 74INTEGRATED 74INTEGRATED TEXT
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Abstract: MITSUBISHI LSTTLs M74LS109AP M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET DESCRIPTION The M74LS109AP M74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered , MITSUBISHI I MITSUBISHI LSTTLs M74LS109AP M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET , LSTTLs M74LS109AP M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS , J-K flip-flop, Sp and Rq must be kept in high. By connecting J and K, this IC can be used as a D-type ... OCR Scan
datasheet

4 pages,
244.28 Kb

toggle type flip flop ic 20-PIN Toggle flip flop IC JK flip flop IC T flip flop pin configuration M74LS109AP RS flip flop IC TEXT
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Abstract: J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , and 256 signal I/O pads. The channelless " sea of gates" architecture of the base arrays allows for , high drive macrocells for criti cal path speed optimization as well as cells to control output slew ... OCR Scan
datasheet

8 pages,
661.5 Kb

SC21C1 SC17C1 Toggle flip flop IC LD-3x siemens pg 740 SC75C1 programmable slew rate control IO scxc1 full adder circuit using nor gates SR flip flop IC pin diagram siemens Nand gate bt10s JK flip flop IC SC11C1 jk flip flop to d flip flop conversion TC110G toshiba tc110g SR flip flop IC siemens master drive circuit diagram TEXT
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Abstract: . For use as a J-K flip -flo p , So and R q must be kept in high. By connecting J and K, this IC can be , MITSUBISHI LSTTLs M 74LS109A 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION The M74LS109AP M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive , ith the fu n ctio n table. By using So and R q , this IC can be made into a direct R-S flip -flo p . , IT IV E EDGE-TRIGGERED FLIP FLOP W IT H SET AND RESET TIMING REQUIREMENTS Symbol tw(TH) tw(So.RD ... OCR Scan
datasheet

4 pages,
228.43 Kb

M74LS109AP flip flop RS M74LS109 74LS109A TEXT
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Abstract: become high and low respectively, irrespective of other inputs. When used as a J-K flip flop, SD should ,  MITSUBISHI HIGH SPEED CMOS M74HC113P M74HC113P DUAL J-K FLIP-FLOP WITH SET PIN CONFIGURATION (TOP , integrated circuit consisting of two negative-edge triggered J-K flip flops with independent control inputs , edge-triggered J-K flip flops, each circuit with independent clock input CK, direct set input SD, and both inputs , no-load conditions, (per flip flop) The power dissipated during operation under no-load conditions is ... OCR Scan
datasheet

5 pages,
118.14 Kb

M74HC113P M74HC113 74LS113 4000B "J-K Flip flops" JK flip flop IC J-K Flip flops TEXT
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Abstract: simultaneously become high, the condition of Q and Q canncrt be predetermined. When used as a J-K flip flop, Sq , D-type flip flop. 2-66 This Material MITSUBISHI HIGH SPEED CMOS M74HC109P M74HC109P DUAL J-K FLIP-FLOP WITH , 74LS109 74LS109. The M74HC109 M74HC109 contains two edge-triggered J-K flip flops, each circuit with Independent clock , accordance with the function table given. Use of SD and Rd permits direct R-S flip flop operation. When SD , operation supply current under no-load conditions, (per flip flop) The power dissipated during operation ... OCR Scan
datasheet

5 pages,
125.6 Kb

RS flip flop M74HC109 74LS109 4000B M74HC109P Toggle flip flop IC RS flip flop cmos JK flip flop IC RS flip flop IC TEXT
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Abstract: MITSUBISHI LSTTLs M74LS76AP M74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET DESCRIPTION The M74LS76AP M74LS76AP is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip , cannot be anticipated. For use as a J-K flip -flo p , S q and R p must be kept in high. Also available is , M 74LS76AP 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET ABSOLUTE MAXIMUM RATINGS , 74LS76AP 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS ( V c c = S ... OCR Scan
datasheet

4 pages,
242.26 Kb

toggle type flip flop ic M74LS112AP 20-PIN JK flip flop IC diagram M74LS76AP ic for jk flip flop 8-pin 74LS76AP TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 2002 Date Update: 09 Document Format and Raw Text Format M54HC76 M54HC76 M74HC76 M74HC76 October 1992 DUAL J-K FLIP FLOP WITH FUNCTION COMPATIBLE WITH 54/74LS76 54/74LS76 The M54/74HC76 M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP fabricated in following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC76 M54/M74HC76 5/11 SWITCHING
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2002-v1.htm
STMicroelectronics 02/04/1999 8.61 Kb HTM 2002-v1.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Datasheet DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER CODES speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C 2 MOS technology. It has the same obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC73 M54/M74HC73 5
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999.htm
STMicroelectronics 20/10/2000 10.88 Kb HTM 1999.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1891 Date Update: 09 Document Format and Raw Text Format M54HC112 M54HC112 M74HC112 M74HC112 October 1992 DUAL J-K FLIP FLOP dual JK flip-flop features indi- vidual J, K, clock, and asynchronous set and clear inputs for each M74HC112C1R M74HC112C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1891-v1.htm
STMicroelectronics 02/04/1999 8.79 Kb HTM 1891-v1.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date Update: 09 Document Format and Raw Text Format M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH COMPATIBLE WITH 54/74LS73 54/74LS73 The M54/74HC73 M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999-v1.htm
STMicroelectronics 02/04/1999 8.48 Kb HTM 1999-v1.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1999 Date Update: 09 Document Format and Raw Text Format M54HC73 M54HC73 M74HC73 M74HC73 October 1992 DUAL J-K FLIP FLOP WITH COMPATIBLE WITH 54/74LS73 54/74LS73 The M54/74HC73 M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in can be obtained by the following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1999-v2.htm
STMicroelectronics 14/06/1999 8.44 Kb HTM 1999-v2.htm
ST | DUAL J-K FLIP FLOP WITH PRESET M74HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET Document Number: 1892 Date Update: 09/04/94 Pages Text Format M54HC113 M54HC113 M74HC113 M74HC113 October 1992 DUAL J-K FLIP FLOP WITH PRESET B1R (Plastic /74LS113 /74LS113 The M54/74HC113 M54/74HC113 is a high speed CMOS DUAL J- K FLIP FLOP WITH PRESET fabricated in silicon gate V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC113 M54/M74HC113 5/11 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1892-v1.htm
STMicroelectronics 02/04/1999 8.67 Kb HTM 1892-v1.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 2002 Date Update: 09 Document Format and Raw Text Format M54HC76 M54HC76 M74HC76 M74HC76 October 1992 DUAL J-K FLIP FLOP WITH FUNCTION COMPATIBLE WITH 54/74LS76 54/74LS76 The M54/74HC76 M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP fabricated in following equation. I CC (opr) = C PD w V CC w f IN + I CC /2 (per FLIP/FLOP) M54/M74HC76 M54/M74HC76 5/11 SWITCHING
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2002-v2.htm
STMicroelectronics 14/06/1999 8.57 Kb HTM 2002-v2.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Datasheet DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC76 M74HC76 M54HC76 M54HC76 M74HC76 M74HC76 October 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER CODES speed CMOS DUAL J-K FLIP FLOP fabricated in silicon gate C 2 MOS tech- nology. It has the same high /2 (per FLIP/FLOP) M54/M74HC76 M54/M74HC76 5/11 SWITCHING CHARACTERISTICS TEST WAVEFORM INPUT TRANSITION TIME IS
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2002.htm
STMicroelectronics 20/10/2000 11.01 Kb HTM 2002.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Datasheet DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M54HC112 M54HC112 M74HC112 M74HC112 October 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 54/74LS112 The M54/74HC112 M54/74HC112 is a high speed CMOS DUAL J-K JK flip-flop features indi- vidual J, K, clock, and asynchronous set and clear inputs for each
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1891-v3.htm
STMicroelectronics 25/05/2000 10.58 Kb HTM 1891-v3.htm
ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR M74HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR Document Number: 1891 Date Update: 09 Document Format and Raw Text Format M54HC112 M54HC112 M74HC112 M74HC112 October 1992 DUAL J-K FLIP FLOP dual JK flip-flop features indi- vidual J, K, clock, and asynchronous set and clear inputs for each M74HC112C1R M74HC112C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/1891-v2.htm
STMicroelectronics 14/06/1999 8.75 Kb HTM 1891-v2.htm