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HPA00614DRCR Texas Instruments 750mA SINGLE-CHIP Li-Ion/Li-Pol CHARGE MANAGEMENT IC with Thermal Regulation 10-SON 0 to 125
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ic for jk flip flop 8-pin

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: are inhibited. A jo in t (JK) input is provided fo r all flip -flop s in this fam ily. The com mon , . This operation is represented sym bolically by AND gates in the logic symbol for each flip -flop . , . definitions PIN NAMES JK Jn, Kn, Jn, Kn CP Cd Sd Q, G DESCRIPTION JK Input Data Inputs Clock Pulse Input , Cd Q p-9 V cc - Pin 14 G N D = Pin 7 V cc = Pin 16 G N D = Pin 8 9001 , JK. 9022 , to satisfy the storage requirem ents of a lo g ic system. All are master/slave JK designs and have -
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JK flip flop IC RS flip flop IC 9022 ic 9022 JK flipflop 9001 toggle type flip flop ic 9000DC 9020DC 9022DC 9000FC 9001FC 9020FC
Abstract: PO74G112A www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET , negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation. Logic Block Diagram Pin , NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Maximum Ratings , www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise , DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Potato Semiconductor
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T flip flop pin configuration JK flip flop IC diagram 750MH 5000-VH A114-A 200-VM A115-A PO74G112ASU
Abstract: Latch with 5 - D Flip Flop - D Flip Flop with R {reset) - D Flip Flop with S(set) - D Flip Flop with R - D Flip Flop with S - D Flip Flop with R and S - D Flip Flop with R and S - D Flip Flop with 1 clock - JK Flip Flop - JK Flip Flop with R (reset) · JK Flip Flop with S (set) - JK Flip Flop with R - JK Flip Flop with S - JK Flip Flop with S and R - JK Flip Flop with S and R - RS Flip Flop with NAND - RS Flip Flop with NOR 1-3 MA 0250/0400/0800/1200 MACROCELL S e q u e n tia l L o g ic F u n c -
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internal structure of ic 4017 4017 equivalent hc 7400 RS FLIP FLOP LAYOUT sentry 0250-MA 0800-MA 0250-M 0400-M 0800-M
Abstract: slave flip flop Dual J-K flip-flop with clear Dual J-K pos. edge trig. flip flop with preset.+clear Dual J-K Neg edge triggered flip flop with preset and clear Dual J-K Neg edge triggered flip flop , Quad 2-input NOR gate with N-input JK-master-slave flip flop with 2J and K inputs and N-input on slave section JK-master-slave flip flop with N-input on master slave section JK-master-slave flip flop with N-input on master slave section Dual JK-master-slave flip flop with set and reset inputs Electro Value
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FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 74INTEGRATED 16-DIL
Abstract: MITSUBISHI LSTTLs M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET DESCRIPTION The M74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered , MITSUBISHI I MITSUBISHI LSTTLs M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET , LSTTLs M74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS , J-K flip-flop, Sp and Rq must be kept in high. By connecting J and K, this IC can be used as a D-type -
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20-PIN Toggle flip flop IC 14-PIN 16-PIN
Abstract: J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , and 256 signal I/O pads. The channelless " sea of gates" architecture of the base arrays allows for , high drive macrocells for criti cal path speed optimization as well as cells to control output slew -
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TC110G siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 M33S004
Abstract: . For use as a J-K flip -flo p , So and R q must be kept in high. By connecting J and K, this IC can be , MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive , ith the fu n ctio n table. By using So and R q , this IC can be made into a direct R-S flip -flo p . , IT IV E EDGE-TRIGGERED FLIP FLOP W IT H SET AND RESET TIMING REQUIREMENTS Symbol tw(TH) tw(So.RD -
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74LS109AP M74LS109 flip flop RS 0013S
Abstract: become high and low respectively, irrespective of other inputs. When used as a J-K flip flop, SD should ,  MITSUBISHI HIGH SPEED CMOS M74HC113P DUAL J-K FLIP-FLOP WITH SET PIN CONFIGURATION (TOP , integrated circuit consisting of two negative-edge triggered J-K flip flops with independent control inputs , edge-triggered J-K flip flops, each circuit with independent clock input CK, direct set input SD, and both inputs , no-load conditions, (per flip flop) The power dissipated during operation under no-load conditions is -
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M74HC113 4000B 74LS113 J-K Flip flops I-85C
Abstract: simultaneously become high, the condition of Q and Q canncrt be predetermined. When used as a J-K flip flop, Sq , D-type flip flop. 2-66 This Material MITSUBISHI HIGH SPEED CMOS M74HC109P DUAL J-K FLIP-FLOP WITH , 74LS109. The M74HC109 contains two edge-triggered J-K flip flops, each circuit with Independent clock , accordance with the function table given. Use of SD and Rd permits direct R-S flip flop operation. When SD , operation supply current under no-load conditions, (per flip flop) The power dissipated during operation -
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RS flip flop cmos RS flip flop
Abstract: MITSUBISHI LSTTLs M74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET DESCRIPTION The M74LS76AP is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip , cannot be anticipated. For use as a J-K flip -flo p , S q and R p must be kept in high. Also available is , M 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET ABSOLUTE MAXIMUM RATINGS , 74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET AND RESET TIMING REQUIREMENTS ( V c c = S -
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M74LS112AP
Abstract: . K 4 Sam e load circuit as above! Lzf R eset 1. Measurement made for each flip flop. 2 , generator |Zout=50n K Q R eset T ~ Notes 1. Measurement made for each flip flop. 2. CL includes , LS TTL DN74LS Series DN74LS78 DN74LS78 Dual J-K F lip -F lo p s (with Set,Com m on R eset and Common Clock) D escription P-1 DN74LS78 contains two negative-edge triggered J-K flip-flop , and Q outputs Wide operating temperature range (Ta = - 2 0 to +75°C) 14-pin plastic D IL package -
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ma161 SO-14D MA161
Abstract: JK JK JK JK JK JK Flip Flip Flip Flip Flip Flip Flip Flop Flop Flop Flop Flop , Flop - D Flip Flop w ith R (reset) - D Flip Flop w ith SJset) - D Flip Flop w ith R - D Flip Flop w ith S - D Flip Flop w ith R and S - D Flip Flop w ith R and S - D Flip Flop w ith 1 clock 2 2 , and R - RS Flip Flop w ith NAND - RS Flip Flop w ith NOR 3 2 5 2 2 MA 0250/0400/0800 , ) Sequential Logic Functions (cont'd) - 68 MSI functions Toggle Flip Flop w ith asynchronous -
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Abstract: _ p u tQ Zout=50fl I- ¡ 3 rCl nr 1. Measurement made for each flip flop. 2. CL includes , . Measurement made for each flip flop. 2. CL includes probe and tool floating capacitance. 3. Diodes are all , LS TTL DN74LS Series DN74LS113 DN74LS113 l^7^iS)3 P-1 Dual J-K Negative Edge-Triggered Flip-Flops (with Set) Description DN74LS113 contains two negative-edge triggered J-K flipflop , · · Negative-edge trigger Independent input and output terminals for each flip-flop Direct-coupled -
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MAI61
Abstract: MITSUBISHI LSTTLs M 7 4LS 113 A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET DESCRIPTION The M 74LS113A P is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits c o n ta in in g 2 J -K PIN CONFIGURATION (TOP VIEW) w ith discrete te rm in als , EDGE-TRIGGERED FLIP FLOP W ITH SET ABSOLUTE MAXIMUM RATINGS ( T Sym bol P a ra m e te r S u p p ly vo lta g e , EDGE-TRIGGERED FLIP FLOP WITH SET Note 4 Measurement circuii Vcc ' 1) The pulse generator (PG) has the fol -
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tp 2123
Abstract: 1. M easurem ent m ade for each flip flop. 2. C L includes probe and tool floating capacitance. 3 , easurem ent m ade for each flip flop. 2. Cj_ includes probe and tool floating capacitance. 3. Diodes are , LS TTL DN74LS Series DN74LS114 DN74LS114 Description ivj'7q_ uSiiqP-1 Dual J-K , negative-edge triggered J-K flipflop circuits w ith com m on clock-CP and direct-coupled reset input term inals , package P -4 Logic diagram (1/2) 14-p in P an a fla t package (S O -1 4 D ) Pin configuration -
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Abstract: TTL INTEGRATED CIRCUITS DUAL JK MASTER/SLAVE FLIP FLOP GENERAL DESCRIPTION The flip flops described herein are TTI, (Transistor-Transistor Logic) dual ]K Master/Slave flip flops. Asynchrorous CLEAR inputs are provided on the flip flops The device is totally monolithic and designed for use in high speed , after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the , one pin is used for data entry, fully asynchronous (both PRESET and CLEAR) capability can be provided -
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ic D flip flop 7474 T flip flop IC ic 7474 features of ic 7474 7474 j-k flip flop pin IC 7474
Abstract: . Measurement circuit Input Inputs | Outputs | 1. Measurement made for each flip flop. 2. CL includes , each flip flop. 2. CL includes probe and tool floating capacitance. duty cycle 50% 2. When , I LS TTL DN74LS Series DN74LS113 DN74LS113 Dual J-K Negative Edge-Triggered Flip-Flops (with Set) I Description P-1 DN74LS113 contains two negative-edge triggered J-K flipflop , â'¢ Negative-edge trigger â'¢ Independent input and output terminals for each flip-flop â -
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Abstract: RESET D-TYPE FLIP FLOP D-TYPE FLIP FLOP WITH SET D-TYPE FLIP FLOP WITH RESET D-TYPE FLIP FLOP WITH SET AND RESET J-K FLIP FLOP J-K FLIP FLOP WITH SET J-K FLIP FLOP WITH RESET J-K FLIP FLOP WITH SET AND , Ceram ic FLA T ) P lastic P lastic P lastic Can not be used for RP3G01 4 0 -P IN PLASTIC , N T h e R P 3 G 01 and R P 3 G 0 2 a r e A n a lo g /D ig ita l se m ic u s to m g a te a r r a y s fa b r ic a te d w ith m e ta l g a te B i-C M O S p ro cess. T h e R P 3 G 0 1 and R P 3 G 0 2 c o n -
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ic 74226 jk flip flop 74103 7471 rs flip flop 4011 flip flop IC 7400 SERIES list 7414 NOT gate ic 3W1X879 00GG71S
Abstract: . When used as a J-K flip flop, RD should be maintained at high-level. M74HC107 is the same functions , IC calculated from operation supply current under no-load conditions, (per flip flop) The power , 74LS107. The M74HC107 contains two edge-triggered J-K flip flops, each circuit with independent clock ,  s* si""' M*r,te MITSUBISHI HIGH SPEED CMOS M74HC107P DUAL J-K FLIP-FLOP WITH RESET DESCRIPTION The M74HC107 is a semiconductor integrated circuit consisting of two negative-edge triggered J-K -
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pin configuration 74LS107 74LS107* pin and application M74HC73P JOPR 15
Abstract: LDF J-K flip flop with reset _ J-K flip flop w ith set/reset Toggle flip flow with enable/reset , D-type flip flop with set/reset and L S S D J-K flip flop with reset and LSSD J-K flip flop with set , 75000. 77 STANDARD NUMBER OF POWER-SUPPLY PINS AND STANDARD PIN LAYOUT FOR EACH PACKAGE Package , standard pin layout of each package is determined for the ceramic/crystal oscillator terminals X1 and X 2 , reset D -type flip flo p w ith set/reset J-K flip flo p 8 8 1-51 DF 9 8 1-52 JK -
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MSM70000 function of latch ic 74373 full adder using ic 74138 pins and their function in ic 74163 encoder IC 74147 74373 cmos dual s-r latch MSM7000 MSM71000/72000/73000/74000 MSIW71000 MSM74000
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