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i960JX

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Abstract: different PMCONs (PMCONs are the i960JX's Physical Memory Configuration registers - see i960JX User , appropriate i960Jx's PMCON register to the desired bus width, and mapping the appropriate Device n Address , System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary , i960JX family of CPUs · 16-33MHz bus frequency · Flexible DRAM controller - Page mode and EDO DRAMs - , 160 PQFP i960JX External Agent AD Bus 32 373 Address & Control DRAM ADBusReq ... Galileo Technology
Original
datasheet

67 pages,
522.42 Kb

QS3257 PCMCIA SRAM Card MON960 GT-32090 TEXT
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Abstract: V96SSC V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 ® Jx/Sx and PowerPCTM401Gx PROCESSORS BLOCK DIAGRAM · Glueless interface between Intel's i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices (Fast time-to-market) · Support for boot PROM devices · High-performance , Controller simplifies the design of systems based on Intel's i960Jx and i960Sx microprocessors. By using the , directly connects the i960Sx or i960Jx processor to DRAM arrays, from 128KByte to 128MByte. The fully ... V3 Semiconductor
Original
datasheet

2 pages,
396.18 Kb

V96SSC I960SX TEXT
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Abstract: 32bit devices in the same system, using different PMCONs (PMCONs are the i960JX's Physical Memory , -32090 System Controller For I960JX Processors {Si n Galileo Technology, Inc. OVERVIEW The GT-32090 GT-32090 is a low cost, highly integrated single-chip System Controller for the i960Jx Family It provides high , Card B Misc. Rst* JTAG SCAN JTMS JTRst* JTDO GT-32090 GT-32090 System Controller For I960JX , device on the AD bus. _ Galileo Technology, Inc. GT-32090 GT-32090 System Controller For I960JX Processors ... OCR Scan
datasheet

67 pages,
1364.76 Kb

TEXT
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Abstract: and i960Jx based designs · Two 32-bit general purpose timers · Pulse width modulation capability , systems based on i960Sx, i960Jx or PPC401Gx embedded microprocessors. The V96SSC V96SSC replaces many lower , Mode Boot Address Description 10 i960Jx (32 bit bus) A[31, 26:24]="1110" 32-bit data , i960Jx (16 bit bus) A[31, 26:24]="1110" 32-bit data bus, BE3 and BE0 valid for current cycle , i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the ... V3 Semiconductor
Original
datasheet

20 pages,
157.79 Kb

V96SSC-33LP V96SSC V961PBC V960PBC PPC401GF ppc401 heartbeat counter TEXT
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Abstract: or disable the Secondary CPU self-test. The Galileo-5 is shipped with a 33MHz i960Jx. 1.3 CPU , 32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE , standalone system - As slave card in a standard ISA slot · Several CPU options - Intel i960Jx 32-bit CPUs , - Message passing protocol between the i960Jx and the Host CPU - May be used for software , Expansion AD Bus i960Jx CPU P2 AD Bus DRAM Control & Addr OSC DRAM SIMMs Flash 373 ... Original
datasheet

58 pages,
565.82 Kb

0x83000 JS66-JS67 JS109 JS76-JS82 TP1-TP11 J551 JS129-JS136 JS84 74LS373SC JS107 JS31-JS32 JS108 JS-105 edo dram 72-pin simms 64mb JS98 28f040 js83 TEXT
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Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · Configurable for primary master, bus master or , -bit multiplexed local bus applications to the PCI bus. V350EPC V350EPC directly connects to i960Jx or i960Sx processors , versions. i960Jx CPU V96BMC V96BMC MEMORY CONTROL D R A M ROM TYPICAL APPLICATION V350EPC V350EPC LOCAL , 1: Product Codes Product Code V350EPC-33 V350EPC-33 REV A0 V350EPC-40 V350EPC-40 REV A0 Processors i960Jx/Sx i960Jx/Sx , state during reset. b. Applies to i960Sx mode. c. Applies to i960Jx mode. 2.1 Test Mode Pins ... V3 Semiconductor
Original
datasheet

18 pages,
95.61 Kb

I960SX V350EPC V961PBC V960PBC TEXT
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Abstract: . i960Jx Processor Interface ÂDS I/04 z Asserted low to indicate the beginning of a bus cycle. RDYRCV 1/04 z Local Bus data ready. P_HOLD 04 L i960Jx HOLD signal. Primary Local , i960Jx HOLD signal. Secondary Local bus hold request: asserted by the chip to initiate a local bus master cycle. PJHOLDA I i960Jx HOLDA signal. Primary Local bus hold acknowledge. S_HOLDA I LPAR[3:0] I/04 Z Local bus parity. i960Jx HOLDA signal. Secondary Local bus hold ... OCR Scan
datasheet

27 pages,
504.79 Kb

PJ3N TEXT
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Abstract: · Fastest time to market for i960Sx and i960Jx based designs The V96SSC V96SSC High-Integration System Controller is a single-chip device that simplifies the design of systems based on i960Sx, i960Jx or PPC401Gx , V96SSC V96SSC Table 2: BTYPE[1:0] Pin Decoding BTYPE[1:0] 10 CPU Mode i960Jx (32 bit bus) i960Jx (16 bit bus , order address inputs. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC V96SSC latches the high order address signals internally on the assertion of ALE ... V3 Semiconductor
Original
datasheet

22 pages,
157.1 Kb

PPC401GF TEXT
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Abstract: interface to Intel's i960Jx and IBM's PowerPC TM 401Gx processors · On-the-fly byte order (endian , bus. V350EPC V350EPC directly connects to i960Jx or i960Sx proces sors with out a ny glue logic . Mi ni ma l , i960Jx CPU D R A M V350EPC V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 Semiconductor Corp , A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 V350EPC-40 REV A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 40MHz 2.0 Pin Description and ... V3 Semiconductor
Original
datasheet

18 pages,
117.17 Kb

V96BMC V961PBC V960PBC V350EPC-40 V350EPC-33 V350EPC AD30 AD29 TEXT
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Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · On-the-fly byte order (endian) conversion · , bus. V350EPC V350EPC directly connects to i960Jx or i960Sx processors without any glue logic. Minimal glue , MEMORY CONTROL i960Jx CPU D R A M V350EPC V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 , Codes Product Code Processors Bus Type Package Frequency V350EPC-33 V350EPC-33 REV A0 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 V350EPC-40 REV A0 i960Jx/Sx 32/16 ... V3 Semiconductor
Original
datasheet

18 pages,
124.44 Kb

V96BMC V961PBC V960PBC V350EPC-40 V350EPC-33 V350EPC AD30 AD29 TEXT
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Abstract: to the i960Jx Microprocessor User's Manual, Table 11-2). In the current implementation, of both the ... Intel
Original
datasheet

47 pages,
373.51 Kb

intel DOC 80960JF 80960JD 80960JA 272852 80960JA/JF/JD TEXT
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Abstract: SALIGN is an implementation-specific parameter. For the i960Jx processors, SALIGN = 1, so stack frames , implementations. On the i960Jx processors, interrupts may also be requested in software with the sysctl ... Intel
Original
datasheet

6 pages,
58.03 Kb

microprocessor architecture programming 80960JT I960 micro instruction set of I960 hx TEXT
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Abstract: # is asserted. The i960Jx processor does not assert LOCK# except while a read-modify-write operation , of atmod completes. 1.3 Bus Applications The i960Jx microprocessor is a cost-effective , potential 80960Jx systems. These diagrams do not represent any particular i960Jx processor- based , i960Jx processor systems, the 80960Jx is the primary master of the local bus. A number of memory and I/O ... Intel
Original
datasheet

10 pages,
38.76 Kb

Intel AP-693 embedded microprocessors D310 28F800F3 28F160F3 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
Galileo Technology: GT-32090 GT-32090 High-Performance i960Jx System : Integrated system controller for embedded applications Supports the i960JX family of CPUs Ideal system controller for i960Jx/Galaxy™ switch applications 16-33MHz The GT-32090 GT-32090 has a direct interface to the Intel family of i960JX processors. It has the 3. High performance glueless support of all members of the i960JX family.
/datasheets/files/scantec/galileo/www/tbriefs/32090tb.htm
Scantec 20/04/1998 14.25 Kb HTM 32090tb.htm
Galileo Technology: Galileo-5: ISA Based 32-bit i960JX Evaluation & Development System for GT-32090 GT-32090 Galileo-5: ISA Based 32-bit i960JX Evaluation & Development System for GT-32090 GT-32090 Intel i960JX CPUs Debug monitor software (MON960 MON960 standard ISA slot Several CPU options Intel i960JX
/datasheets/files/scantec/galileo/www/tbriefs/gal5tb.htm
Scantec 20/04/1998 9.97 Kb HTM gal5tb.htm
Galileo Technology: Galileo Announces i960Jx System Controller GALILEO TECHNOLOGY INTRODUCES SYSTEM CONTROLLER FOR i960 EMBEDDED DESIGNS Under $15 Chip Supports Intel's i960JX Family of CPUs FOR IMMEDIATE RELEASE System Controller supports the Intel i960JX family of 32-bit embedded RISC processors. pleased to support the i960JX family, since its attractive cost/ performance and pin-compatible
/datasheets/files/scantec/galileo/www/news/3290_100295.htm
Scantec 20/04/1998 12.01 Kb HTM 3290_100295.htm
i960Jx processors have the capability to program two specific contiguous regions in their memory space as document: i960Jx Microprocessor User's Manual, Order #272483 Determining Starting
/datasheets/files/intel/design/i960/technote/2458-v7.htm
Intel 30/04/1998 8.83 Kb HTM 2458-v7.htm
Controller MIPS 4600/4650/4700 Intel i960Jx System Controllers GT-32090 GT-32090 High-Performance System Controller for i960Jx Processors Click here for our
/datasheets/files/scantec/galileo/www/prodidx.htm
Scantec 20/04/1998 10.36 Kb HTM prodidx.htm
MIPS 4600/4650/4700 Intel i960Jx System Controllers GT-32090 GT-32090 High-Performance System Controller for i960Jx Processors © Galileo Technology 1997
/datasheets/files/scantec/galileo/www/coreidx.htm
Scantec 20/04/1998 6.33 Kb HTM coreidx.htm
individual workstations; a i96OHx or i960Jx host processor for network management, specifically RMON support could be implemented. The i960Jx processor, by comparison, allowed for cost-sensitive designs to forgo introduced the i960RP processor, which included not only an i960Jx processor, but also two PCI interfaces and (over $75 in components.) Of course, the i960RP is more expensive than an i960Jx (by about $30 in 10k
/datasheets/files/scantec/plx/press/articles/ee_times/ethernet.htm
Scantec 22/05/1998 9.67 Kb HTM ethernet.htm
transfers, although the i960Jx does not have bus pipelining capability. The 80960Jx products do not occupy existing design based on 80960Cx processors: · The i960Jx device extends the use of the READY# pin to 80960Jx. Bus Arbitration The HOLD/HOLDA protocol provides that the i960Jx processor will be sampled on the rising edge of CLKIN. DMA The i960Jx processor does not have
/datasheets/files/intel/design/i960/technote/2399-v1.htm
Intel 10/02/1998 16.1 Kb HTM 2399-v1.htm
Galileo Technology: Intel i960® Processor Based 24-Port Switch Links to Intel Web Site Intel's i960® Processor Based 24-Port Switch A Comprehensive Reference Design 24-Port Ethernet Switch Reference Design Can switch >700Kpps (full-duplex, Unicast) Full schematics and documentation (more than 200 pages!) Uses i960Jx or i960Hx processor for management
/datasheets/files/scantec/galileo/www/library/other/24switch.htm
Scantec 20/04/1998 4.33 Kb HTM 24switch.htm
processor busses are capable of high bandwidth burst transfers, although the i960Jx does not have bus : The i960Jx device extends the use of the READY# pin to control the number of recovery (Tr) states Arbitration The HOLD/HOLDA protocol provides that the i960Jx processor cannot pass directly from a Td bus CLKIN. DMA The i960Jx processor does not have a DMA unit. If your i960Cx design uses DMA
/datasheets/files/intel/products one/design/i960/technote/2399.htm
Intel 02/05/1999 16.79 Kb HTM 2399.htm