500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : MI-960 Supplier : ADLINK Technology Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : RW-EMB-Q170B-PHI-96-0800-001 Supplier : AAEON Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : RW-EMB-Q170B-PHI-96-0800-002 Supplier : AAEON Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : YI9601510000G Supplier : Amphenol Manufacturer : Avnet Stock : - Best Price : €15.8316 Price Each : €19.7895
Part : YI96015100J0G Supplier : Amphenol Manufacturer : Avnet Stock : - Best Price : $19.5534 Price Each : $21.2163
Part : STI960 Supplier : - Manufacturer : Newark element14 Stock : 5 Best Price : $199.9900 Price Each : $199.9900
Part : YI96015100J0G Supplier : Amphenol Manufacturer : Heilind Electronics Stock : - Best Price : - Price Each : -
Shipping cost not included. Currency conversions are estimated. 

i960JX

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: different PMCONs (PMCONs are the i960JX's Physical Memory Configuration registers - see i960JX User , appropriate i960Jx's PMCON register to the desired bus width, and mapping the appropriate Device n Address , System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary , i960JX family of CPUs · 16-33MHz bus frequency · Flexible DRAM controller - Page mode and EDO DRAMs - , 160 PQFP i960JX External Agent AD Bus 32 373 Address & Control DRAM ADBusReq Galileo Technology
Original
GT-32090 AD2699 ad2690 MON960 PCMCIA SRAM Card QS3257 960JX 16-33MH 128MB 256K-4M 160-P
Abstract: V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 ® Jx/Sx and PowerPCTM401Gx PROCESSORS BLOCK DIAGRAM · Glueless interface between Intel's i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices (Fast time-to-market) · Support for boot PROM devices · High-performance , Controller simplifies the design of systems based on Intel's i960Jx and i960Sx microprocessors. By using the , directly connects the i960Sx or i960Jx processor to DRAM arrays, from 128KByte to 128MByte. The fully V3 Semiconductor
Original
I960SX PCTM401G 2348G
Abstract: 32bit devices in the same system, using different PMCONs (PMCONs are the i960JX's Physical Memory , -32090 System Controller For I960JX Processors {Si n Galileo Technology, Inc. OVERVIEW The GT-32090 is a low cost, highly integrated single-chip System Controller for the i960Jx Family It provides high , Card B Misc. Rst* JTAG SCAN JTMS JTRst* JTDO GT-32090 System Controller For I960JX , device on the AD bus. _ Galileo Technology, Inc. GT-32090 System Controller For I960JX Processors -
OCR Scan
Abstract: and i960Jx based designs · Two 32-bit general purpose timers · Pulse width modulation capability , systems based on i960Sx, i960Jx or PPC401Gx embedded microprocessors. The V96SSC replaces many lower , Mode Boot Address Description 10 i960Jx (32 bit bus) A[31, 26:24]="1110" 32-bit data , i960Jx (16 bit bus) A[31, 26:24]="1110" 32-bit data bus, BE3 and BE0 valid for current cycle , i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V3 Semiconductor
Original
heartbeat counter AD1065 ppc401 PPC401GF V960PBC V961PBC PPC401G
Abstract: or disable the Secondary CPU self-test. The Galileo-5 is shipped with a 33MHz i960Jx. 1.3 CPU , 32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE , standalone system - As slave card in a standard ISA slot · Several CPU options - Intel i960Jx 32-bit CPUs , - Message passing protocol between the i960Jx and the Host CPU - May be used for software , Expansion AD Bus i960Jx CPU P2 AD Bus DRAM Control & Addr OSC DRAM SIMMs Flash 373 -
Original
js83 28f040 JS98 edo dram 72-pin simms 64mb JS-105 JS108 256KB
Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · Configurable for primary master, bus master or , -bit multiplexed local bus applications to the PCI bus. V350EPC directly connects to i960Jx or i960Sx processors , versions. i960Jx CPU V96BMC MEMORY CONTROL D R A M ROM TYPICAL APPLICATION V350EPC LOCAL , 1: Product Codes Product Code V350EPC-33 REV A0 V350EPC-40 REV A0 Processors i960Jx/Sx i960Jx/Sx , state during reset. b. Applies to i960Sx mode. c. Applies to i960Jx mode. 2.1 Test Mode Pins V3 Semiconductor
Original
Abstract: . i960Jx Processor Interface Ã'DS I/04 z Asserted low to indicate the beginning of a bus cycle. RDYRCV 1/04 z Local Bus data ready. P_HOLD 04 L i960Jx HOLD signal. Primary Local , i960Jx HOLD signal. Secondary Local bus hold request: asserted by the chip to initiate a local bus master cycle. PJHOLDA I i960Jx HOLDA signal. Primary Local bus hold acknowledge. S_HOLDA I LPAR[3:0] I/04 Z Local bus parity. i960Jx HOLDA signal. Secondary Local bus hold -
OCR Scan
PJ3N V96DPC VLJ100A V292BMC VU1150A V962PBC V292PBC
Abstract: · Fastest time to market for i960Sx and i960Jx based designs The V96SSC High-Integration System Controller is a single-chip device that simplifies the design of systems based on i960Sx, i960Jx or PPC401Gx , V96SSC Table 2: BTYPE[1:0] Pin Decoding BTYPE[1:0] 10 CPU Mode i960Jx (32 bit bus) i960Jx (16 bit bus , order address inputs. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC latches the high order address signals internally on the assertion of ALE V3 Semiconductor
Original
PC401TMG
Abstract: interface to Intel's i960Jx and IBM's PowerPC TM 401Gx processors · On-the-fly byte order (endian , bus. V350EPC directly connects to i960Jx or i960Sx proces sors with out a ny glue logic . Mi ni ma l , i960Jx CPU D R A M V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 Semiconductor Corp , A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 REV A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 40MHz 2.0 Pin Description and V3 Semiconductor
Original
AD29 AD30
Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · On-the-fly byte order (endian) conversion · , bus. V350EPC directly connects to i960Jx or i960Sx processors without any glue logic. Minimal glue , MEMORY CONTROL i960Jx CPU D R A M V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 , Codes Product Code Processors Bus Type Package Frequency V350EPC-33 REV A0 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 REV A0 i960Jx/Sx 32/16 V3 Semiconductor
Original
Abstract: recognized: i960Sx and i960Jx. Because the bus type is dynam ically detected, the V96SSC may be used in , ific to e a ch p ro c e s s o r: 0 x0 0 0 0 .0 0 0 0 fo r th e i9 6 0 S x, OxFEFF.OOOO for the i960Jx. , to 25MHz · Low cost 100-pin EIAJ PQFP package · Fastest time to market for i960Sx and i960Jx based , directly to ¡960Sx and i960Jx processors. No "glue logic" is required. Care was taken during the design of , inputs. The ¡960Jx p ro ce sso r uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus -
OCR Scan
V96SSC25LP 10GME00 0DDD720 00007BS
Abstract: â'¢ Low cost 100-pin EIAJ PQFP package â'¢ Fastest tim e to market for i960Sx and i960Jx based , 10 i960Jx (32 bit bus) A [3 1 , 26:24]=â'1110â' 32-bit data bus, B t[3:0J valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock 11 i960Jx (16 bit bus) A [3 1 , i960Jx bus accesses, the V96SSC latches the high order address signals internally on the assertion of , 32-bit i960Jx system s, the internal registers are typically accessed in a 32 bit region w here -
OCR Scan
Abstract: Galileo-5 Benchmark Results 17 Jan 1997 Summary The following results are a summary of the detailed output of the benchmark tests below. All Benchmarks were performed with compiler optimization and with a standard 33Mhz I960jx Galileo-5 Board. Linpack-: 0.37 Mflops Dhrystones: 24 Dhrystones per second Linpack- Benchmark =>do Downloading - Download complete -Start address is : 00008000 =>go , seconds Repeat seconds Average Galileo-5 i960jx 33 On ic960 -AJA -Tgal5 -DSP -DROLL linpack-.c -
Original
54565 ic960
Abstract: , i960Jx, Motorola ColdFire, RV4650 (through Galileo system controllers) and more · On-board system , Configuration EV-48212-14 ships with the following: · EV-48212-14 motherboard with 1 Mbyte SGRAM · i960Jx , the Intel i960Jx microprocessor. 5 Publish Date: 3/27/98 EV-48212-14 Preliminary (Revision 1.0 , i960Jx daughtercard) These settings can be changed via jumpers on the board. 3.3 Default Jumpers Galileo Technology
Original
GT-48212 ICT3041 lattice 2032 pc motherboard schematics smartbits duplex clock led display duplex led display
Abstract: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS · Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus · Dual bi-directional address space , to directly connect i960Jx or PPC401Gx processors to the PCI bus. V961PBC is also a suitable , increasing the FIFO depth and utilizing the unique DYNAMIC V96BMC MEMORY CONTROL i960Jx PPC401Gx , 4.2 Local Bus Timings Table 11: i960Jx Local Bus AC Test Conditions Symbol Parameter Limits V3 Semiconductor
Original
AD14 V961PBC-33 V961PBC-40
Abstract: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS · Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus · Fully compliant with PCI 2.1 specification · , highest performance, most flexible, and most economical method to directly connect i960Jx or PPC401Gx , Plastic Quad Flat Pack (PQFP) package. i960Jx PPC401Gx CPU V96BMC MEMORY CONTROL D R A M ROM , Timings Table 11: i960Jx Local Bus AC Test Conditions Symbol VCC VIN COUT Parameter Supply voltage Input V3 Semiconductor
Original
Abstract: _5 VCCPLL DEN# I960JX-3.3V-66Mhz 132-PQFP .01u DT/R# W/R# Phold D/C# R1000 4.7K , alileo ® EV-96010 Evaluation Platform for the GT-96010 and Intel's i960Jx CPU Preliminary , : +1-408.451.1404 EV-96010 - Evaluation Platform for the GT-96010 and Intel's i960Jx CPU 1. Galileo Technology TM Introduction The EV-96010 Evaluation Platform for the GT-96010 and Intel's i960Jx CPU , Technology EV-96010 - Evaluation Platform for the GT-96010 and Intel's i960Jx CPU 1.1 TM EV Galileo Technology
Original
CON20B 1N5005 CON28C hp simens 10BASE PLCC28 intel r1000 development platform EV96010 960JF-25 RS232/ EV-96010-EXP RS-232 GALILEO-10
Abstract: - V 9 6 1 P B C Rev. B1 yi '« IC O * ' LOCAL BUS TO PCI BRIDGE FOR i960®Jx AND PowerPCTM 401 Gx PROCESSORS · Glueless interface between i960Jx, PPC401Gx processors and , adding PCI to your i960Jx or PPC401Gx system. The V961PBC may also be used in systems without a CPU for a , , w h ile d ra m a tica lly improving the overall throughput of the system. The i960Jx processor , 11: i960Jx Local Bus AC Test Conditions Svmbo V CC P n m 11-I ' i. i nni s lints Supply voltage -
OCR Scan
Abstract: SALIGN is an implementation-specific parameter. For the i960Jx processors, SALIGN = 1, so stack frames , implementations. On the i960Jx processors, interrupts may also be requested in software with the sysctl Intel
Original
micro instruction set of I960 hx I960 80960JT microprocessor architecture programming 80960J
Abstract: sooner than the i960Jx. This will cause system failure due to a lack of synchronization between the , the i960Jx processors. In this section, we will cover two design examples: â'¢ 16-bit system based on , Chapter 3 Processor Interface The V96SSC is capable of directly interfacing to the i960Sx, i960Jx and , -Bit Multiplexed Address/Data Bus (i960Jx, PPC401Gx Processors) Unlike the ¡960Sx, the ¡960Jx and PPC401Gx , , the 16 bit i960Jx mode was not available 12 V96SSC User's Manual Rev 2.3x Copyright © 1997-1998, V3 -
OCR Scan
AV9154-04 I960SA MAS 10 RCD V3 SEMICONDUCTOR
Abstract: to the i960Jx Microprocessor User's Manual, Table 11-2). In the current implementation, of both the Intel
Original
272852 80960JA 80960JD 80960JF intel DOC 80960JA/JF/JD
Abstract: # is asserted. The i960Jx processor does not assert LOCK# except while a read-modify-write operation , of atmod completes. 1.3 Bus Applications The i960Jx microprocessor is a cost-effective , potential 80960Jx systems. These diagrams do not represent any particular i960Jx processor- based , i960Jx processor systems, the 80960Jx is the primary master of the local bus. A number of memory and I/O Intel
Original
28F800F3 28F160F3 D310 embedded microprocessors Intel AP-693 AP-693 AP-655 AP-617
Abstract: -32090 System Controller For I960JX Processors {Si n Galileo Technology, Inc. OVERVIEW The GT-32090 is a low cost, highly integrated single-chip System Controller for the i960Jx Family It provides high , Card B Misc. Rst* JTAG SCAN JTMS JTRst* JTDO GT-32090 System Controller For I960JX , device on the AD bus. _ Galileo Technology, Inc. GT-32090 System Controller For I960JX Processors , bus. GT-32090 System Controller For I960JX Processors lü _ Galileo ' M Technology, Inc. Pin Intel
Original
80960 272483 PMCON14 12345678H
Showing first 20 results.