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i960JX

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Abstract: V96SSC V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 ® Jx/Sx and PowerPCTM401Gx PROCESSORS BLOCK DIAGRAM · Glueless interface between Intel's i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices (Fast time-to-market) · Support for boot PROM devices · High-performance , Controller simplifies the design of systems based on Intel's i960Jx and i960Sx microprocessors. By using the , directly connects the i960Sx or i960Jx processor to DRAM arrays, from 128KByte to 128MByte. The fully ... Original
datasheet

2 pages,
396.18 Kb

V96SSC I960SX V96SSC abstract
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Abstract: Galileo-5 Benchmark Results 17 Jan 1997 Summary The following results are a summary of the detailed output of the benchmark tests below. All Benchmarks were performed with compiler optimization and with a standard 33Mhz I960jx Galileo-5 Board. Linpack-: 0.37 Mflops Dhrystones: 24 Dhrystones per second Linpack- Benchmark =>do Downloading - Download complete -Start address is : 00008000 =>go , seconds Repeat seconds Average Galileo-5 i960jx 33 On ic960 -AJA -Tgal5 -DSP -DROLL linpack-.c ... Original
datasheet

3 pages,
6.27 Kb

ic960 datasheet abstract
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Abstract: and i960Jx based designs · Two 32-bit general purpose timers · Pulse width modulation capability , systems based on i960Sx, i960Jx or PPC401Gx embedded microprocessors. The V96SSC V96SSC replaces many lower , ] Pin Decoding BTYPE[1:0] CPU Mode Boot Address Description 10 i960Jx (32 bit bus) A , V96SSC V96SSC uses 2X clock 11 i960Jx (16 bit bus) A[31, 26:24]="1110" 32-bit data bus, BE3 and , high order address inputs. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore ... Original
datasheet

20 pages,
157.79 Kb

V96SSC-33LP V96SSC V961PBC V960PBC PPC401GF heartbeat counter V96SSC abstract
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Abstract: , i960Jx, Motorola ColdFire, RV4650 RV4650 (through Galileo system controllers) and more · On-board system , Configuration EV-48212-14 EV-48212-14 ships with the following: · EV-48212-14 EV-48212-14 motherboard with 1 Mbyte SGRAM · i960Jx , incorporates the Intel i960Jx microprocessor. 5 Publish Date: 3/27/98 EV-48212-14 EV-48212-14 Preliminary (Revision , optional i960Jx daughtercard) These settings can be changed via jumpers on the board. 3.3 Default ... Original
datasheet

9 pages,
230.83 Kb

ICT3041 duplex led display duplex clock led display smartbits GT-48212 lattice 2032 EV-48212-14 EV-48212-14 abstract
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Abstract: · Fastest time to market for i960Sx and i960Jx based designs The V96SSC V96SSC High-Integration System Controller is a single-chip device that simplifies the design of systems based on i960Sx, i960Jx or PPC401Gx , V96SSC V96SSC Table 2: BTYPE[1:0] Pin Decoding BTYPE[1:0] 10 CPU Mode i960Jx (32 bit bus) i960Jx (16 bit bus , order address inputs. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC V96SSC latches the high order address signals internally on the assertion of ... Original
datasheet

22 pages,
157.1 Kb

PPC401GF datasheet abstract
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Abstract: different PMCONs (PMCONs are the i960JX's Physical Memory Configuration registers - see i960JX User's , appropriate i960Jx's PMCON register to the desired bus width, and mapping the appropriate Device n Address , System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary , design. FEATURES · Integrated system controller for embedded applications · Supports the i960JX , 160 PQFP i960JX External Agent AD Bus 32 373 Address & Control DRAM ADBusReq ... Original
datasheet

67 pages,
522.42 Kb

QS3257 PCMCIA SRAM Card MON960 GT-32090 256K-4M 256K-4M abstract
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Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · On-the-fly byte order (endian) conversion · I2O , V350EPC V350EPC directly connects to i960Jx or i960Sx processors without any glue logic. Minimal glue logic is , D Y N A M I C B A N D W I D T H A L L O C AT I O N TM V96BMC V96BMC MEMORY CONTROL i960Jx CPU D , Code Processors Bus Type Package Frequency V350EPC-33 V350EPC-33 REV A0 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 V350EPC-40 REV A0 i960Jx/Sx 32/16-bit multiplexed ... Original
datasheet

18 pages,
124.44 Kb

V96BMC V961PBC V960PBC V350EPC-40 V350EPC-33 V350EPC AD30 AD29 V350EPC abstract
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Abstract: interface to Intel's i960Jx and IBM's PowerPC TM 401Gx processors · On-the-fly byte order (endian , bus. V350EPC V350EPC directly connects to i960Jx or i960Sx proces sors with out a ny glue logic . Mi ni ma l , i960Jx CPU D R A M V350EPC V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 Semiconductor Corp. , V350EPC-33 V350EPC-33 REV A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 V350EPC-40 REV A0 / A1 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 40MHz 2.0 Pin Description ... Original
datasheet

18 pages,
117.17 Kb

V96BMC V961PBC V960PBC V350EPC-40 V350EPC-33 V350EPC AD30 AD29 V350EPC abstract
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Abstract: Intel's i960Jx and IBM's PowerPCTM 401Gx processors · Configurable for primary master, bus master or , multiplexed local bus applications to the PCI bus. V350EPC V350EPC directly connects to i960Jx or i960Sx processors , versions. i960Jx CPU V96BMC V96BMC MEMORY CONTROL D R A M ROM TYPICAL APPLICATION V350EPC V350EPC LOCAL , 1: Product Codes Product Code V350EPC-33 V350EPC-33 REV A0 V350EPC-40 V350EPC-40 REV A0 Processors i960Jx/Sx i960Jx/Sx , Applies to i960Sx mode. c. Applies to i960Jx mode. 2.1 Test Mode Pins Several device pins are ... Original
datasheet

18 pages,
95.61 Kb

V350EPC V961PBC V960PBC V350EPC abstract
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Abstract: recognized: i960Sx and i960Jx. Because the bus type is dynam ically detected, the V96SSC V96SSC may be used in , ific to e a ch p ro c e s s o r: 0 x0 0 0 0 .0 0 0 0 fo r th e i9 6 0 S x, OxFEFF.OOOO for the i960Jx. , to 25MHz · Low cost 100-pin EIAJ PQFP package · Fastest time to market for i960Sx and i960Jx based , directly to ¡960Sx and i960Jx processors. No "glue logic" is required. Care was taken during the design of , inputs. The ¡960Jx p ro ce sso r uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus ... OCR Scan
datasheet

24 pages,
1044.9 Kb

V96SSC V96SSC abstract
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Abstract: on (SALIGN*16)-byte boundaries, where SALIGN is an implementation-specific parameter. For the i960Jx , is not directly portable to other i960 implementations. On the i960Jx processors, interrupts may ... Original
datasheet

6 pages,
58.03 Kb

microprocessor architecture programming 80960JT micro instruction set of I960 hx datasheet abstract
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Abstract: 3 Volt Intel® Fast Boot Block to i960® Jx CPU Design Guide Application Note 693 May 2000 Document Number: 292241-002 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, r ... Original
datasheet

10 pages,
38.76 Kb

Intel AP-693 embedded microprocessors 28F800F3 28F160F3 datasheet abstract
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Abstract: 1 Overview The i960® Jx microprocessor provides a new set of essential enhancements for an emerging class of high-performance embedded applications. Based on the i960 core architecture, it is implemented in a proven 0.6 micron, three-layer metal process. Figure 1-1 identifies the processor's most notable features, each of which is described in subsections that follow the figure. These features include: · instruction cache · on-chip data RAM · timer units · data cache · local r ... Original
datasheet

4 pages,
50.69 Kb

80960JT 80960JF 80960JD 80960JA datasheet abstract
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Abstract: SUPPORT COMPONENTS V3 CORPORATION V96SSC V96SSC High-Integration Controller s s s s s s s s s s Glueless Interface to Intel's i960® Sx and i960 Jx Series Processors High-Performance DRAM Controller With DRAM Page Cache Management and EDO Support Two Channel Fly-By DMA Controller Synchronous/Asynchronous Serial Communication Unit Programmable Chip Select/ Peripheral Device Strobe Generation Programmable System Heartbeat and System Watchdog Timers Two 32-Bit Ge ... Original
datasheet

1 pages,
19.54 Kb

V96SSC intel i960 EDO dram heartbeat embedded microprocessors 64 Mb Synchronous DRAM V96SSC abstract
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Abstract: ® 80 TEP PACKAGE PINOUT APPLICATION BRIEF S5933 S5933 PCI MATCHMAKER - INTERFACING THE INTEL i960 Jx TO THE PCI BUS S5933 S5933 PCI MATCHMAKER - INTERFACING THE INTEL i960® Jx TO THE PCI BUS 1.0 AMCC S5933 S5933 PCI MATCHMAKER ARCHITECTURE 1.1.1 The best solution for interfacing to the PCI bus is an off-the-shelf device that is guaranteed to be PCI compliant while providing a flexible interface to the add-on card. The AMCC S5933 S5933 PCI Matchmaker provides bus mastering capabilities, suppor ... Original
datasheet

9 pages,
135.64 Kb

S5933 amcc pci matchmaker S5933 amcc pci matchmaker amcc s5933 S5933 abstract
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Abstract: same clock edge that BLAST# is asserted. The i960Jx processor does not assert LOCK# except while a , of atmod completes. 1.3 Bus Applications The i960Jx microprocessor is a cost-effective , potential 80960Jx systems. These diagrams do not represent any particular i960Jx processor- based , i960Jx processor systems, the 80960Jx is the primary master of the local bus. A number of memory and I/O ... Original
datasheet

32 pages,
351.04 Kb

datasheet abstract
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Abstract: i960® Jx PROCESSOR SPECIFICATION UPDATE Release Date: April, 1997 Order Number: 272852-002 The i960® Jx Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are not covered by Intel's warranty. Current characterized errata are available on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intel ... Original
datasheet

27 pages,
155.55 Kb

intel DOC 80960JF 80960JD 80960JA 272852 datasheet abstract
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Abstract: i960® JA/JF/JD/JS/JC/JT Microprocessors PRODUCT HIGHLIGHTS s Clock tripling technology s Large caches for faster performance s State of the art testability s i960® processor compatible RISC core s 100 MIPS execution for the i960 - JT-100 JT-100 processors s 16-Kbyte 2-way set associative instruction cache s 4-Kbyte direct mapped data cache s 1-Kbyte on-chip data RAM s Built-in interrupt controller s Low-power features s Two 32-bit timers PRODUCT OVERVIEW The ... Original
datasheet

6 pages,
94.14 Kb

80960RN 80960RM 80960JT 80960JF 80960JD 80960JA 80960HA datasheet abstract
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www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE13.TD)
Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE14.TD)
Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE14.TDK)
Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE17.TD)
Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE17.TDK)
Intel 17/03/1997 1212.21 Kb ZIP i960.zip
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www.datasheetarchive.com/download/56684786-173679ZC/i960.zip (FIGURE12.TD)
Intel 16/03/1997 1212.21 Kb ZIP i960.zip
No abstract text available
www.datasheetarchive.com/download/56684786-173679ZC/i960.zip (FIGURE12.TDK)
Intel 16/03/1997 1212.21 Kb ZIP i960.zip