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i678

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Abstract: destination code I678 When high, the Y outputs are in the high impedance state. When low, either the contents of the A-register or the outputs of the ALU are displayed on Y0-Y3 , as determined by I678. The carry , } what data is to be written into the Q register or on board RAM(I678). Signal paths at the MSB of the on-board RAM and the Q-register which are used for shifting data. When the destination code on I678 , Destination Address D0-D 3 Cn 1 (5 1 2 I345 I678 RAMO, 3 and Q0, 3 DO NOT CHANGE (Note 2) - - - - 25 20 -
OCR Scan
le5d p2g SMD 3Y0 "SMD CODE" WS5901 2901C WS5901C WS5901D MIL-STD-883C WS5901CP
Abstract: data on the A Port of the register stack, as determined by the destination code I678- 7 FUNCTIONAL , what data is to be deposited in the Q register or the register stack (I678)- OE Output Enable (Input , three-state outputs connected to TTL inputs internal to the device. When the destination code on I678 , 40 33 30 46 33 36 - I345 41 38 32 28 45 36 39 - I678 20 - - - - - 29 29 A Bypass ALU (I = 2XX) 23 - - , Change (Note 2) 0 D - - 26 0 Gin - - 16 0 1012 - - 30 0 1345 - - 31 0 I678 10 Do Not Change (Note 2) 0 -
OCR Scan
29C101 Dynamic Controls DZ 120-5 Am29C03 AM2904 amd 2901 pinout diagram 29C10 AIS-WCP-15M-04/87-0
Abstract: data on the A Port of the register stack, as determined by the destination code I678- 6 Powered by , what data is to be deposited in the Q register or the register stack (I678)-OE Output Enable (Input , three-state outputs connected to TTL inputs internal to the dev'ce. When the destination code on I678 , Destination Address 15 Do Not Change (Note 2) 0 D - - 25 0 Cjn - - 20 0 1012 - - 30 0 I345 - - 30 0 I678 , 24 24 25 24 25 - I345 26 24 24 24 26 24 26 - I678 16 - - - - - 21 21 A Bypass ALU (I = 2XX) 24 - - -
OCR Scan
qn2222- 29C10A-1 29C011 amd AM3 PIN LAYOUT amd am3 pin out amd am3 pinout diagram 29C01
Abstract: . When the destination code on I678 indicates an up shift (octal 6 or 7), the three-state outputs are , 43 40 33 30 46 33 36 - I345 41 38 32 28 45 36 39 - I678 20 - - - - - 29 29 A Bypass ALU (I = 2XX , 20 10 - !! ;. 24 18 20 - 1012 35 32 26 21 36 26 25 - I345 33 30 25 I 23 35 30 27 - I678 15 - - - - , 0 1012 - - 25 0 I345 - - 26 0 I678 7 Do Not Change (Note 2) 0 RAMq, 15, Qo, 15 - I 0 D , 46 39 41 - Qn 33 28 15 - 33 27 30 - 1012 50 47 36 34 53 38 41 - I345 47 44 35 35 51 44 45 - I678 -
OCR Scan
AM290L amd 2901 alu amd am2 pinout CGX068 l67s pinout AM2 AMD
Abstract: data on the A Port of the register stack, as determined by the destination code I678- 6 Thi s , what data is to be deposited in the Q register or the register stack (I678)-OE Output Enable (Input , three-state outputs connected to TTL inputs internal to the dev'ce. When the destination code on I678 , Destination Address 15 Do Not Change (Note 2) 0 D - - 25 0 Cjn - - 20 0 1012 - - 30 0 I345 - - 30 0 I678 , 25 - I345 26 24 24 24 26 24 26 - I678 16 - - - - - 21 21 A Bypass ALU (I = 2XX) 24 - - - - - - - -
OCR Scan
CD004110
Abstract: 1) C l = 50pF To Output From Input A, B Address D Cn 1012 I345 I678 A Bypass ALU (I - 2XX) Clock J , Set-up Time Before H - L A, B Source Address B Destination Address D Cn 1012 I345 I678 RAMO, 3, 00 , 3 20 , Delays. (Note 1) C l = SOpF To Output From Input A, B Address D Cn 1012 I345 I678 A Bypass ALU (I - 2XX , Output From Input A, B Address D Cn 1012 I345 I678 A Bypass ALU (I - 2XX) Clock _ r Y 40 30 22 35 35 25 , D Cn 1012 I345 I678 RAMO, 3, Q0, 3 15 15 10 \ Hold Tim« After H - L 1 (Note 3) Set-up Tim * Before L -
OCR Scan
processor Am2901 2901B AM-201C AM2902 i345 2901B/A 01656B
Abstract: by I678. G, P 0 The carry generate and propagate outputs of the ALU. OVR 0 This , ) what data is to be written into the Q register or on board RAM (I678). Q 3 , RAM3 I/O Signal , destination code on I678 indicates an up shift (Octal 6 or 7) the three state outputs are enabled and the MSB , destination code I678 Ã"Ã' 1 When high, the Y outputs are in the high impedance state. When low -
OCR Scan
WS5901CY WS5901CYM WS5901CYMB WS5901DY WS5901DYM WS5901DYMB
Abstract: perform (I345), and what data is to be deposited in the Q-register or the register stack (I678)- q15 , code on I678 indicates an up shift (octal 6 or 7) three-state outputs are enabled and the MSB of the Q -
OCR Scan
MPR-006 4X2901B TTL ALU 16-BIT
Abstract: th e ALU as d e term ined by th e d e s tin a tio n code I678. W hen high, th e Y o u tp u ts are in , o u tp u ts o f th e ALU are displaye d on Y0-Y 15, as d e term ined by I678. The carry g e n e ra , e Q re g iste r or on board RAM (I678). S ignal paths at th e M SB of th e on-boa rd RAM and th e Q -re g is te r w h ich are used fo r s hifting d a ta W hen th e d e s tin a tio n co d e on I678 in d -
OCR Scan
WS59016 WS59016CL BD-AD 59016e 3644Y dlc9 w2902a WS59016CB WS59016CBM WS59016CBMB WS59016CJ
Abstract: ,9,10,11 From 1678 to RAMo, 3 7, 8,9,10,11 From I678 to Q0, 3 7,8,9,10,11 From A Bypass ALU to Y (I = , L+H 7,8,9,10,11 I678 Set-Up Time Before H ♦ L 7,8,9,10,11 I678 Hold Time After H*L 7,8,9,10,11 1678 -
OCR Scan
CY2901C CY2901 AM2901 CY2901CDC CY2901CDMB CY2901CPC 38-00008-B
Abstract: CN 1012 I345 I678 A Bypass ALU(i = 2XX) CP ` 56.0 52.5 38.7 38.6 31.9 28.8 43.9 40.4 25.8 26.5 19.3 , 0 0 . A, B Address B Destination Address D CN 1012 1 345 I678 RAMI/QI0:15 Notes: 1. A dash -
OCR Scan
2901s 512x64 LSA2005 LL7000 792/286/20K/IM/J
Abstract: . When the destination code on I678 indicates an up shift (octal 6 or 7), the three-state outputs are , 36 39 - I678 20 - - - - - 29 29 A Bypass ALU (I = 2XX) 23 - - - - - - - Clock _r 38 34 25 27 36 32 34 , I345 33 30 25 I 23 35 30 27 - I678 15 - - - - - 20 20 A Bypass ALU (I = 2XX) 18 - - : - - - - - Clock , Change (Note 2) 0 D - - 22 0 Cm - - 13 0 1012 - - 25 0 I345 - - 26 0 I678 7 Do Not Change (Note 2) 0 , 36 34 53 38 41 - I345 47 44 35 35 51 44 45 - I678 22 - - - - - 30 30 A Bypass ALU (1 = 2 XX) 27 - - - -
OCR Scan
am2901b Am29C101s amd 2901
Abstract: - I345 51 52 52 45 60 49 53 - I678 28 - - - - - 35 35 A Bypass ALU (I = 2XX) 37 - - - - - - - , - - 51 0 Cn - - 39 0 1012 - - 56 0 I345 - - 55 0 I678 11 Do Not Change (Note 2) 0 RAMO, 3, QO , - I345 58 58 58 48 64 56 55 - I678 29 - - - - - 27 27 A Bypass ALU (I = 2XX) 50 - - - - - - - , 25 22 25 - 1012 35 35 35 37 37 35 35 - I345 35 35 35 35 38 35 35 - I678 25 - - - - - 26 26 A , 25 21 - 28 25 28 - 1012 40 40 40 44 44 40 40 - I345 40 40 40 40 40 40 40 - I678 29 - - - - - 29 29 -
OCR Scan
d401c 4bit alu D-40
Abstract: 45 I345 5 1 52 52 45 I678 28 - - - A Bypass ALU (I = 2XX) 37 , - 39 0 1012 - - 56 0 I345 - - 55 0 I678 11 RAMO, 3, Q0 , 40 32 24 1012 53 50 I345 58 I678 29 A Bypass ALU (I = 2XX) Clock J , 55 0 Cn - - 42 0 1012 - - 58 0 I345 - - 62 0 I678 -
OCR Scan
am2901a AM2901ADC AM2901BPC Am2901DC 2901A MPR-014
Abstract: I678 Set-Up Time Before H » L 7, 8, 9,10,11 I678 Hold Time After H » L 7, 8, 9,10,11 I678 Set-Up Time Before L * H 7, 8, 9,10,11 I678 Hold Time After L* H 7, 8, 9,10,11 RAM0, RAM15, QO, Q15 Set-Up Time -
OCR Scan
CY7C9101 CY7C9101-30 CY7C9101-35 cy7c9101-30jc CY7C9101-30GC CY7C9101-40JC 7c9101 AM29C101 38-00017-D
Abstract: Destination Address 15 Do Not Change (Note 2) 0 D - - 51 0 Cn - - 39 0 1012 - - 56 0 I345 - - 55 0 I678 , 50 47 46 65 55 58 - I345 58 58 58 48 64 56 55 - I678 29 - - - - - 27 27 A Bypass ALU (I = 2XX) 50 , 35 - I678 25 - - - - - 26 26 A Bypass ALU (I - 2XX) 35 - - - - - - - Clock _r 35 35 35 35 35 35 35 , I678 29 - - - - - 29 29 A Bypass ALU (I = 2XX) 40 - - - - - - - Clock _r 40 40 40 40 40 40 40 33 C , 1012 - - 30 0 I345 - - 30 0 I678 10 Do Not Change (Note 2) 0 RAMO, 3, Q0, 3 - â'¢1 0 Output -
OCR Scan
AM2901BDC 01G56B
Abstract: 40 30 22 40 38 25 37 38 35 35 35 25 35 35 35 35 35 35 35 35 35 35 35 I345 I678 A , ) I345 I678 RAMq, 3 , Qq, 3 - - 12 D. Input ÜË Output Enable/Disable Times (N o te 5 , 10 Do Not Change (Note 2) 16 13 19 19 Do Not Change (Note 2) 9 7 - I345 I678 RAMq, a, Qo, 3 , 48 37 28 40 40 29 Qo q3 29 u. O II A, B Address D Cin 1012 I345 I678 48 37 25 40 40 , ) Do Not Change (Note 2) 25 20 30 30 I345 I678 RAMo, 3 , Qo, 3 Do Not Change (Note 2) 12 - -
OCR Scan
QN1012
Abstract: 56 0 I345 - - 55 0 I678 11 Do Not Change {Note 2) 0 RAMO, 3, QO, 3 - I 16 0 D. Output Enable , I678 29 - - - - - 27 27 A Bypass ALU (I = 2XX) 50 - - - - - - - Clock _T 53 50 49 41 63 58 61 31 C , 35 - I678 25 - - - - - 26 26 A Bypass ALU (I - 2XX) 35 - - - - - - - Clock _r 35 35 35 35 35 35 35 , I678 29 - - - - - 29 29 A Bypass ALU (I = 2XX) 40 - - - - - - - Clock _r 40 40 40 40 40 40 40 33 C , 1012 - - 30 0 I345 - - 30 0 I678 10 Do Not Change (Note 2) 0 RAMO, 3, Q0, 3 - â'¢1 0 Output -
OCR Scan
i5 instruction
Abstract: Dynamic Performance - A D I678 INPUT AMPLITUDE - dB INPUT FREQUENCY - kHz Figure 6. Harmonic , CONVERTERS ! j ] Package Options* N-28A N-28A D-28A D-28A Application Information - A D I678 , Interface Figure 17. A D I678 to ADSP-2100A Interface Figure 15. AD1678 to 80186 DMA Interface -
OCR Scan
ADSP2100A
Abstract: ined by th e destination code I678- 3, P C a rry G enerate, Propagate O utputs (Output) The carry , 35 35 - 35 35 35 35 38 35 35 - I678 25 - - - - - , 1012 - I678 0 30 0 - I345 0 20 - - 25 - - Qn 30 0 , 25 - I345 26 24 24 24 26 24 26 - I678 16 - - - - - , 16 0 Qn - - 13 0 1012 - - 19 0 I345 - - 19 0 I678 -
OCR Scan
Abstract: what data is to be deposited in the Q register or the register stack (I678)-OE Output Enable (Input , three-state outputs connected to TTL inputs internal to the dev'ce. When the destination code on I678 , data on the A Port of the register stack, as determined by the destination code I678- 6 Thi s , Destination Address 15 Do Not Change (Note 2) 0 D - - 25 0 Cjn - - 20 0 1012 - - 30 0 I345 - - 30 0 I678 , 25 - I345 26 24 24 24 26 24 26 - I678 16 - - - - - 21 21 A Bypass ALU (I = 2XX) 24 - - - - - - - Toshiba
Original
Transistor AND DIODE Equivalent list Transistor Equivalent list 8ch pnp DARLINGTON TRANSISTOR ARRAY pnp Octal Darlington Transistor Arrays equivalent transistor 2sk TD62783 TD62S050AFM TD62S051AFM TD62S350AFM 2SC3420 HSOP16 TD62M8600F
Abstract: } what data is to be written into the Q register or on board RAM(I678). Signal paths at the MSB of the on-board RAM and the Q-register which are used for shifting data. When the destination code on I678 , destination code I678 When high, the Y outputs are in the high impedance state. When low, either the contents of the A-register or the outputs of the ALU are displayed on Y0-Y3 , as determined by I678. The carry , Destination Address D0-D 3 Cn 1 (5 1 2 I345 I678 RAMO, 3 and Q0, 3 DO NOT CHANGE (Note 2) - - - - 25 20 Integrated Device Technology
Original
IDT49C402 IDT49C402A IDT49C402B ex-nor 49c402 exnor 2902a MIL-STD-883 IDT49C402/A/B 49C402
Abstract: 40 30 22 40 38 25 37 38 35 35 35 25 35 35 35 35 35 35 35 35 35 35 35 I345 I678 A , ) I345 I678 RAMq, 3 , Qq, 3 - - 12 D. Input ÜË Output Enable/Disable Times (N o te 5 , 10 Do Not Change (Note 2) 16 13 19 19 Do Not Change (Note 2) 9 7 - I345 I678 RAMq, a, Qo, 3 , 48 37 28 40 40 29 Qo q3 29 u. O II A, B Address D Cin 1012 I345 I678 48 37 25 40 40 , ) Do Not Change (Note 2) 25 20 30 30 I345 I678 RAMo, 3 , Qo, 3 Do Not Change (Note 2) 12 - -
OCR Scan
59032D 59032 WS59032 32-BIT S59032 WS59032DA
Abstract: 56 0 I345 - - 55 0 I678 11 Do Not Change {Note 2) 0 RAMO, 3, QO, 3 - I 16 0 D. Output Enable , I678 29 - - - - - 27 27 A Bypass ALU (I = 2XX) 50 - - - - - - - Clock _T 53 50 49 41 63 58 61 31 C , 35 - I678 25 - - - - - 26 26 A Bypass ALU (I - 2XX) 35 - - - - - - - Clock _r 35 35 35 35 35 35 35 , I678 29 - - - - - 29 29 A Bypass ALU (I = 2XX) 40 - - - - - - - Clock _r 40 40 40 40 40 40 40 33 C , 1012 - - 30 0 I345 - - 30 0 I678 10 Do Not Change (Note 2) 0 RAMO, 3, Q0, 3 - â'¢1 0 Output -
OCR Scan
59016c S59016 59016C IL-STD-883C S59016C S59016EJ S59016EL
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