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Part Manufacturer Description PDF Samples Ordering
8403701DA Texas Instruments IC NAND GATE, Gate ri Buy
SNJ54S37J Texas Instruments IC NAND GATE, Gate ri Buy
SN54265J-00 Texas Instruments IC TTL/H/L SERIES, DUAL 2-INPUT AND/NAND GATE, CDIP16, Gate ri Buy

full subtractor circuit using xor and nand gates

Catalog Datasheet Results Type PDF Document Tags
Abstract: to 8 inputs) - Simple Gates, including XOR, XNOR and AOI - 3-state and Non-Inverting Buffers Several , more buses. Datapath memory elements (register files, latches, and flip flops) can be clocked using a , their own locations. For gate array and stan dard cell datapath designs that are implemented using a , accepts VHDL and VerilogTM HDL behavioral inputs and can generate complete ASIC devices using datapath , fewer gates but can also (depending on the applica tion and design) be 1/3 to 1/2 the area of an ... OCR Scan
datasheet

10 pages,
1099.16 Kb

74181 pin configuration alu 74181 pin diagram bit-slice T3FL verilog code for 16 bit barrel shifter verilog code for 64 bit barrel shifter 32 bit ALU vhdl code datasheet abstract
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Abstract: 8 bit versions of the macro (except for Adder and Subtractor Carry Select, which have a minimum bit , · CacheLogic® dynamic full/partial reconfigurability in-system · Eight global clocks and four fast , ® capabilities. With CacheLogic, DSP and other logic functions can be created quickly and accurately using , a single data base to take your work from design entry to configured circuit quickly and , circuit, which improves the rise and fall times (leading and trailing edges) of the incoming signal. · ... Original
datasheet

122 pages,
2679.56 Kb

vhdl code of carry save adder full subtractor circuit using and gates vhdl code for crc16 using lfsr half adder using x-OR and NAND gate carry select adder Mux 1x8 74 verilog code for jk flip flop FULL SUBTRACTOR using 41 MUX pn sequence generator using d flip flop AT40K AT40K abstract
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Abstract: , NAND, and OR gates with two to six inputs. At each input count, all numbers of inversion bubbles are , also features the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single , circuit board as well. You may create inverting HD2PADs or HD3PADs by using multiple HDiPADs and tying , AND, OR, NAND, and NOR gates with two to six inputs with each input invertable. As well, a very wide , utilization property-two AND gates and a 3-input XOR gate can be packed into a single pASIC logic cell. 3 ... Original
datasheet

60 pages,
603.93 Kb

74139 Dual 2 to 4 line decoder 7474 shift register schematic of TTL XOR Gates d-latch by using D flip-flop 7474 TTL 7400 CI 74139 full subtractor circuit using nor gates 74823 FULL ADDER verilog code of 8 bit comparator vhdl code for 8-bit BCD adder 3-8 decoder 74138 datasheet abstract
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Abstract: complex as a dual D latch with enable. The QuickLogic Macro Library includes AND, NOR, NAND, and OR gates , the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single logic cell , Gates The QuickLogic Macro Library includes AND, OR, NAND, and NOR gates with two to six inputs with , property-two AND gates and a 3input XOR gate can be packed into a single pASIC logic cell. EQCOMP4 A[0:3 , as equivalence) gates. Their names use the same terminology as the AND, NOR, NAND, OR gates ... Original
datasheet

56 pages,
821.6 Kb

74194 shift register pin configuration of d flip flip 7474 74138 74139 mux 7474 j-k flip flop full subtractor circuit using nor gates TTL 74139 7400 QUAD Nor 74171 74594 data sheet 74139 vhdl code for 8-bit BCD adder datasheet abstract
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Abstract: srlab1 srlab2 Subtractor su01d1 Power and Ground Cells vddcon vsscon Exclusive NOR Gates , fabricates CBICs using one of the following CMOS silicon processes: ECPD07 ECPD07 AT19.8K 5V and 3V , test vectors is developed for the design, and verified using Atmel's FAST tools. This is to ensure , analysis, floorplanning, hierarchical placement and routing, delay estimation and calculation using , ATPG Design Rules Check, Full Scan Path Insertion, ATPG Vector Generation and Fault Coverage ... Original
datasheet

41 pages,
312.46 Kb

barrel shifter using verilog AT56K AT55K AOI21 nd02d4 OAI211 OAI31 atmel 0532 vhdl code for 8 bit barrel shifter XP-140 8 bit barrel shifter vhdl code ECPD07 or03d1 MX 0541 8051TM 8051TM abstract
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Abstract: gates which have inputs from the two 5-input LUT outputs. In some cases, this can be used for faster and/or wider logic functions. As can be seen, two of the three inputs into the NAND, XOR, and MUX gates , XOR and MUX share the f1 output, the F5X and F5M modes are mutually exclusive. The output of the NAND , in a variety of packages, speed grades, and temperature ranges. Table 1 lists the usable gates for , two four-input functions using F5A and F4B modes or F4A and F5B modes. HLUTA A4A3A2A1A0a4 a3 R? a1 aO ... OCR Scan
datasheet

23 pages,
1377.05 Kb

RuC15 R11C5 DRIVERS R13C10 R13C6 plc array R7C19 RSC16 R8C1B R12C20 R3C15 datasheet abstract
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Abstract: type any type any type Logical and or nand nor xor not Relational = /= < > = 14 , , "data_a" and "data_b." Adders and subtractors can be inferred by using the following subtractor example (to , . . . . . . . . 5 VHDL Naming Conventions and Declaring a Circuit. . . . . . . Signals . . . . . . , ��Introduction VHDL is a high-level description language for system and circuit design that supports various , contains information and techniques for using ACTmap VHDL to design an Actel device. This includes ... Original
datasheet

99 pages,
474.88 Kb

vhdl code sum between 2 numbers in C2 datasheet abstract
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Abstract: Description Using Combinatorial Process and Always Block . 2-29 VHDL , , XC2064 XC2064, XC3090 XC3090, XC4005 XC4005, XC5210 XC5210, and XC-DS501 XC-DS501 are registered trademarks of Xilinx, Inc. The shadow X , , XACT-Performance, XAM, XAPP, XBLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, Xilinx Foundation Series, XPP, XSI, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array , improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not ... Original
datasheet

336 pages,
1078.34 Kb

8 bit subtractor 411 mux verilog code for 16 bit inputs verilog code for johnson decoder Verilog code subtractor vhdl code of floating point adder verilog code for johnson counter UNSIGNED SERIAL DIVIDER using verilog 8 bit carry select adder verilog codes datasheet abstract
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Abstract: information about using the Designer series software and the Synopsys documentation for additional information , illustrates and describes the design flow for creating Actel designs using Synopsys and Designer Series , techniques. Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for using design , information about using the ACTgen Macro Builder and ACTmap VHDL Synthesis software. Actel HDL Coding Style , information, optimization techniques, and procedures to assist designers in the design of Actel devices using ... Original
datasheet

147 pages,
756.93 Kb

vhdl code for full subtractor datasheet abstract
datasheet frame
Abstract: Actel manual for additional information about using the Designer series software and the Synopsys , Actel-Synopsys Design Flow illustrates and describes the design flow for creating Actel designs using Synopsys , and user interface for the Actel Designer Series software, including information about using the , procedures to assist designers in the design of Actel devices using Cadence CAE software and the Designer , assist designers in the design of Actel devices using Mentor Graphics CAE software and the Designer ... Original
datasheet

147 pages,
1489.48 Kb

verilog code of 2 bit comparator verilog code for 4 bit ripple COUNTER vhdl coding for pipeline datasheet abstract
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