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Part Manufacturer Description Datasheet BUY
SN74F283DR Texas Instruments F/FAST SERIES, 4-BIT ADDER/SUBTRACTOR, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments
SN74LS283DG4 Texas Instruments LS SERIES, 4-BIT ADDER/SUBTRACTOR, PDSO16, GREEN, SOIC-16 visit Texas Instruments
SN74F283DRE4 Texas Instruments F/FAST SERIES, 4-BIT ADDER/SUBTRACTOR, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments
SN74F283DRG4 Texas Instruments F/FAST SERIES, 4-BIT ADDER/SUBTRACTOR, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments
SN74F283DE4 Texas Instruments F/FAST SERIES, 4-BIT ADDER/SUBTRACTOR, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments
SN74F283DG4 Texas Instruments F/FAST SERIES, 4-BIT ADDER/SUBTRACTOR, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16 visit Texas Instruments

full subtractor circuit using xor and nand gates

Catalog Datasheet MFG & Type PDF Document Tags

pn sequence generator using d flip flop

Abstract: pn sequence generator using jk flip flop 8 bit versions of the macro (except for Adder and Subtractor Carry Select, which have a minimum bit , · CacheLogic® dynamic full/partial reconfigurability in-system · Eight global clocks and four fast , . With CacheLogic, DSP and other logic functions can be created quickly and accurately using Atmel , a single data base to take your work from design entry to configured circuit quickly and , comparator circuit, which improves the rise and fall times (leading and trailing edges) of the incoming
Atmel
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full subtractor circuit using xor and nand gates

Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 more buses. Datapath memory elements (register files, latches, and flip flops) can be clocked using a , their own locations. For gate array and stan dard cell datapath designs that are implemented using a , accepts VHDL and VerilogTM HDL behavioral inputs and can generate complete ASIC devices using datapath , fewer gates but can also (depending on the applica tion and design) be 1/3 to 1/2 the area of an , g y, inc. - Counters - Comparator - Multiplexers (2 to 8 inputs) - Simple Gates, including XOR
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full subtractor circuit using xor and nand gates

Abstract: 74138 full subtractor complex as a dual D latch with enable. The QuickLogic Macro Library includes AND, NOR, NAND, and OR gates , the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single logic cell , Gates The QuickLogic Macro Library includes AND, OR, NAND, and NOR gates with two to six inputs with , property-two AND gates and a 3input XOR gate can be packed into a single pASIC logic cell. EQCOMP4 A[0:3 , as equivalence) gates. Their names use the same terminology as the AND, NOR, NAND, OR gates
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7474 D flip-flop

Abstract: vhdl code for 74154 4-to-16 decoder , NAND, and OR gates with two to six inputs. At each input count, all numbers of inversion bubbles are , also features the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single , circuit board as well. You may create inverting HD2PADs or HD3PADs by using multiple HDiPADs and tying , includes AND, OR, NAND, and NOR gates with two to six inputs with each input invertable. As well, a very , . This macro's design takes advantage of theXOR utilization property-two AND gates and a 3-input XOR
QuickLogic
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verilog code for 16 bit carry select adder

Abstract: X8978 Verilog constructs and meta comments. Chapter 8, "Command Line Mode," describes how to run XST using the , Description Using Combinatorial Process and Always Block . 2-29 VHDL Code , , XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc. The shadow X , , XACT-Performance, XAM, XAPP, XBLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, Xilinx Foundation Series, XPP, XSI, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array
Xilinx
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verilog code for 16 bit carry select adder X8978 verilog code of 8 bit comparator 8 bit carry select adder verilog codes UNSIGNED SERIAL DIVIDER using verilog SR-4X

8 bit full adder

Abstract: "8 bit full adder" Turbo Path for ispLSI5000V and 8000 devices. XOR Net Identifies XOR gates on a net that are , . . . . . . . . . . . . . . . . . Using IN, OUT, and BIDI Pins . . . . . . . . . . . . . . . . . . , Attributes to designs created in Viewlogic Creating and using macros, including programmable macros , Provides information for compiling designs using the ispEXPERT Compiler and Viewlogic software. Chapter 7 , documentation is useful when using the ispEXPERT Compiler and Viewlogic software: Lattice Semiconductor s
Lattice Semiconductor
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8 bit full adder vhdl code for 8-bit serial adder ZF8.2 quad design motive CBU441 1-800-LATTICE DS2101-PC-UM

rda 5807 sp

Abstract: rda 5807 , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND
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rda 5807 sp rda 5807 rda 5807 sp fm receiver ic Elcom IC TDA 2208 NA51 transistor datasheet

design an 8 Bit ALU using VHDL software tools -FP

Abstract: AOI221 srlab1 srlab2 Subtractor su01d1 Power and Ground Cells vddcon vsscon Exclusive NOR Gates , fabricates CBICs using one of the following CMOS silicon processes: ECPD07 AT19.8K 5V and 3V , test vectors is developed for the design, and verified using Atmel's FAST tools. This is to ensure , analysis, floorplanning, hierarchical placement and routing, delay estimation and calculation using , ATPG Design Rules Check, Full Scan Path Insertion, ATPG Vector Generation and Fault Coverage
Atmel
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design an 8 Bit ALU using VHDL software tools -FP AOI221 atmel 0928 OAI221 MX 0541 or03d1 8051TM

tda 8210

Abstract: rtl 8112 , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND
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tda 8210 rtl 8112 8085 microprocessor simulator NA52 transistor datasheet AMI MG82C54 8 BIT ALU design with verilog/vhdl code

verilog code for Modified Booth algorithm

Abstract: Booth algorithm using verilog about using the Designer series software and the Synopsys documentation for additional information about , describes the design flow for creating Actel designs using Synopsys and Designer Series software. Chapter 3 , . Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for using design , information for using the Designer Series Development System software to create designs for, and program , design of Actel devices using Cadence CAE software and the Designer Series software. Mentor Graphics
Actel
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verilog code for Modified Booth algorithm Booth algorithm using verilog structural vhdl code for ripple counter booth multiplier code in vhdl 8 bit booth multiplier vhdl code 8 bit carry select adder verilog code

vhdl coding for pipeline

Abstract: structural vhdl code for ripple counter Actel manual for additional information about using the Designer series software and the Synopsys , Actel-Synopsys Design Flow illustrates and describes the design flow for creating Actel designs using Synopsys , and user interface for the Actel Designer Series software, including information about using the , assist designers in the design of Actel devices using Cadence CAE software and the Designer Series , designers in the design of Actel devices using Mentor Graphics CAE software and the Designer Series software
Actel
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vhdl coding for pipeline RAM32X32 verilog code for 4 bit ripple COUNTER verilog code of 2 bit comparator

DW01 pinout

Abstract: vhdl code for full subtractor information about using the Designer series software and the Synopsys documentation for additional information , illustrates and describes the design flow for creating Actel designs using Synopsys and Designer Series , techniques. Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for using , software, including information about using the ACTgen Macro Builder and ACTmap VHDL Synthesis software , Actel devices using ACTmap VHDL. Silicon Expert User's Guide. This guide contains information and
Actel
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DW01 pinout vhdl code for full subtractor 16 bit carry select adder verilog code full subtractor implementation using 4*1 multiplexer

DIGITAL GATE EMULATOR USING 8085

Abstract: 8086 microprocessor book by A K RAY Array Description: AN11 is an AND-NOR circuit consisting of two 2-input AND gates into a 2-input NOR , Description: AN81 is an AND-NOR circuit consisting of two 2-input AND gates into a 3-input NOR gate. iiA , , INC. AMI ANC1 is an AND-NOR circuit consisting of one 3-input AND gate and two 2-input AND gates , CHIOS Gate Array Description: AND1 is an AND-NOR circuit consisting of two 3-input AND gates and one , responsible for capturing and verifying the design using the AMI ASIC Standard Library. He is also responsible
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AMI6G33S DIGITAL GATE EMULATOR USING 8085 8086 microprocessor book by A K RAY 180 nm CMOS standard cell library AMI IC1732 DL021 ic isl 887 AMI6G16S AMI6G41S AMI6G70S AMI6G106S AMI6G150S

bb 9790 schematic diagram

Abstract: DIGITAL GATE EMULATOR USING 8085 circuit consisting of one 3-input AND gate and two 2-input AND gates into a 3-input NOR gate. Logic Symbol , for the number of gates and pads required. - Provides 6 extra power pads per corner to pre-serve more , , multipliers, adders, barrel shifters). · Wide range of packaging: Full QFP and LCC line, DIPs and PGAs , with an AMI design center, the customer is responsible for capturing and verifying the design using the , design is then released for mask and wafer fabrication. The test program is developed in parallel using
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bb 9790 schematic diagram 04S75 TDA 1006 equivalents verilog code motor ami equivalent gates IC tda 2548 MG65C02 MG29C01 MG29C10 MG80C85 MG82C MGMC51

QL24X32B-1PF144C

Abstract: vhdl code for 74194 dual D latch with enable. The QuickLogic Macro Library includes AND, NOR, NAND, and OR gates with two , possible AND, NOR, NAND, and OR gates which can be implemented in a single logic cell (AND14i7, NOR14i7 , Reference 3.4 Gates The QuickLogic Macro Library includes AND, OR, NAND, and NOR gates with two to six , Programmer using HITERM Appendix A: SUN Installation and Requirements Hardware Requirements Software , sources in specific cases. This is called double buffering. Using two gates to drive a high-fanout net
Vantis
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QL24X32B-1PF144C vhdl code for 74194 QP-PL84G 74164 pin assignment ls 74138 74154

vhdl code for traffic light control

Abstract: 32 bit sequential multiplier vhdl type any type any type Logical and or nand nor xor not Relational = /= < > = 14 , . . . . . . . . 5 VHDL Naming Conventions and Declaring a Circuit. . . . . . . Signals . . . . . . , Introduction VHDL is a high-level description language for system and circuit design that supports various , contains information and techniques for using ACTmap VHDL to design an Actel device. This includes , ACTmap and describes how to implement optimization techniques in a design. Appendix A - Using ACTmap in
Actel
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vhdl code for traffic light control 32 bit sequential multiplier vhdl 4 bit sequential multiplier Vhdl vhdl code of 32bit floating point adder vhdl code sum between 2 numbers in C2

multiplier using CARRY SELECT adder

Abstract: R3C15 gates which have inputs from the two 5-input LUT outputs. In some cases, this can be used for faster and/or wider logic functions. As can be seen, two of the three inputs into the NAND, XOR, and MUX gates , XOR and MUX share the f1 output, the F5X and F5M modes are mutually exclusive. The output of the NAND , in a variety of packages, speed grades, and temperature ranges. Table 1 lists the usable gates for , two four-input functions using F5A and F4B modes or F4A and F5B modes. HLUTA A4A3A2A1A0a4 a3 R? a1 aO
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multiplier using CARRY SELECT adder R3C15 R14C17 R12C20 R8C1B RuC15

8085 mini projects

Abstract: full subtractor circuit using decoder and nand ga , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND
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8085 mini projects full subtractor circuit using decoder and nand ga DF102 ic tda 2030 8085 mini projects with low budget AMI 9198

schematic diagram online UPS

Abstract: na44 , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 2-input OR and 3-input OR into 2-input NAND , .3-189 2-input OR and 3-input OR into 3-input NAND
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schematic diagram online UPS na44 MG82C54 NA51 DC motor fpga highway speed checker circuit diagram

NA2X

Abstract: vhdl code gold sequence code , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND
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NA2X vhdl code gold sequence code 16 BIT ALU design with verilog/vhdl code tda 2030 ic 5 pins QN-08 1329 DL021D
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