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HIP4082IBT Intersil Corporation 1.3A FULL BRDG BASED MOSFET DRIVER, PDSO16 ri Buy
HS9-4080ARH-8 Intersil Corporation FULL BRDG BASED MOSFET DRIVER, CDFP20, CERAMIC, DFP-20 ri Buy
HS9-4080ARH-Q Intersil Corporation FULL BRDG BASED MOSFET DRIVER, CDFP20, CERAMIC, DFP-20 ri Buy

full subtractor circuit using xor and nand gates

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 8 bit versions of the macro (except for Adder and Subtractor Carry Select, which have a minimum bit , · CacheLogic® dynamic full/partial reconfigurability in-system · Eight global clocks and four fast , . With CacheLogic, DSP and other logic functions can be created quickly and accurately using Atmel , a single data base to take your work from design entry to configured circuit quickly and , comparator circuit, which improves the rise and fall times (leading and trailing edges) of the incoming ... Atmel
Original
datasheet

122 pages,
2679.56 Kb

full subtractor circuit using and gates vhdl code for crc16 using lfsr verilog code CRC8 half adder using x-OR and NAND gate carry select adder Mux 1x8 74 verilog code for jk flip flop FULL SUBTRACTOR using 41 MUX pn sequence generator using d flip flop TEXT
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Abstract: more buses. Datapath memory elements (register files, latches, and flip flops) can be clocked using a , their own locations. For gate array and stan dard cell datapath designs that are implemented using a , accepts VHDL and VerilogTM HDL behavioral inputs and can generate complete ASIC devices using datapath , fewer gates but can also (depending on the applica tion and design) be 1/3 to 1/2 the area of an , g y, inc. - Counters - Comparator - Multiplexers (2 to 8 inputs) - Simple Gates, including XOR ... OCR Scan
datasheet

10 pages,
1099.16 Kb

74181 pin configuration bit-slice 74181 full subtractor circuit using nand gate alu 74181 pin diagram T3FL verilog code for 16 bit barrel shifter vhdl code of 32bit floating point adder 32 bit ALU vhdl code verilog code for 64 bit barrel shifter ALU 74181 verilog TEXT
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Abstract: complex as a dual D latch with enable. The QuickLogic Macro Library includes AND, NOR, NAND, and OR gates , the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single logic cell , Gates The QuickLogic Macro Library includes AND, OR, NAND, and NOR gates with two to six inputs with , property-two AND gates and a 3input XOR gate can be packed into a single pASIC logic cell. EQCOMP4 A[0:3 , as equivalence) gates. Their names use the same terminology as the AND, NOR, NAND, OR gates ... Original
datasheet

56 pages,
821.6 Kb

encoder 74174 74823 FULL ADDER 7474 j-k flip flop 74139 mux full subtractor circuit using nor gates 74138 TTL 74139 7400 QUAD Nor 74594 74171 data sheet 74139 3-input-XOR 74138 decoder vhdl code for 8-bit BCD adder 7474 D flip-flop 74138 full subtractor TEXT
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Abstract: , NAND, and OR gates with two to six inputs. At each input count, all numbers of inversion bubbles are , also features the largest possible AND, NOR, NAND, and OR gates which can be implemented in a single , circuit board as well. You may create inverting HD2PADs or HD3PADs by using multiple HDiPADs and tying , includes AND, OR, NAND, and NOR gates with two to six inputs with each input invertable. As well, a very , . This macro's design takes advantage of theXOR utilization property-two AND gates and a 3-input XOR ... QuickLogic
Original
datasheet

60 pages,
603.93 Kb

8 shift register by using D flip-flop 7474 shift register schematic of TTL XOR Gates d-latch by using D flip-flop 7474 TTL 7400 full subtractor circuit using nor gates CI 74139 verilog code of 8 bit comparator 74823 FULL ADDER vhdl code for 8-bit BCD adder 3-8 decoder 74138 74138 full subtractor vhdl code for 74194 7478 J-K Flip-Flop vhdl code for 74154 4-to-16 decoder 7474 D flip-flop TEXT
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Abstract: Verilog constructs and meta comments. Chapter 8, "Command Line Mode," describes how to run XST using the , Description Using Combinatorial Process and Always Block . 2-29 VHDL Code , , XC2064 XC2064, XC3090 XC3090, XC4005 XC4005, XC5210 XC5210, and XC-DS501 XC-DS501 are registered trademarks of Xilinx, Inc. The shadow X , , XACT-Performance, XAM, XAPP, XBLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, Xilinx Foundation Series, XPP, XSI, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array ... Xilinx
Original
datasheet

336 pages,
1078.34 Kb

411 mux verilog code for 16 bit inputs 8 bit adder subtractor ABSTRACT MODEL 8 bit subtractor 8x4 bit binary multiplier 8x4 ram vhdl UNSIGNED SERIAL DIVIDER using vhdl verilog code for johnson decoder verilog code for half subtractor ieee vhdl verilog code for johnson counter UNSIGNED SERIAL DIVIDER using verilog 8 bit carry select adder verilog codes TEXT
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Abstract: Turbo Path for ispLSI5000V and 8000 devices. XOR Net Identifies XOR gates on a net that are , . . . . . . . . . . . . . . . . . Using IN, OUT, and BIDI Pins . . . . . . . . . . . . . . . . . . , Attributes to designs created in Viewlogic Creating and using macros, including programmable macros , Provides information for compiling designs using the ispEXPERT Compiler and Viewlogic software. Chapter 7 , documentation is useful when using the ispEXPERT Compiler and Viewlogic software: Lattice Semiconductor s ... Lattice Semiconductor
Original
datasheet

159 pages,
593.52 Kb

OT11 FD31 MUX24 OD34E Application Schematic SCPC 8 bit adder netlist 7-segment LED display 1 to 99 vhdl vhdl code for full subtractor VHDL Lattice Macros DMUX viewlogic Software CBU441 quad design motive vhdl code for 8-bit serial adder 1-800-LATTICE "8 bit full adder" 1-800-LATTICE 8 bit full adder 1-800-LATTICE 1-800-LATTICE 1-800-LATTICE TEXT
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Abstract: , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND ... Original
datasheet

448 pages,
3668.56 Kb

ami equivalent gates rtl 8112 tda 8210 na51 datasheet tda 4020 UNSIGNED SERIAL DIVIDER using verilog na44 AN62 NA51 transistor data sheet DF101 am 2901 verilog NA51 transistor datasheet IC TDA 2208 vhdl code M8490 Elcom rda 5807 sp fm receiver ic rda 5807 rda 5807 sp TEXT
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Abstract: srlab1 srlab2 Subtractor su01d1 Power and Ground Cells vddcon vsscon Exclusive NOR Gates , fabricates CBICs using one of the following CMOS silicon processes: ECPD07 ECPD07 AT19.8K 5V and 3V , test vectors is developed for the design, and verified using Atmel's FAST tools. This is to ensure , analysis, floorplanning, hierarchical placement and routing, delay estimation and calculation using , ATPG Design Rules Check, Full Scan Path Insertion, ATPG Vector Generation and Fault Coverage ... Atmel
Original
datasheet

41 pages,
312.46 Kb

barrel shifter using verilog 16 bit single cycle mips vhdl nd02d4 OAI31 AOI21 AOI32 AT55K AT56K vhdl code for 8 bit barrel shifter XP-140 NA2D atmel 0532 8 bit barrel shifter vhdl code or03d1 ECPD07 MX 0541 OAI221 atmel 0928 AOI221 TEXT
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Abstract: , Boston, Portland, Dresden, and Tokyo, which offer customers a full range of digital ASIC design , , achieving world-class reliability, and designing to customer need. AMI provides a full range of digital , , high noise immunity, and high circuit densities to digital and mixed-signal ASICs. ASIC Design , .3-181 ON5x 2-input OR and 3-input OR into 2-input NAND , .3-189 ON9x 2-input OR and 3-input OR into 3-input NAND ... Original
datasheet

440 pages,
3613.66 Kb

256X8* sram NA76 verilog hdl code for parity generator power transistor na51 8250 uart phillips am 2901 verilog AMIS 690 tda 4020 8 BIT ALU design with verilog/vhdl code na2x NA51 transistor data sheet AMI MG82C54 NA52 transistor datasheet 8085 microprocessor simulator NA51 transistor datasheet rtl 8112 tda 8210 TEXT
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Abstract: about using the Designer series software and the Synopsys documentation for additional information about , describes the design flow for creating Actel designs using Synopsys and Designer Series software. Chapter 3 , . Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for using design , information for using the Designer Series Development System software to create designs for, and program , design of Actel devices using Cadence CAE software and the Designer Series software. Mentor Graphics ... Actel
Original
datasheet

151 pages,
1717.8 Kb

vhdl code for Booth multiplier structural vhdl code for ripple counter 8 bit carry select adder verilog code booth multiplier code in vhdl Booth algorithm using verilog 8 bit booth multiplier vhdl code TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/5692482-988247ZC/wcd03623.zip ()
Xilinx 12/02/1999 571.77 Kb ZIP wcd03623.zip
No abstract text available
/download/93627041-987072ZC/wcd02e3f.zip ()
Xilinx 13/07/1998 571.77 Kb ZIP wcd02e3f.zip
No abstract text available
/download/66124278-995866ZC/mfrd_source_code.zip ()
Xilinx 11/11/2004 958.87 Kb ZIP mfrd_source_code.zip
No abstract text available
/download/80892771-299169ZC/eagle-m11-eng-4.15.tar
Kaleidoscope 08/06/2005 34650 Kb TAR eagle-m11-eng-4.15.tar
No abstract text available
/download/90447169-299171ZC/eagle-m11-eng-4.15.tar
Kaleidoscope 08/06/2005 34650 Kb TAR eagle-m11-eng-4.15.tar
No abstract text available
/download/26794946-996405ZC/verilog.tar
Xilinx 20/01/1997 13424.65 Kb TAR verilog.tar