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Abstract: for54LS/74LS Figure 1 PROPAGATION DELAY B INPUT TO Q AND Q OUTPUT, AND INPUT AND OUTPUT PULSE WIDTHS fZ ... OCR Scan
datasheet

4 pages,
138.39 Kb

N74221N S54LS221W S54LS221F S54221W S54221F N74LS221N N74LS221F 74LS PINOUT N74221F 74LS221 P TTL 74 pinout 54221 74221 74LS221 /74LS 74LS221 /74LS abstract
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Abstract: mode or reaches *15* in the count-up mode for54LS191. The TC output w ill remain High until a state ... OCR Scan
datasheet

9 pages,
425.42 Kb

54LS191 datasheet abstract
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Abstract: 54/74259-See 9334 54LS / 74LS259 74LS259 (Preliminary data) LOGIC SYMBOL DESCRIPTION The "259" is an 8-Bit Addressable Latch with these control inputs; three Address inputs (Aq, Ai, A2). an active LOW Enable input (E) and an active LOW Clear input (CLR). Each latch has a common D input and a separate Q output. The "259" combines the features of a 1-of-8 demultiplexer and 8bit transparent latch into one 16 pin package. FEATURES • Combines demultiplexer and 8-bit latch « Serial-to-Parallel capabilit ... OCR Scan
datasheet

4 pages,
137.77 Kb

S54LS259W 74LS259 54LS N74LS259F N74LS259N NE590 S54LS259F demultiplexer 74ls 8bit latch 74ls 74259 latch 74259 /74LS /74LS abstract
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Abstract: 54/74196 - See 8290 54S/74S196 54S/74S196 - See 82S90 82S90 54LS/74LS196 54LS/74LS196 LOGIC SYMBOL FEATURES • Performs BCD or Bi-quinary counting • Asynchronous parallel load for presetting counter • Overriding Master Reset • Buffered Qo output drives CP-| input plus standard fan-out • See 82S90 82S90 for faster version DESCRIPTION The "196" is an asynchronously presettable Decade Ripple Counter. It is partitioned into divide-by-2 and divide-by-5 sections which can be combined to count in either BCD (8421) mode or bi-quin ... OCR Scan
datasheet

5 pages,
151.91 Kb

S54LS196W S54LS196F N74LS196N N74LS196F counter 54LS/74LS BCD counter circuit diagram max plus pin diagram decade counter 74196 82s90 74S196 82S90 54LS/74LS196 82S90 abstract
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Abstract: 54/74190 54LS/74LS190 54LS/74LS190 LOGIC SYMBOL DESCRIPTION FEATURES The "190" is a presettable BCD/Decade Up/Down Counter with state charges of the counter synchronous with the LOW-to-HIGH transition of the Clock Pulse input. The circuit features an asynchronous Parallel Load (PL) input which overrides counting and loads the data present on the Dn inputs into the flip-flops. Synchronous expansion in a multistage counter is made possible by a Count Enable (CE) input. The count up or count down mode is de ... OCR Scan
datasheet

5 pages,
200.72 Kb

truth table of 74LS190 74LS190 APPLICATIONS counter 54LS/74LS counter 74190 N74190F N74190N N74LS190F N74LS190N S54LS190W S54LS190F S54190W S54190F 74LS190 up down decade counter 54LS/74LS 54LS/74LS abstract
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Abstract: 54/74197-See 8291 54S/74S197-See 82S91 82S91 54LS/74LS197 54LS/74LS197 LOGIC SYMBOL 10 3 11 FEATURES • High speed 4-bit binary counting • Asynchronous parallel load for presetting counter • Overriding Master Reset _ « Buffered Qo output drives CPt input plus standard fan-out • See 82S91 82S91 for faster version DESCRIPTION The "197" is a 4-Stage Presettable Ripple Counter containing divide-by-2 and divide-by-8 sections which can be combined to form a modulo-16 binary counter. The circuit has a Master Reset (M ... OCR Scan
datasheet

5 pages,
144.58 Kb

S54LS197W S54LS197F N74LS197N N74LS197F counter 54LS/74LS 82S91 54LS/74LS197 82S91 abstract
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Abstract: 54LS/74LS379 54LS/74LS379 (Preliminary data) LOGIC SYMBOL DESCRIPTION The "379" is a Quad edge-triggered D FlipFlop with a common buffered clock and an edge-triggered Clock Enable input. Data on the D inputs is transferred to storage during the LOW-to-HIGH transition of the clock pulse. Each flip-flop has both true (Q) and complement (Q) outputs useful for general purpose flip-flop applications and simple latch/decoding schemes. FEATURES « Four edge-triggered D flip-flops • Both true and complement out ... OCR Scan
datasheet

3 pages,
98.48 Kb

S54LS379W S54LS379F N74LS379N N74LS379F d flipflop datasheet abstract
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Abstract: 5477 54LS77 54LS77 LOGIC SYMBOL DESCRIPTION The "77" is a Duai 2-Bit D-Latch offered in a 14-Pin flat pack. Two Enable inputs are provided; each controls two latches. When the Enable (E) is HIGH, information present at a Data (D) input is transferred to the Q outputs, and the outputs will follow the data input as long as the Enable remains HIGH. The information that is present at the data input one setup time prior to the HIGH-to-LOW Enable transition is stored in the latch until the Enable returns ... OCR Scan
datasheet

3 pages,
87.42 Kb

S54LS77W S5477W 54LS77 741s 54LS77 abstract
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Abstract: 54LS/74LS399 54LS/74LS399 (Preliminary data) LOGIC SYMBOL DESCRIPTION The "399" is a Quad 2-Port Register which combines the functions of a quad 2-input multiplexer and a 4-bit positive edge triggered register. The state of the common Select input (S) determines the source of the data loaded into the register synchronous with the LOW-to-HIGH Clock (CP) transition. FEATURES • Fully synchronous operation • Select from two data sources • Buffered, positive edge triggered clock • See "398" for true and c ... OCR Scan
datasheet

3 pages,
91.88 Kb

S54LS399W S54LS399F N74LS399N N74LS399F 74LS 04 functions 74LS399 datasheet abstract
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Abstract: 54/74162 54LS/74LS162A 54LS/74LS162A LOGIC SYMBOL DESCRIPTION The "162" is a high-speed BCD decade counter. The counters are positive edge-triggered, synchronously presettable and are easily cascaded to n-bit synchronous applications without additional gating. A Terminal Count output is provided which detects a count of HLLH. The Synchronous Reset is edge-triggered. It overrides all control inputs; but is active only during the rising clock edge. ORDERING CODE (See Section 9 for further Package and Orderi ... OCR Scan
datasheet

5 pages,
211.35 Kb

S54LS162AW LS162 N74162F N74162N N74LS162AF 16 INPUT TO BCD OUTPUT S54LS162AF S54162W S54162F 74LS162 74162 LOAD N74LS162AN pin diagram of 74162 counter 74162 54LS/74LS162A 54LS/74LS162A abstract
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Abstract: 5 4 L S /7 4 L S 3 7 9 (Prelim inary data) DESCRIPTION The ''3 7 9 " is a Quad edge-trigge red D FlipFlop w ith a common buffered c lo c k and an ed ge-triggered C lock Enable input. Data on the D inputs is transferred to s torage during th e LOW -to-HIGH tra n s itio n of th e c lo c k pulse. Each flip-flo p has both true (Q ) and com plem ent (Q ) outputs useful for general purpose flip -flo p ap p lic a tio n s and sim ple la tc h /d e c o d in g schem es. LOGIC SYMBOL FEATURES · Four ... OCR Scan
datasheet

3 pages,
167.19 Kb

datasheet abstract
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