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Part Manufacturer Description Datasheet BUY
SN74ACT7802-XXFN Texas Instruments 1KX18 OTHER FIFO, PQCC68 visit Texas Instruments
SN74ALVC7804-20DL Texas Instruments 512X18 OTHER FIFO, PDSO56 visit Texas Instruments
SN74ACT7801-20PN Texas Instruments 1KX18 OTHER FIFO, PQFP80 visit Texas Instruments
SN74ACT7801-20PNR Texas Instruments 1KX18 OTHER FIFO, PQFP80 visit Texas Instruments
SN74ACT7802-28.5FN Texas Instruments 1KX18 OTHER FIFO, PQCC68 visit Texas Instruments
SN74ACT7805DL Texas Instruments 256X18 OTHER FIFO, PDSO56 visit Texas Instruments

fifo ttl

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: , TTL) RESET when LOW clears the FIFO address counters and sets the internal registers to zero. Data , provided to load the Data Serializer from the FIFO. Start Bit Strobe (Input, TTL) The start bit , clock. FIFO Full (Output, TTL) FULL goes HIGH on reset and stays HIGH until there are more than 56 bytes in the FIFO. FULL w ill go HIGH again when there are less than 56 bytes in the FIFO. TTL , Am8172 Video Data Assembly FIFO (VDAF) PRELIMINARY DISTINCTIVE CHARACTERISTICS â'¢ â'¢ â -
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Abstract: and looped back out TXOUTA/B (B1CALCEN = X). TTL A logic 1 causes frame alignment FIFO's to be , , FRALIGNRST resets only the unselected channel alignment FIFO. TTL Selects which input channel, RXINA , ] TXCLK+/TXCLK_SRC+/- 16 bit 155MHz 4 bit 622MHz Retiming FIFO TXOUTA+/- 2:1 MUX [15:0 , inputs operating at 155MHz or 622MHz, respectively, into an internal FIFO using source synchronous , signals and large internal FIFO for tolerance of up to +/- 75ns of serial backplane skew â'¢ Realignment Vitesse Semiconductor
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FM1702SL

Abstract: fm1702 ) 10cm ISO14443 typeA SPI 512byte EEPROM 64byte FIFO TTL/CMOS power down 3V 5V SOP24 2 FIFO EEPROM EEPROM CRC , _51 7 FIFO 7.1 7.2 7.3 7.4 7.5 FIFO _53 FIFO
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FM1702SL fm1702 ISO1443A IEC3309 ISO1443 CRC3309 197RX 1910SPI 194SPI 231SOP24

SC16C550B

Abstract: the 16C450. The SC16C550B also provides DMA mode data transfers through FIFO trigger levels and the , operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V 16 byte transmit FIFO 16 byte receive FIFO with , selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface , status reporting capabilities s 3-state output TTL drive capabilities for bi-directional data bus and , SC16C550B TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TX D0 to D7 IOR, IOR IOW, IOW RESET DATA
Philips Semiconductors
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ST16C550 TL16C550 PC16C550 HVQFN32 DIP40 PLCC44

transistor AC126

Abstract: equivalent transistor ac125 AC161 ACT161 FUNCTION Quad 2-Input NAND Gate Quad 2-Input NAND Gate (TTL Compatible) Quad 2-Input NAND Gate (Open Drain) Quad 2-Input Positive-NOR Gate Quad 2-Input Positive-NOR Gate (TTL Compatible) Quad 2-Input NAND Gate (Open Drain) Quad 2-Input NAND Gate (Open Drain - TTL Compatible) Hex Inverter Hex Inverter (TTL Compatible) Hex Inverter (Unbuffered) Hex Inverter w/ Open-Drain Output Hex Inverter w/ Open-Drain Output(TTL Compatible) Hex Buffer w/ Open-Drain Output Quad 2-Input NAND Gate
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ACT03 AC125 AC126 74ACT16475 transistor AC126 equivalent transistor ac125 AC393 74AC393 AC365 ACT00 ACT02 ACT04 ACU04 ACT05

7805 ACT

Abstract: FB 3306 LS S TTL AC ACT AHC AHCT ALVC HC HCT LV LVC OTHER FIFO '7806 , BIPOLAR BCT LVT ALS AS F LS CMOS S TTL AC ACT AHC AHCT '1G04 ' ' , '01 * · '00 BiCMOS ALB ALVT BCT LVT ALS AS F LS CMOS S TTL , BCT LVT ALS AS F LS CMOS S TTL AC ACT AHC AHCT ' ' '157 , LS CMOS S TTL AC ACT AHC AHCT I ALVC HC HCT LV LVC OTHER I
Texas Instruments
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7805 ACT FB 3306 ahct 367 Cmos 74 HC 1G14 ACT 4060 A 1GU04

1030J6C

Abstract: 1030J6A size of the FIFO by leaving open 7 x 64 . . . 1 x input pins must Value TTL TTL TTL TTL TTL TTL TTL , , the outputs of the FIFO are TTL compatible. When disabled (OE HIGH), the outputs go into their , he T R W T D C 1 0 3 0 is an expandable, First-In First-Out (FIFO ) m em ory organized as 64 w o rd s , ond ing input pins, facilitating board layouts in ex p an ded form at. All inputs and outputs are TTL , 1 3 M H z · R ead ily Exp and able In W o rd A n d B it D im ension · TTL C om patib le · A synchro
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TDC1030B6C 1030J6C 1030J6A C1030B 18MFH C1030B6A TDC1030C3C TDC1030C3A C1030J6C

TRW 1030J6C

Abstract: 1030J6C state of power up. With the OE LOW, the outputs of the FIFO are TTL compatible. When disabled (OE HIGH , expandable, First-ln First-Out (FIFO) memory organized as 64 words by 9 bits. A 15MHz data rate makes it , , facilitating board layouts in expanded format. All inputs and outputs are TTL compatible. Features â'¢ 64 , '¢ TTL Compatible â'¢ Asynchronous Or Synchronous Operation â'¢ Three-State Outputs â'¢ Master Reset , Description Data Input (Figure 1) Following power up, the Master Reset IMRI is pulsed LOW to clear the FIFO
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TDC1030 TDC1030B6A TRW 1030J6C SO-64 1030B6C 1030B6A 1030C3C 1030C3A

MAC8110

Abstract: MAC110 signals to indicate that a threshold number of locations TTL Output are available in the transmit FIFO , -bit FIFO transfer using these signals. TTL l/O R/W* FIFO Read/FlFO Write. The host asserts this , ; when LOW, the pin indicates a write operation. TTL Input TREN* Transfer Enable. Enables FIFO transfers. TTL Input SOF Start of Frame. The FIFO data originator asserts this signal HIGH to , being written or read is the last word in the frame. TTL l/O DATA[63:0] FIFO Data Bus. Carries
OKI Electric Industry
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ML53101 MAC8110 MAC110 100-M

ML53101

Abstract: MAC110 of bytes are TTL Output available in the receive FIFO on the indicated port. TXDRDY[7:0 , data transfer. TTL Input BVAL[7:0] Byte Valid. The FIFO data originator indicates the validity of respective data bytes within the 64-bit FIFO transfer using these signals. TTL l/O R/W , Input TREN* Transfer Enable. Enables FIFO transfers. TTL Input SOF Start of Frame. The , is the first word in the frame. TTL l/O EOF End of Frame. The FIFO data originator asserts
OKI Electric Industry
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interlace parity

Abstract: MAC layer sequence number in the frame. FIFO Data Bus. Carries data for the FIFO interface. TTL Input TTL I/O I/O TTL , 8 M il inter faces on one side and with shared first-in, first-out queue (FIFO) and peripheral , ) support. · Shared 64-bit, 66-MHz FIFO Interface for TX and RX data transfer. · FIFO bus bandwidth exceeds , Frame Status can be appended at the end of a frame as an additional 64-bit data word on the FIFO Interface. · Independent dual-port RX and TX FIFOs for each MAC. · Programmable FIFO burst size of 32/ 64
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interlace parity MAC layer sequence number 66-MH

CY7C9689-AC

Abstract: CY7C42X5 to The TTL parallel I/O interface may be configured as either a FIFO (configurable for depth , TTL clock input Transmit FIFO Clock. Used to sample all Transmit FIFO and related interface , TXBISTEN is HIGH. All Transmit FIFO read operations are suspended when BIST is active. TTL input , . When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL input , continue loading data into the Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL
Cypress Semiconductor
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CY7C9689 CY7C9689-AC CY7C9689-AI CY7C42X5 100-L 100-P

CY7C42X5

Abstract: CY7C9689 additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for , active. 16 TXRST TTL input, sampled on TXCLKt Reset Transmit FIFO. When the Transmit FIFO is enabled , TTL output, changes following TXCLKt or REFCLKt Transmit FIFO Full status flag. When the Transmit FIFO , . Receive Path Signals 8 RXCLK Bidirectional TTL clock Receive clock. When the Receive FIFO is enabled , rxrst TTL input, sampled on rxclkT Receive FIFO Reset. Active LOW. When the Receive FIFO is enabled
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4b/5b encoder AM7968/7969
Abstract: additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for , Path Signals 68 TXCLK TTL clock input Transmit FIFO Clock. CY7C9689 Used to sample all Transmit FIFO and related interface signals. 44,42, TXDATA[7:0] 40,36, 34,32, 30, 22 TTL input, sampled on , TTL input, sampled on Reset Transmit FIFO. TXCLKt When the Transmit FIFO is enabled (FIFOBYP is HIGH , asserted. When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL -
OCR Scan
Abstract: for additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO , Signal Description Transmit Path Signals 68 TXCLK TTL clock input Transmit FIFO Clock. Used , TXBISTEN is HIGH. All Transmit FIFO read operations are suspended when BIST is active. TTL input , . When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored. 9 TXHALT TTL input , continue loading data into the Transmit FIFO while TXHALT is asserted. 72 TXFULL Three-state TTL -
OCR Scan

OXPCI958

Abstract: AT96C46 Supports both 5.0-V & 3.3-V PCI signalling 32-byte deep FIFO per transmitter & receiver Baud rates up to , enhancements: · Clock prescaler allows more baud rate options · Readable FIFO levels & tuneable trigger , the receive FIFO. The state of the UART can be found at any time by reading status registers, and , by using the prioritised interrupt identification register, readable FIFO levels, and tuneable FIFO , Registers 4.3. Serial Data Format 4.4. Transmitter/Receiver Section 4.5. FIFO Interrupt Mode Operation
Oxford Semiconductor
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OX16PCI958 16C550 OXPCI958 AT96C46 PU5103 at96c 16C550/450 C--70 DS-0022 OX16PCI958-PQAG

AM8172

Abstract: used and four bits FDCC FIFO Full (Output, TTL) FULL goes HIGH on reset and stays HIGH until there are , rising edge of DOTCLK. ftESfeT Reset (input, TTL) RESET when LOW clears the FIFO address counters and , Am8172 Video Data Assembly FIFO (VDAF) _PRELIMINARY_ DISTINCTIVE CHARACTERISTICS â'¢ Supports , '¢ 10KH ECL with pixel rates of up to 200 MHz GENERAL DESCRIPTION The Am8172 Video Data Assembly FIFO is a , ALU, a 64 x 8 FIFO, and a Data Serializer. The Data Assembly ALU accepts display memory data as either
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AM8172 TC002852 TC002661 WF024701 WF024710

BD005

Abstract: AM8172 FDCC FIFO Full (Output, TTL) FULL goes HIGH on reset and stays HIGH until there are more than 56 bytes , DOTCLK. ftESfeT Reset (input, TTL) RESET when LOW clears the FIFO address counters and sets the internal , Am8172 Video Data Assembly FIFO (VDAF) _PRELIMINARY_ DISTINCTIVE CHARACTERISTICS â , '¢ 10KH ECL with pixel rates of up to 200 MHz GENERAL DESCRIPTION The Am8172 Video Data Assembly FIFO is , ALU, a 64 x 8 FIFO, and a Data Serializer. The Data Assembly ALU accepts display memory data as
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BD005 AM8172DC

dp8512

Abstract: vlt 2900 required in high performance raster scan video systems. Also on the VSR are four words of FIFO which by , configured as flip-flops (one word FIFO mode), and four word FIFO mode. As mentioned above, the mode control , CLOCK input shifts data out of the shift register. In the four word FIFO mode, four write operations may , written data. The four words of FIFO significantly ease the timing constraints which are present when , associated with the shift register, are TTL compatible. The shift register in- puts and control signals are
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dp8512 vlt 2900 DP8515/DP8515-350/ DP8516/DP8516-350 DP8515/DP8515-350/DP8516/DP8516-350 D-8000 AA32096

als007

Abstract: ALS120 Characteristic Definition 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL compatible CMOS IO (Vt=1.7V) 6mA TTL
Avance Logic
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ALS300 ALS120 als007 Avance Logic MX365 Application data MX08 TAG 8646 RL5305 P-160 P-128 OCT-10 82371AB
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