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e200z7

Catalog Datasheet MFG & Type PDF Document Tags

MPC5674

Abstract: MPC5674F Semiconductor Core 4 Core The MPC5674F employs the e200z7 core, instead of the e200z6 core used on the MPC5566. The e200z7 core is instruction-set equivalent with the e200z6 core, however some new instructions and features are added to the e200z7. The essential differences in the two cores are described in , the machine check cause in the MCSR register. Refer to Freescale document e200z7RM, e200z7 PowerPCTM , e200z6 e200z7 SIMD Yes Yes VLE Yes Yes Cache 32 KB 32 KB (16 KB I/16 KB D
Freescale Semiconductor
Original
AN3903 MPC567 MPC5674 e200z7 MPC5673F MPC5674F manual MPC5674F flash

e200z7 instruction

Abstract: e200z7 MPC5676R employs two e200z759 cores, instead of the single e200z760 core used on the MPC5674F. The e200z759 , targeted for powertrain applications. The two e200z7 host processor cores of the MPC5676R are compatible , and functionality of the MPC5676R. Power Architecture e200z7 Core Power Architecture e200z7 Core , Table 1. MPC5674F/MPC5676R feature comparison Feature MPC5674F MPC5676R Core e200z760 e200z759 Number of cores 1 2 MMU entries 64 32 per core Software Watchdog Timer (SWT
Freescale Semiconductor
Original
e200z7 instruction AN4175

MPC5674

Abstract: MPC5566 instruction set 4 Core The MPC5674F employs the e200z7 core, instead of the e200z6 core used on the MPC5566. The e200z7 core is instruction-set equivalent with the e200z6 core, however some new instructions and features are added to the e200z7. The essential differences in the two cores are described in the , the machine check cause in the MCSR register. Refer to Freescale document e200z7RM, e200z7 PowerPCTM , e200z6 e200z7 SIMD Yes Yes VLE Yes Yes Cache 32 KB 32 KB (16 KB I/16 KB D
Freescale Semiconductor
Original
MPC5566 instruction set MPC5674F instruction set microsecond bus MPC567xF EB716 MPC5674* memory 496CSP

MPC5600

Abstract: AN3970 cores are the e200z0, e200z1, e200z3, e200z4, e200z6, e200z6 with VLE, and the e200z7. Some devices , Nexus e200z7 Class 3+ IEEE-ISTO 5001TM-2010 1 Class 3+ NZ7C3 Nexus e200z7 Class 3+ IEEE-ISTO 5001TM-2010 e200z759 e200z760 1. Generically, both the e200z759 and the e200z760 are , e200z6 PowerPC Core Reference Manual e200z7RM e200z760 Power Architecture Core Reference Manual , NXDM_B NXFR e200z7 MMU eTPU2 D-Cache I-Cache eDMA2_A eDMA2_B FlexRay Reserved
Freescale Semiconductor
Original
MPC5500 MPC5600 AN3970 e200z4RM IEEE-ISTO Nexus S e200z446 AN4088 MPC5500/MPC5600 5001TM

MPC5676R

Abstract: drive an unknown value immediately after power up but before the 1st clock edge 4396 e200z7 , used, the pins may be left unconnected. e4396: e200z7: Erroneous Address Fetch Errata type: Errata , e200z7 core can issue an errant fetch address to the memory system (instruction fetched from wrong , : Exceptions generated on speculative prefetch Errata type: Errata Description: The e200z7 core can prefetch
Freescale Semiconductor
Original
3N23A CRC-32 CRC-16 LVREH/LVREA/LVRE50

MRD2001

Abstract: A comprehensive suite of hardware and In addition to the two 266 MHz e200z7 processing cores and , -bit DAC CPU Platform Processing cores: 2x e200z7 (266 MHz) Functional safety core2: e200z4 in
Freescale Semiconductor
Original
MRD2001 MPC577 AEC-Q100

4/MPC5674F manual

Abstract: 4396 e200z7: Erroneous Address Fetch 3419 e200z: Exceptions generated on speculative prefetch , Nexus Read/Write Access registers cleared by system reset Errata type: Errata Description: The e200z7 , after changing it to the external clock. e4396: e200z7: Erroneous Address Fetch Errata type: Errata , e200z7 core can issue an errant fetch address to the memory system (instruction fetched from wrong , e3419: e200z: Exceptions generated on speculative prefetch Errata type: Errata Description: The e200z7
Freescale Semiconductor
Original
4/MPC5674F manual 3M17W

IVOR33

Abstract: chapter of document number e200z760RM, e200z760n3 Power Architecture Core Reference Manual. Table 1. SRR0 register behavior for each IVORx exception (e200z7 core) IVORx number IVORx name SRR0 , debug register, so it is not accessible by the main core. See e200z760RM, e200z760n3 Power Architecture , e200z760RM Title e200z760n3 Power Architecture Core Reference Manual VLEPEM freescale.com , the SRR0 register for the e200z7 core. For further information, refer to the "Debug © 2013
Freescale Semiconductor
Original
IVOR33 AN4648 MPC56

Bosch ICs

Abstract: e200z7 "¢ PowerPCâ"¢ e200Z7 e200420 Powerâ"¢ e200Z7 SWT Powerâ"¢ e200Z7 STM INTC FPU FPU MCM
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Original
Bosch ICs LINFlex PROTOCOL ISO26262 200MH 300MH MPC5646C

"microsecond bus"

Abstract: MPC5674 Benefits e200z7 core built on Power Architecture technology at 264 MHz SIMD module for DSP and
Freescale Semiconductor
Original
SPC5674FMVY264 PPC5674FMVYA264 PPC5674FMVRA264 MPC5674FXKIT516 MPC5674ADAT516 gasoline direct injection SPC5674 knock detection SPC5674FMVR264 SPC5674FMVZ200 PPC5674FMVZA200

e200z7

Abstract: e200z760n3 e200z760n3 Power Architecture® Core Reference Manual Supports e200z760n3 e200z760RM Rev. 0 , @hibbertgroup.com Document Number: e200z760RM Rev. 0, 06/2010 or for any other application in which the , . xliii Chapter 1 e200z7 Core Complex Overview 1.1 1.1.1 1.2 1.2.1 1.2.2 1.2.2.1 1.2.3 1.2.3.1 1.2.3.2 1.2.3.3 1.2.3.4 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 e200z7 Overview , ) . 2-11 e200z760n3 Power Architecture® Core Reference Manual, Rev. 0 Freescale Semiconductor
Freescale Semiconductor
Original
e200z760n3 e200z760 csc 9102 IVOR10 IVOR13 dcwm 760RM EL516

e200z7

Abstract: MPC5674 e200z7: Erroneous Address Fetch 3419 e200z: Exceptions generated on speculative prefetch 6966 , /Write Access registers cleared by system reset Errata type: Errata Description: The e200z7 Nexus Read , . e4396: e200z7: Erroneous Address Fetch Errata type: Errata Description: Under certain conditions, if a , ) occur simultaneously in the Branch Target Buffer (BTB), the e200z7 core can issue an errant fetch , type: Errata Description: The e200z7 core can prefetch up to 2 cache lines (64 bytes total) beyond the
Freescale Semiconductor
Original

MPC57xx instruction set

Abstract: e200z7 e200z759n34 e200z759n3 â'" Core 1 (e200z758) MPC5777M 13 e200z720n3 e200z720n3 , e200z720n3 No Single e200z720 based cores No Dual e200z7260 based cores MPC5775K 1.0/1.1 , Core 0/1 e200z710n3 MPC5777M 1.0 Core 0/1 e200z720n3 24 Yes e200z720 based cores 24 Yes e200z7260 based cores MPC5775K 1.0/1.1/ Core 1/2 e200z7260n3 2.0 24 Yes e200z759 , 1/2 e200z7260n3 3+ e200z759 based cores Future device 2 1.0 Core 0/1 e200z759n3
Freescale Semiconductor
Original
MPC57xx instruction set e200z420n3 MPC5775 freescale mpc5777M MPC5744P AN4802 MPC57 MPC555
Abstract: TWR-PXR40 Features â'¢ MPXR4040VVU264 MCU (Up to 264 MHz 32-bit e200z7 core, up to 4 MB on-chip flash Freescale Semiconductor
Original
RS485 MC9S08JM60 TWRPXR40QSG

MPC5675K

Abstract: e200z7d with ECC Harvard Execution speed e200z7 core · 16K D cache and 16K I cache Yes (SoR , Enhanced direct memory access 2 · 3 x eTimer (3 x 6 channels) MPC5675Ke200z7d (SoR) in
Freescale Semiconductor
Original
MPC5561 LVD12 HVD12 e200z7d MPC567xK MPC5673 sram ecc eTimer MPC5673K MPC5500/5600 IRCOSC--16 LVD27
Abstract: '¢ High-performance 180 MHz e200z7 dual cores â'¢ Dual processing spheres, including: CPU, DMA, interrupt Freescale Semiconductor
Original
TWR-PXS3020 TWR-PXS30 PXS30QSG

PowerVR SGX540

Abstract: e200z7 instruction Qorivva 57A7 Performance Power Safety TM Performance 1700 DMIPS 2 x zen e200z7 @266MHz , Fusion Module â'" ASIL D 2 x Qorivva 57A7 Performance 3400 DMIPS 4 x zen e200z7 @266MHz 16K I-cache
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Original
PowerVR SGX540 Nexus S camera SGX535 58A-8 MX58A 600/800MH 264/GPU SCP2201/07 350MH MPC560

voltage regulator ana 618 -28239

Abstract: voltage regulator ana 618 21153 1.1.8.1 High-Performance e200z7 Core Processor . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.8.2 , 11-25 11-26 11-26 11-29 11-29 11-30 11-32 11-33 Chapter 12 Core (e200z7) Overview 12.1
Freescale Semiconductor
Original
MPC5674FRM voltage regulator ana 618 -28239 voltage regulator ana 618 21153 mdu 2657 voltage regulator ana 618 21156 mPC5764

MPC5676R

Abstract: MPC5676RRM e200z7 cores. Using the Development Trigger Semaphore Module , Rev. 0, 31/August/2010 2 Freescale
Freescale Semiconductor
Original
MPC5676RRM st5027 bosch edc 17 MAC MTA E200 ssy 1920 8 pin bosch edc 17 calibration maps MIOS200
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