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TMS320C6474GUN Texas Instruments IC OTHER DSP, Digital Signal Processor ri Buy
TMS320C6474ZUN Texas Instruments IC OTHER DSP, Digital Signal Processor ri Buy
TMS320LBC53PQ57 Texas Instruments Digital Signal Processor 132-BQFP ri Buy

dsp bus clock interface aynchronous

Catalog Datasheet Results Type PDF Document Tags
Abstract: derivatives) features an External Bus Interface Unit (EBIU) which provides interface to the external memory devices. The EBIU supports interface for the synchronous and asynchronous memory banks. The data bus on the ADSP-BF533 ADSP-BF533 EBIU is 16 bits wide. This EE-Note discusses a hardware interface scheme between the ADSP-21365 ADSP-21365 PDAP port and the EBIU interface on an ADSP-BF532 ADSP-BF532 processor. Since the EBIU is 16 bits wide, the , Signals to the Blackfin The External Bus Interface Unit (EBIU) on Blackfin processors ... Original
datasheet

16 pages,
76.59 Kb

EE-254 bf532 ADSP21365 ADSP-BF533 ADSP-BF532 ADSP-BF531 ADSP-21365 EE-254 abstract
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Abstract: . . . . . . . . . . . . . . . . . 7 7 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode , clock is 2.89 MHz. The DSP serial interface port standard configuration provides a 10-MHz clock that , FSR NOTE: Fixed data clock is only possible with VDD = 5 V. Figure 2. Standard ADC/DSP Interface , Figure 7. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = High) At the tenth , . . . . . . . . . . . . . . . . . . . . . . . 2 2 Standard ADC/DSP Interface . . . . . . . . . . . ... Original
datasheet

38 pages,
149.91 Kb

TPS7101 TMS320C50 TMS320C203 TLV1548 dsp processor Architecture of TMS320C5X TLV1544 schematic diagram inverter delta free TLV1544 abstract
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Abstract: . . . . . . . . . . . . . . . . . 7 7 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode , clock is 2.89 MHz. The DSP serial interface port standard configuration provides a 10-MHz clock that , FSR NOTE: Fixed data clock is only possible with VDD = 5 V. Figure 2. Standard ADC/DSP Interface , Figure 7. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = High) At the tenth , . . . . . . . . . . . . . . . . . . . . . . . 2 2 Standard ADC/DSP Interface . . . . . . . . . . . ... Original
datasheet

38 pages,
149.85 Kb

TPS7101 TMS320C50 TMS320C203 TLV1548 TLV1544 texas TMS320C5X PROCESSOR data sheet architecture of TMS320C50 dsp bus clock interface aynchronous TLV1544 abstract
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Abstract: DD-00429 DD-00429 device provides a complete and flexible interface to a microprocessor and an ARINC 429 data bus , MN-00429-001 MN-00429-001 DD-00429 DD-00429 / DD-42900 DD-42900 Microprocessor Interface Device User's Manual The information , .7 ARINC 429 INTERFACE GROUPS , ARINC 429 RECEIVE INTERFACE , .15 ARINC 429 TRANSMIT INTERFACE ... Original
datasheet

83 pages,
2554.65 Kb

DD42900 DD00429 DD-42900 DD-00429VP MN-00429-001 DD-00429 1-800-DDC-5757 MN-00429-001 abstract
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Abstract: During a read cycle, data from the selected DSP interface mem ory register is gated onto the data bus by , During a write cycle, data from the data bus is copied into the selected DSP interface memory reg ister , Interconnect. 2-1 Figure 2-2. Microprocessor Bus Interface Waveforms , . 2-7 Figure 3-1. DSP Interface Memory Map , . 2-3 Table 2-5. Microprocessor Bus Interface Timing ... OCR Scan
datasheet

83 pages,
3884.76 Kb

Zener Diode oz RC9696/14 RC1496/14 RC9696/14 abstract
datasheet frame
Abstract: receive (ADTR) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A , access. This bit is stored in the host port interface control (HPIC) register. 14 DSP Glossary , clock division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 TMS320 DSP Product Family Glossary 1998 Digital Signal Processing Solutions Printed ... Original
datasheet

125 pages,
344.42 Kb

deutsch rectangular connector C209 RCA VGA CONNECTOR sage phase shifter stereo jack female pcb TGC4000 TMS320 TMS320C209 TMS320C24X 4 bit barrel shift register datasheet INSTRUCTION SET of TMS320C4X PLU processor DEUTSCH connectors DBA TMS320 abstract
datasheet frame
Abstract: ) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A C data type, such , access. This bit is stored in the host port interface control (HPIC) register. 14 DSP Glossary , clock division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 TMS320 DSP Product Family Glossary 1998 Digital Signal Processing Solutions Printed in ... Original
datasheet

126 pages,
395.9 Kb

vga to pal video convertor ic c language pulse interval encoding C209 cvbs video digitizer DEUTSCH DBA INSTRUCTION SET of TMS320C4X TMS320C2XX C Language Tools TGC4000 TMS320C24X TMS320 TMS320C209 dsp processor Architecture of TMS320C5X TMS320 abstract
datasheet frame
Abstract: receive (ADTR) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A , access. This bit is stored in the host port interface control (HPIC) register. 14 DSP Glossary , clock division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 TMS320 DSP Product Family Glossary Literature Number: SPRU258A SPRU258A February 1998 Printed on ... Original
datasheet

122 pages,
329.36 Kb

C209 DBA 79 Deutsch TGC4000 TMS320 TMS320C209 TMS320C24X TMS320C2XX vga to rca video chip converter TMS320C62xx cpu DEUTSCH connectors DBA SPRU258A TMS320 abstract
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Abstract: Interface to A/D and D/A - Serial I/O - Parallel I/O Fig u re 1. O verview o f th e pPD77810 DSP , P B 0 -P B 7 INT - Clock Out Reset Interrupt * - - Send Data Interface Control PE LL Û. , rising edge of the ADCK serial clock, converted to parallel data by SI, and output DSP Instructions , Functional Area DSP interface fiPD77810 Address FF60H FF60H (16-bits) FF61H FF61H FF62H FF62H (8 -bits) FF63H FF63H FF90H FF90H (8 , processor comprises a ftPD77C25 digital signal proces sor (DSP) and ftCOM78K/l general purpose processor ... OCR Scan
datasheet

62 pages,
3417.17 Kb

MPD77810 PD77810 78K/I MPD77810 abstract
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Abstract: 'HYLFH +LJKOLJKWV $GYDQFHG &ORFN 1HWZRUN Multiple dedicated Low Skew Clock )OH[LEOH 3URJUDPPDEOH , networks Quadrant-based segmentable clock networks User Programmable Phase Locked Loops (PEHGGHG &RPSXWDWLRQDO 8QLWV (&8V Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate , 64 155 MHz 280 MHz Clock-to-Out 4.5 ns 2.5 ns System clock 200 MHz 400 MHz , be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read ... Original
datasheet

49 pages,
439.59 Kb

QL8325 QL8250 QL8150 QL8050 QL8025 eclipse datasheet abstract
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