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TMS380BIU-XTPQ Texas Instruments BUS Interface Unit 100-BQFP visit Texas Instruments
TUSB2043VFR Texas Instruments 4-Port USB Hub W/Optional Serial EEPROM Interface (Input Clock: 48 MHz Oscillator/Clock Source) 32-LQFP visit Texas Instruments
CP3SP33SMSX/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 224-NFBGA -40 to 85 visit Texas Instruments
CP3SP33SMR/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 144-NFBGA -40 to 85 visit Texas Instruments
CP3SP33SMRX/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 144-NFBGA -40 to 85 visit Texas Instruments
CP3SP33SMS/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 224-NFBGA -40 to 85 visit Texas Instruments

dsp bus clock interface aynchronous

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bf532

Abstract: ADSP21365 derivatives) features an External Bus Interface Unit (EBIU) which provides interface to the external memory devices. The EBIU supports interface for the synchronous and asynchronous memory banks. The data bus on the ADSP-BF533 EBIU is 16 bits wide. This EE-Note discusses a hardware interface scheme between the ADSP-21365 PDAP port and the EBIU interface on an ADSP-BF532 processor. Since the EBIU is 16 bits , Signals to the Blackfin The External Bus Interface Unit (EBIU) on Blackfin processors
Analog Devices
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EE-254 ADSP21365 ADSP-BF531 bf532 PIN05

TLV1544

Abstract: schematic diagram inverter delta free . . . . . . . . . . . . . . . . . 7 7 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode , clock is 2.89 MHz. The DSP serial interface port standard configuration provides a 10-MHz clock that , -ns after the rising edge of EOC before the next falling edge of CS. Figure 7. DSP Interface Timing (16-Clock , . . . . . . . . . . . . . . . . . . . . . . . 2 2 Standard ADC/DSP Interface . . . . . . . . . . . , -bit fixed-point digital signal processor (DSP). The report describes the interface hardware and shows a
Texas Instruments
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TLV1544 TMS320C203 schematic diagram inverter delta free dsp processor Architecture of TMS320C5X TLV1548 TMS320C50 SLAA028A TMS320C2

dsp bus clock interface aynchronous

Abstract: TLV1544 . . . . . . . . . . . . . . . . . 7 7 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode , clock is 2.89 MHz. The DSP serial interface port standard configuration provides a 10-MHz clock that , -ns after the rising edge of EOC before the next falling edge of CS. Figure 7. DSP Interface Timing (16-Clock , . . . . . . . . . . . . . . . . . . . . . . . 2 2 Standard ADC/DSP Interface . . . . . . . . . . . , -bit fixed-point digital signal processor (DSP). The report describes the interface hardware and shows a
Texas Instruments
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dsp bus clock interface aynchronous TPS7101 architecture of TMS320C50 instruction set of TMS320C50 DSP PROCESSOR texas TMS320C5X PROCESSOR data sheet

Zener Diode oz

Abstract: 3E29 interface mem ory register is gated onto the data bus by means of three-state drivers in each DSP. These , copied into the selected DSP interface memory reg ister, with high and low bus levels representing one , . 2-1 Figure 2-2. Microprocessor Bus Interface Waveforms , . 2-7 Figure 3-1. DSP Interface Memory Map , . 2-3 Table 2-5. Microprocessor Bus Interface Timing
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Zener Diode oz 3E29 RC1493 rockwell EQM RC9696/14 RC1496/14 49-S9 CA92660-3095 TW31HY

DEUTSCH connectors DBA

Abstract: TMS320C62xx cpu receive (ADTR) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A , stored in the host port interface control (HPIC) register. 14 DSP Glossary C C: A high-level , division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit: See clock , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 DSP Product Family Glossary Literature Number: SPRU258A February 1998 Printed on
Texas Instruments
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DEUTSCH connectors DBA TMS320C62xx cpu TMS320C24X C209 TGC4000 TMS320C209 TMS320C30 TMS320C62

DEUTSCH connectors DBA

Abstract: RCA VGA CONNECTOR ) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A C data type, such , stored in the host port interface control (HPIC) register. 14 DSP Glossary C C: A high-level , division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit: See clock , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 DSP Product Family Glossary 1998 Digital Signal Processing Solutions Printed in
Texas Instruments
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RCA VGA CONNECTOR how to wire vga to rca jacks TMS320C27 direct memory access controller in TMS320C54X future scope of 32 bit barrel shifter apl 117

PD7720

Abstract: Interface to A/D and D/A - Serial I/O - Parallel I/O Fig u re 1. O verview o f th e pPD77810 DSP , P B 0 -P B 7 INT - Clock Out Reset Interrupt * - - Send Data Interface Control PE LL Û , clock, converted to parallel data by SI, and output DSP Instructions All DSP instructions consist of , Functional Area DSP interface fiPD77810 Address FF60H (16-bits) FF61H FF62H (8 -bits) FF63H FF90H (8 , processor comprises a ftPD77C25 digital signal proces sor (DSP) and ftCOM78K/l general purpose processor
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PD7720 PD77810 PD77C25 COM78K/ 78K/I M-PD77810

DEUTSCH connectors DBA

Abstract: 7 segment latch decoder for hexa decimal numbers receive (ADTR) register. AFB: See auxiliary register file bus. 2 DSP Glossary aggregate type: A , stored in the host port interface control (HPIC) register. 14 DSP Glossary C C: A high-level , division factor (CLKDV) bits. CLKIN: See input clock signal. 18 DSP Glossary CLKMOD bit: See clock , the current character position on the command line. 20 DSP Glossary command-line interface: A , TMS320 DSP Product Family Glossary 1998 Digital Signal Processing Solutions Printed
Texas Instruments
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7 segment latch decoder for hexa decimal numbers VGA Video output to RGB - RCA Plugs - Original Circuit Design 4 bit barrel shift register datasheet ABSTRACT FOR REMOTE OPERATED MASTER SWITCH IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER INSTRUCTION SET of TMS320C4X

DD00429

Abstract: TXDB12 -00429 device provides a complete and flexible interface to a microprocessor and an ARINC 429 data bus , MN-00429-001 DD-00429 / DD-42900 Microprocessor Interface Device User's Manual The information , .7 ARINC 429 INTERFACE GROUPS , .8 ARINC 429 RECEIVE INTERFACE , .15 ARINC 429 TRANSMIT INTERFACE
Data Device
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DD00429 TXDB12 DD-00429VP DD42900 1-800-DDC-5757

QL8025

Abstract: QL8050 'HYLFH +LJKOLJKWV $GYDQFHG &ORFN 1HWZRUN Multiple dedicated Low Skew Clock )OH[LEOH 3URJUDPPDEOH , networks Quadrant-based segmentable clock networks User Programmable Phase Locked Loops (PEHGGHG &RPSXWDWLRQDO 8QLWV (&8V Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate , 64 155 MHz 280 MHz Clock-to-Out 4.5 ns 2.5 ns System clock 200 MHz 400 MHz , be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read
QuickLogic
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QL8025 QL8050 QL8150 QL8250 QL8325 eclipse LVCMOS18