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dram 512mb

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Abstract: technology from Spansion. The 512Mb NOR, 512Mb DDR DRAM and 512Mb MirrorBit® ORNANDTM memory solution is , without having to increase their size and weight. NOR + pSRAM 64Mb 512Mb ­ ­ ­ ­ 16Mb 128Mb NOR +DRAM 512Mb 512Mb 512Mb 512Mb 256Mb 1Gb ­ ­ ­ ­ ­ ­ 1Gb 1Gb 768Mb , DRAM + ORNAND 512Mb 512Mb 512Mb 1Gb 512Mb 512Mb ­ ­ 15x15mm Now 15x15mm Now ­ , ARCHITECTURE NOR FLASH MIRRORBIT® ORNAND TM FLASH DRAM pSRAM Spansion's Package-on-Package ... Freescale Semiconductor
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2 pages,
146.44 Kb

FLASH NOR 64mb PSRAM mobile hardware integration ARM1136JF-S 512MB NOR FLASH Spansion NAND Flash 200-ball 152-Ball PoP 152-Ball MX31L TEXT
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Abstract: Rate Peak Throughput 512Mb DDR2 512MB DRAM Speed Grade 1Gb DDR2 2GB Module Speed , FB-DIMM4.8Gbps 18DIMM 18DIMM FB-DIMM JEDECDDR2 SDRAM Memory Controller DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM AMB AMB AMB DRAM DRAM DRAM DRAM DRAM DRAM DRAM 8 DIMM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM ... Elpida Memory
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datasheet

2 pages,
282.61 Kb

DRAM elpida 72 pin dimm ELPIDA DDR2 elpida ddr2 dram J0632E80 pc2-5300 dram DDR2 memory organization ddr2 D-RAM 512MB PC2-5300F TEXT
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Abstract: REV 1.4 Oct. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Pin Configuration ­ 400 mil , Oct. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Block Diagram (64Mb x 8) 6 REV 1.4 Oct. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR , configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve ... Nanya Technology
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datasheet

70 pages,
2238.56 Kb

NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: containing 536,870,912 bits. It is internally configured as a qual-bank DRAM. The 512Mb chip is organized as , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Ordering Information , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Input / Output Functional , Jan. 2012 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Block Diagram (64Mb x 8) 6 REV 1.6 Jan. 2012 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR ... Nanya Technology
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datasheet

70 pages,
2203.72 Kb

NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: 0.3 Jan. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Preliminary , ,870,912 bits. It is internally configured as a qual-bank DRAM. The 512Mb chip is organized as 16Mbit x , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Preliminary Edition Ordering , 3-3-3 3 REV 0.3 Jan. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , 4 REV 0.3 Jan. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM ... Nanya Technology
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datasheet

72 pages,
2247.91 Kb

NT5DS32M16 NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Description Nanya 512Mb SDRAMs , as a qual-bank DRAM. The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 , 3-3-3 2.5-3-3 3-3-3 3 REV 1.1 Jul. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb , A0-A9 4 REV 1.1 Jul. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Block Diagram (32Mb x 16 ... Nanya Technology
Original
datasheet

71 pages,
2248.41 Kb

NT5DS32M16 NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: REV 1.7 May. 2012 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Pin Configuration ­ 400 mil , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Input / Output Functional , May. 2012 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Block Diagram (64Mb x 8) 6 REV 1.7 May. 2012 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR ... Nanya Technology
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datasheet

70 pages,
2206.16 Kb

NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: http://www.deutron.com.tw 512Mb DDRII Synchronous DRAM P3R12E2GEU/F P3R12E2GEU/F P3R12E3GEU/F P3R12E3GEU/F Description , . Oct,2005 - 3 - Rev.1.0 512Mb DDRII Synchronous DRAM P3R12E2GEU/F P3R12E2GEU/F P3R12E3GEU/F P3R12E3GEU/F CONTENTS , . 65 Oct,2005 - 4 - Rev.1.0 512Mb DDRII Synchronous DRAM P3R12E2GEU/F P3R12E2GEU/F P3R12E3GEU/F P3R12E3GEU/F , and VDDL tied together. Oct,2005 - 6 - Rev.1.0 512Mb DDRII Synchronous DRAM P3R12E2GEU/F P3R12E2GEU/F , Conditions. Oct,2005 - 8 - Rev.1.0 512Mb DDRII Synchronous DRAM P3R12E2GEU/F P3R12E2GEU/F P3R12E3GEU/F P3R12E3GEU/F AC ... Deutron Electronics
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datasheet

68 pages,
614.66 Kb

P3R12E2GEU/F P3R12E3GEU/F TEXT
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Abstract: CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Description Nanya 512Mb SDRAMs , as a qual-bank DRAM. The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 , 3-3-3 2.5-3-3 3-3-3 3 REV 1.0 Jul. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb , A0-A9 4 REV 1.0 Jul. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Block Diagram (32Mb x 16 ... Nanya Technology
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datasheet

71 pages,
2247.72 Kb

NT5DS64M8DS NT5DS32M16DS TEXT
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Abstract: DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Description Nanya 512Mb SDRAMs is a , qual-bank DRAM. The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device , 3-3-3 3 REV 1.5 Oct. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM , CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM Input / Output Functional , REV 1.5 Oct. 2011 CONSUMER DRAM NT5DS64M8DS NT5DS64M8DS NT5DS32M16DS NT5DS32M16DS 512Mb DDR SDRAM ... Nanya Technology
Original
datasheet

70 pages,
2237.43 Kb

nt5ds64m8 NT5DS64M8DS NT5DS32M16DS TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
memory size is 512MB with SDRAM and 1GB with EDO DRAM. Memory type, size and speed can vary between (DIMM) sockets which support both SDRAM and EDO DRAM DIMMs. Minimum memory size is 16MB. Maximum memory size is 512MB with SDRAM and 1GB with EDO DRAM. Note: The processor will cache up to the The DK440LX DK440LX supports both SDRAM and EDO DRAM DIMMs. The BIOS will automatically detect the memory type four dual in-line memory module (DIMM) sockets which support both SDRAM and EDO DRAM DIMMs. Memory can
/datasheets/files/intel/design/motherbd/dk/dk_inst-v2.htm
Intel 13/02/1998 33.81 Kb HTM dk_inst-v2.htm
FIFO - Accepts csche line writes at zero wait-states. Page mode and EDO DRAM controller - 512MB address space - Programmable timing - 32 or 64 bit DRAM banks (interleaving supported for 64bit wide DRAM arrays system peripherials needed to build a high performance 64-bit MIPs system: DRAM controller
/datasheets/files/scantec/galileo/www/tbriefs/64014tb.htm
Scantec 20/04/1998 5.26 Kb HTM 64014tb.htm
Semiconductor PBC family of I2O-ready PCI interface chips   V3 Semiconductor V96BMC V96BMC DRAM/system Semiconductor V96BMC V96BMC DRAM/system controller helps speed your i960 processor-based design to market The system design in a single, low-power, low-cost package. It provides control for up to 512MB interleaved, zero waitstate fast page or EDO DRAM at up to 40MHz bus speed. In addition, a bus watch timer and 2-24 bit timers are provided. The flexible DRAM controller provides page caching, support for
/datasheets/files/intel/design/i960/t_party-v1.htm
Intel 05/05/1998 13.19 Kb HTM t_party-v1.htm
Semiconductor PBC family of I2O-ready PCI interface chips   V3 Semiconductor V96BMC V96BMC DRAM/system Semiconductor V96BMC V96BMC DRAM/system controller helps speed your i960 processor-based design to market The system design in a single, low-power, low-cost package. It provides control for up to 512MB interleaved, zero waitstate fast page or EDO DRAM at up to 40MHz bus speed. In addition, a bus watch timer and 2-24 bit timers are provided. The flexible DRAM controller provides page caching, support for
/datasheets/files/intel/design/i960/t_party-v3.htm
Intel 31/07/1998 12.93 Kb HTM t_party-v3.htm
) System Controller Interface Chips V96BMC V96BMC DRAM/system controller helps speed your i960 embedded system design in a single, low-power, low-cost package. It provides control for up to 512MB interleaved, zero waitstate fast page or EDO DRAM at up to 40MHz bus speed. In addition, a bus watch timer and 2-24 bit timers are provided. The flexible DRAM controller provides page caching, support for non-symmetric arrays, 3.3V DRAM interface, high-drive DRAM controls for large arrays and up
/datasheets/files/intel/design/i960/t_party-v5.htm
Intel 15/11/1998 21.19 Kb HTM t_party-v5.htm
DRAM (for up to 512MB of system DRAM), and integrates the memory address buffers. Integrated advanced synchronous DRAM (SDRAM) enable a breakthrough in performance. An option for Shared Memory Buffer
/datasheets/files/intel/setup/index.htm
Intel 06/07/1996 4.86 Kb HTM index.htm
system: DRAM controller, device controller, DMA engines, timer/counters, and a high-performance wide 16 level deep DRAM controller Page mode and EDO DRAMs 512MB address space 256KB 256KB - 16MB device depth 1- 4 banks supported directly DRAM and devices Three 24-bit and one 32-bit timers/couters Distributed
/datasheets/files/scantec/galileo/www/tbriefs/64111tb.htm
Scantec 20/04/1998 8.07 Kb HTM 64111tb.htm
) System Controller Interface Chips V96BMC V96BMC DRAM/system controller helps speed your i960 embedded system design in a single, low-power, low-cost package. It provides control for up to 512MB interleaved, zero wait state fast page or EDO DRAM at up to 40MHz bus speed. In addition, a bus watch timer and 2-24 bit timers are provided. The flexible DRAM controller provides page caching, support for non-symmetric arrays, 3.3V DRAM interface, high-drive DRAM controls for large arrays and up
/datasheets/files/intel/products one/design/i960/t_party.htm
Intel 01/05/1999 20.88 Kb HTM t_party.htm
Yes No Yes Yes Yes, up to 4-way DRAM Refresh CAS-before-RAS Max Memory Size 1 GB 256 MB 1 GB EDO 512MB SDRAM 2 GB 8 GB Memory Types SDRAM EDO/SDRAM EDO/SDRAM SDRAM EDO/DRAM Memory Interleave No No No
/datasheets/files/intel/design/pcisets/linecard-v3.htm
Intel 06/08/1998 20.21 Kb HTM linecard-v3.htm
Yes, up to 4-way Yes Yes No No No Yes No DRAM Refresh 8 GB 2 GB 1 GB 256 MB 256 MB 256 MB 1 GB EDO 512MB SDRAM 256 MB Memory Types EDO/DRAM SDRAM SDRAM SDRAM SDRAM SDRAM EDO/SDRAM Memory
/datasheets/files/intel/products one/design/chipsets/linecard.htm
Intel 30/04/1999 32.05 Kb HTM linecard.htm