NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: applications One conversion per clock cycle-throughput Low latency: 6 clock cycles VHDL source code and , Design Document Design File Formats VHDL source code, EDIF netlist Constraints File rgb2yrb.ucf Verification Testbench, test vectors Instantiation VHDL, Verilog Templates Reference designs & None , digital RGB source Table 1: Core Implementation Data Supported Device Clock Family Tested CLBs , · · · · Available under terms of the SignOnce IP License Converts digital RGB to digital ... | Original |
3 pages, |
image processing verilog code rgb to component converter ic digital clock vhdl code xilinx vhdl code for digital clock vhdl code for digital clock datasheet abstract |
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| Abstract: · · · · · Available under terms of the SignOnce IP License Converts digital component video (YCrCb) to digital RGB Optimized for specific Xilinx architectures High-speed operation for HDTV applications One conversion per clock cycle-throughput Low latency: 6 clock cycles All outputs properly limited - No external logic needed to handle these conditions VHDL source code and testbench included , Design File Formats VHDL source code, EDIF netlist Constraints File yrb2rgb.ucf Verification ... | Original |
3 pages, |
xilinx vhdl code for digital clock V100E-8 ycrcb rgb vhdl vhdl code for digital clock datasheet abstract |
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| Abstract: VHDL Static Timing Analyzer reports the longest paths, the maximum clock frequency, and checks for , VHDL Based Design Methodology 4401035 NC VHDL Based Design Methodology Some customers are , languages (HDLs) have revolutionized the way digital systems are designed. This revolution has been , have seen Verilog and VHDL go from being used for less than 5% of new designs to nearly 100% of all , they expand their libraries of reusable code modules. Language Selection Clearly, HDLs are ... | Original |
4 pages, |
new ieee programs in vhdl and verilog vhdl code for digital clock digital clock vhdl code verilog code for digital calculator datasheet abstract |
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| Abstract: ) the digital LTC bitstream. See the application note. 1 Longitudinal Time Code Generator , Digital LTC output LTC interrupt output LTC underrun status Verification Methods VHDL functional and , Longitudinal Time Code Generator September 25, 2000 Product Specification AllianceCORETM , under terms of the SignOnce IP License SMPTE/EBU Longitudinal Time Code time code generator Lock on external (video) reference PAL/NTSC support 27 Mhz clock input for internal timing Five 16-bit double ... | Original |
4 pages, |
16 bit register vhdl B4430 Biphase mark code ltc generator vhdl code for 6 bit parity generator vhdl code for 8 bit register vhdl code for digital clock vhdl code for a 9 bit parity generator binary code generator digital clock vhdl code biphase mark encoder biphase mark vhdl datasheet abstract |
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| Abstract: trademarks of their respective owners. Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic , data are fed every clock cycle. The first result appears after 5 clock periods latency and next results are available each clock cycle. Full IEEE754 IEEE754 precision and accuracy were included. , Full accuracy and precision Results available at every clock Overflow, underflow and ... | Original |
3 pages, |
APEX20K APEX20KC APEX20KE digital clock vhdl code FLEX10KE IEEE754 verilog code for floating point unit vhdl code for floating point adder vhdl code of pipelined adder verilog code for floating point adder vhdl code of floating point adder IEEE-754 IEEE-754 abstract |
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| Abstract: precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Simple interface Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment , are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 IEEE-754 precision and accuracy are included. ... | Original |
3 pages, |
vhdl code of floating point unit APEX20KC APEX20KE ARITHMETIC COPROCESSOR FLEX10KE floating point verilog IEEE-754 IEEE754 APEX20K verilog code for floating point unit verilog code divide vhdl code for Clock divider for FPGA IEEE754 abstract |
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| Abstract: Results available at every clock Fully configurable No programming required Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist , unlimited. There is no time of use limitations. Single Design license for VHDL, Verilog source code , levels. Input data are fed every clock cycle. The first result appears after 9 clock periods latency and next results are available each clock cycle. Precision and accuracy are parameterized. Fully ... | Original |
3 pages, |
FLEX10KE APEX20KE APEX20KC APEX20K IEEE-754 IEEE-754 abstract |
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| Abstract: Fully synthesizable, static synchronous design with no internal tri-states Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & , Single Design license for VHDL, Verilog source code called HDL BLOCK DIAGRAM Upgrade from , Convert operation is pipelined to 2 levels. Input data are fed every clock cycle. The first result appears after latency equal to 2 clock periods and next results are available each clock cycle. Full ... | Original |
3 pages, |
ieee floating point verilog FLEX10KE APEX20KE APEX20KC APEX20K ieee floating point vhdl vhdl code of floating point unit IEEE-754 IEEE-754 abstract |
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| Abstract: trademarks of their respective owners. Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic , are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 IEEE-754 precision and accuracy are included. , Full accuracy and precision Results available at every clock Overflow, underflow and ... | Original |
3 pages, |
vhdl code of floating point unit IEEE754 ieee floating point vhdl ieee floating point verilog k 2996 IEEE-754 IEEE754 abstract |
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| Abstract: : VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & , 12 months. Single Design license for VHDL, Verilog source code called HDL Source , operation is pipelined to 2 levels. Input data are fed every clock cycle. The first result appears after latency equal to 2 clock periods and next results are available each clock cycle. Full precision and , precision Results available at every clock Overflow, underflow and invalid operation flags ... | Original |
3 pages, |
floating point verilog vhdl code of floating point unit digital clock vhdl code verilog code for floating point unit IEEE-754 IEEE-754 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| = Date: March, 2001 VHDL code examples are provided to illustrate Chapter 2 "Design Considerations" of the Virtex-II Platform FPGA Handbook. - VHDL Templates: VHDL templates are available as examples level VHDL code instantiating some primitives. These submodules can be instantiated in a design and Book) Directories: - - clock: "Using Global Clock Networks" - dcm: "Using the Digital Clock Manager section. Each part of the template should be inserted within the VHDL design file. The portmap of the www.datasheetarchive.com/download/74866175-996099ZC/xc2v_vhdl.zip (readme_vhdl.txt) |
Xilinx | 08/08/2003 | 95.41 Kb | ZIP | xc2v_vhdl.zip |
| README file: Virtex-II Pro Platform FPGA Handbook = Date: March, 2002 VHDL code examples are provided to illustrate Chapter 2 "Design Considerations" of the Virtex-II Pro Platform FPGA Handbook. - VHDL Templates: VHDL templates are available as examples to instantiate primitives. - VHDL Submodules: VHDL submodules are low level VHDL code Book) Directories: - - clock: "Using Global Clock Networks" - dcm: "Using the Digital Clock Manager www.datasheetarchive.com/download/96620404-996101ZC/xc2vp_vhdl.zip (readme_vhdl.txt) |
Xilinx | 15/08/2003 | 90.84 Kb | ZIP | xc2vp_vhdl.zip |
| = Date: March, 2001 VHDL code examples are provided to illustrate Chapter 2 "Design Considerations" of the Virtex-II Platform FPGA Handbook. - VHDL Templates: VHDL templates are available as examples level VHDL code instantiating some primitives. These submodules can be instantiated in a design and Book) Directory: - - dcm: "Using the Digital Clock Manager" Templates (primitive): DCM_INST Submodules (code example): - Clock de-skew BUFG_CLK0_SUBM BUFG_CLK2X_SUBM BUFG_CLK0_FB_SUBM BUFG www.datasheetarchive.com/download/74866175-996099ZC/xc2v_vhdl.zip (readme_dcm_vhdl.txt) |
Xilinx | 08/08/2003 | 95.41 Kb | ZIP | xc2v_vhdl.zip |
| Abstract for Testbenches (VHDL) v2.1i Banner -> Testbenchs v2.1i (VHDL) Software & Version: N/A Audience New to first year VHDL users, anyone interested in applying VHDL to the design process. Prerequisites Basic digital design, simulation and - Intermediate Training Duration 1 Hour Content Description This 'VHDL www.datasheetarchive.com/files/xilinx/docs/rp00022/rp022fb.htm |
Xilinx | 29/02/2000 | 5.04 Kb | HTM | rp022fb.htm |
| Speed Clocking Architecture using the local routing clock macro inserted between a digital clock PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE . ################################################################################### # Example local clock macro design use model. # Note: user must change netnames below to match design usage. # Insert local route clock macro between a given DCM and BUFGMUX www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (readme.txt) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| Speed Clocking Architecture using the local routing clock macro inserted between a digital clock PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE . ################################################################################### # Example local clock macro design use model. # Note: user must change netnames below to match design usage. # Insert local route clock macro between a given DCM and BUFGMUX www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (readme.txt) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| Speed Clocking Architecture using the local routing clock macro inserted between a digital clock PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE . ################################################################################### # Example local clock macro design use model. # Note: user must change netnames below to match design usage. # Insert local route clock macro between a given DCM and BUFGMUX www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (readme.txt) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| Speed Clocking Architecture using the local routing clock macro inserted between a digital clock PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\" SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE . ################################################################################### # Example local clock macro design use model. # Note: user must change netnames below to match design usage. # Insert local route clock macro between a given DCM and BUFGMUX www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (readme.txt) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| clock by the analog-to-digital convertor This design provides the capability of using auto phase - Disclaimer - Objective - Simple Design Interface functioning - VHDL instantiation model - Design = Objective Provide a simple Real time pass trough data interface for the Texas Instruments Analog-to-digital convertor family ADS527x. Simple Design Interface Functioning The analog-to-digital convertor provides the FPGA with a fast running clock, a slow running clock, used as frame (Sync) signal and 8 www.datasheetarchive.com/download/4786027-996049ZC/xapp774.zip (Ads5273IntV2Simple_Readme.txt) |
Xilinx | 23/07/2004 | 1079.49 Kb | ZIP | xapp774.zip |
| transmission. RS codes are specified in many data transmission standards, e.g. the ATSC digital TV standard. RS codes provide extremely good error correction. It is one of the most effective forms of coding for maths behind RS codes was developed by Irving Reed and Gus Solomon back in 1959, hence the name. In received. Examples include cellphones, digital TV broadcast, space communications and CD players. In . RS is a block-code, i.e. data is processed a block at a time. Each block contains n words (or symbols www.datasheetarchive.com/files/xilinx/docs/rp0000a/rp00a91.htm |
Xilinx | 29/02/2000 | 16.17 Kb | HTM | rp00a91.htm |