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ARF29-6921G Texas Instruments 500 mW OEM TRX with Rx clock recovery function visit Texas Instruments
ARF29-6921H Texas Instruments 500 mW OEM TRX with Rx clock recovery function visit Texas Instruments
ONET1131ECRSMR Texas Instruments Externally Modulated Laser Driver With Integrated Clock and Data Recovery (CDR) 32-VQFN -40 to 100 visit Texas Instruments Buy
ONET1131ECRSMT Texas Instruments Externally Modulated Laser Driver With Integrated Clock and Data Recovery (CDR) 32-VQFN -40 to 100 visit Texas Instruments
XTNETA1622DW Texas Instruments 622.08-MHz Clock-Recovery Device 20-SOIC -40 to 85 visit Texas Instruments
TLC1543CFN Texas Instruments 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-PLCC visit Texas Instruments Buy

digital clock and carrier recovery

Catalog Datasheet MFG & Type PDF Document Tags

digital clock and carrier recovery

Abstract: satellite phone system /D converters · Dual square-root Nyquist matched filters (=0.2-0.35) · All digital clock and carrier recovery · Integrated PLLs · An integrated solution enabling low complexity/low DVB/DIRECTV , digital transmission solution for DVB, DSS and Digicipher II systems digital satellite reception , phase/frequency recovery block, variable rate digital filters, square-root Nyquist matched filters , , the DIRECTV digital transmission standard and Digicipher II ITU-R 217/11 digital transmission
Broadcom
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Abstract: PC applications · · · · · · · I2C bus microprocessor interface All digital clock and carrier recovery , GQ1N · · · · Up to ± 15 MHz LNB frequency tracking Fully digital timing and phase recovery loops , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , specification for DVB-S and DirecTV specification for DSS On-chip digital filtering supports 1 to 45 MBaud , recovery DVB DSS FEC MPEG/ DSS Packets Analog AGC control Clock Generation Acquisition Zarlink Semiconductor
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digital clock and carrier recovery

Abstract: DS5155 Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering
Zarlink Semiconductor
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digital clock and carrier recovery

Abstract: VP310/CG/GQ1N microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 , · · · Up to ± 15 MHz LNB frequency tracking Fully digital timing and phase recovery loops , Preliminary Information The VP310 is a QPSK/BPSK 1 to 45 MBaud demodulator and channel decoder for digital , Trace back depth 128 · Extensive SNR and BER monitors Timing recovery Matched filter Phase , convenience only. For more information on Zarlink's obsolete products and replacement product lists, please
Zarlink Semiconductor
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DS5155 digital clock and carrier recovery VP310/CG/GQ1N zarlink VP310 philips master replacement guide directv descrambler

Digicipher

Abstract: jtag block diagram dvb All digital clock and carrier recovery · Integrated PLLs cost digital satellite IRDs · Variable , A universal digital transmission solution for DVB, receiver for DIRECTV , DVB and DigicipherTM II digital satellite reception · RECEIVER DSS and Digicipher II systems · An integrated solution , Acquisition/Tracking Loops and Clock Generation JTAG Interface LNB_CTRL The BCM4201 Universal Satellite , , dual 8-bit A/D converters, a phase/frequency recovery block, variable rate digital filters
Broadcom
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Digicipher jtag block diagram dvb direcTV viterbi oqpsk receiver block diagram satellite transponder satellite phone system PB01-R-05

DS5155

Abstract: VP310 Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering
Zarlink Semiconductor
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digital clock and carrier recovery

Abstract: Digicipher · Dual square-root Nyquist matched filters (a=0.2-0.35) · All digital clock and carrier recovery · , QPSK ® SUMMARY OF BENEFITS · A universal digital transmission solution for DVB, DSS, and DigiCipher , S_SYNC P_DATA[7:0] Deinterleaver RAM AGC_CTRL Acquisition/Tracking Loops and Clock Generation JTAG , converters, a phase/ frequency recovery block, variable rate digital filters, square-root Nyquist matched , digital transmission standard, and DigiCipher II ITU-R 217/11 digital transmission standard. Analog
Broadcom
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BCM3440 block diagram of integrated satellite system Viterbi Decoder Broadcom RECEIVER block diagram of receiver synchronization transport demux viterbi 4201-PB04-R

digital clock and carrier recovery

Abstract: DS5155 Q I/P Analog AGC control · · · · I2C bus microprocessor interface All digital clock and carrier recovery On-chip PLL clock generation using low cost 10 to 15 MHz crystal 3.3V , Fully digital timing and phase recovery loops High level software interface for minimum development , MBaud demodulator and channel decoder for digital satellite television transmissions to the European , Conforms to EBU specification for DVB-S and DirecTV specification for DSS On-chip digital filtering
Zarlink Semiconductor
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BPSK demodulator lnb analog tv
Abstract: -bit A/D converters â'¢ Dual square-root Nyquist matched filters (a=0.2-0.35) â'¢ All digital clock and carrier recovery â'¢ Integrated PLLs DVB/DIRECTV/Digicipher II-compliant FEC decoder â'¢ 64 , , DSS and Digicipher II systems â'¢ An integrated solution enabling low complexity/low cost digital , Acquisition/Tracking Loops and Clock Generation AGC_CTRL JTAG Interface LNB_CTRL The BCM4201 , /OQPSK receiver, dual 8-bit A/D converters, a phase/frequency recovery block, variable rate digital Broadcom
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PB03-R-06

BCM4200

Abstract: digital clock and carrier recovery square-root Nyquist matched filters (GC=0.2-0.35) · All digital clock and carrier recovery · Integrated PLLs , solution enabling low complexity/low cost digital satellite IRDs * Variable data rates support ail satellite systems worldwide * Integrated A/D converters reduce system manufacturing costs and complexities * A universal digital transmission solution for DVB and DSS systems * Demodulation up to 45 MBaud for , CTRL Acquisition/Tracking Loops and Clock (Generation JTAG Interface LNB Control Deinterleaver
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BCM4200 BRDCS001 1PB2/97

PHILIPS television tuner schematic

Abstract: digital clock and carrier recovery tuner · · All digital clock and carrier recovery Reed Solomon · On-chip PLL clock , 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to , compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , recovery Matched filter Phase recovery Acquisition Control Clock Generation DVB DSS FEC 2
Zarlink Semiconductor
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ZL10312 ZL10312QCG ZL10312UBH PHILIPS television tuner schematic service manual of philips PC satellite receiver schematic diagram receiver satellite

diseqc

Abstract: ZL10312 tuner · · All digital clock and carrier recovery Reed Solomon · On-chip PLL clock , 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to , compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , Description The ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite
Zarlink Semiconductor
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diseqc viterbi algorithm ZL10312QCG64-

directv descrambler

Abstract: viterbi algorithm clock and carrier recovery On-chip PLL clock generation using low cost 10 to 16 MHz crystal Low power , phase recovery are all digital and the only feed-back to the analogue front-end is for automatic gain , compensation, frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and , ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite television , channel decoder for digital satellite television transmissions compliant to both DVB-S and DSS standards
Zarlink Semiconductor
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ZL10312QCF ZL10312QCG1

ZL10312QCG

Abstract: digital clock and carrier recovery digital clock and carrier recovery Reed Solomon · On-chip PLL clock generation using low cost 10 , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue , filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous , specification for DVB-S and DirecTV specification for DSS · On-chip digital filtering supports 1 - 45 , 45 MSps demodulator and channel decoder for digital satellite television transmissions to the
Zarlink Semiconductor
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DiSEqC 1.3 lnb schematic DVB-S Demodulator digital tv schematic diagram diseqc 1.0

qam circuit

Abstract: QAM-256 The fully digital clock and carrier recovery elim inates the need to im plem ent external VCOs and , Root Raised Cosine Receive Filtering, Carrier Recovery and Digital Gain Control, Equalization (Linear , . Carrier Recovery - Fine Tuning The carrier recovery block allows the acquisition and track ing of a , Recovery Variable Symbol Rate Recovery Anti-aliasing Continuously Variable Digital Filtering with Symbol Rate Adaptive Bandwidth (1 to 18.75 Mbaud at the Same Sampling Frequency) Fully Digital Carrier
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qam circuit QAM-256 QAM16 AT76C651

digital clock and carrier recovery

Abstract: receiver qpsk schematic diagram microprocessor interface with separate interface to tuner. All digital clock and carrier recovery. On-chip PLL , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue , filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous , 2003 Conforms to EBU specification for DVB-S and DirecTV specification for DSS. On-chip digital , demodulator and channel decoder for digital satellite television transmissions to the European Broadcast
Zarlink Semiconductor
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receiver qpsk schematic diagram diseqc* LNB POWER

ZL10312

Abstract: DVB-S Demodulator digital tv schematic diagram microprocessor interface with separate interface to tuner. All digital clock and carrier recovery. On-chip PLL , anti-alias filtering for all symbol rates from 1 - 45 MS/s. Frequency, timing and carrier phase recovery are , , frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering , specification for DVB-S and DirecTV specification for DSS. On-chip digital filtering supports 1 - 45 MS/s symbol , filter Phase recovery DVB DSS FEC MPEG/ DSS Packets Analog AGC Control Clock Generation
Zarlink Semiconductor
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receiver qpsk schematic diagram

Abstract: transmitter qpsk schematic diagram interface. â'¢ All digital clock and carrier recovery. â'¢ On-chip PLL clock generation using low cost 10 , . Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analog front-end , '¢ Fully digital timing and phase recovery loops. â'¢ High level software interface for minimum , filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous , '¢ Conforms to EBU specification for DVB-S and DirecTV specification for DSS. â'¢ On-chip digital filtering
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transmitter qpsk schematic diagram Single Chip zero IF L-band Tuner DVB Satellite qpsk schematic diagram DVB-S receiver single chip qpsk transmitter FR310 MS-022 418/ED/51210/016 20FEB97 22MAY98 10SEP98 30JUN99

reed 108 R12

Abstract: diseqc Features · I²C bus microprocessor interface. · All digital clock and carrier recovery. · On-chip PLL , 45Mbaud. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the , compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation , specification for DVB-S and DirecTV specification for DSS. · On-chip digital filtering supports 1 to 45MBaud , and code rate acquisition. · Up to ± 15MHz LNB frequency tracking. · Fully digital timing and phase
Mitel Semiconductor
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reed 108 R12 1N4445 Reed Solomon encoder IC DVB-S front end receiver schematic diagram SCPC SL1720

receiver philips fr 310

Abstract: directv descrambler digital clock and carrier recovery. · On-chip PLL clock generation using low cost 10 to 15MHz crystal. · , ing and carrier phase recovery are all digital and the only feed-back to the analog front-end is for , 15MHz LNB frequency tracking. · Fully digital timing and phase recovery loops. · High level software , , decim ation filtering, carrier recovery, symbol recovery and matched filtering. The decim ation filters , to 45MBaud demodulator and channel decoder for digital satellite television transmissions to the
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receiver philips fr 310 QPSK application
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