500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
LTC3880EUJ#TRMPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature: E visit Linear Technology - Now Part of Analog Devices
LTC3880EUJ-1#TRPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3880IUJ-1#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3880EUJ-1#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3880EUJ#TRPBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3880IUJ#PBF Linear Technology LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

digital FIR Filter verilog code polyphase

Catalog Datasheet MFG & Type PDF Document Tags

verilog code for interpolation filter

Abstract: VHDL code for polyphase decimation filter using D filter 8. Multi-channel decimation direct-form FIR filter The design files include Verilog HDL code to , interpolation FIR filter structure that the Quartus II software infers from the Verilog HDL example code , code to ensure the Quartus II Fitter utilizes the appropriate DSP block features for your FIR filter , application note contain HDL code for examples of the following different FIR filter variations: 1 , Table 3. Table 2. FIR Filter Top Level Signals Verilog Signal VHDL Direction Name Width
Altera
Original

digital FIR Filter verilog code

Abstract: verilog code for interpolation filter filter, you can use the output files with MATLAB, VHDL, or Verilog HDL simulation tools. The FIR , . Download the FIR compiler function from the Internet. Generate a custom filter using the FIR compiler , coefficient quantization in the frequency domain, generates FIR filter hardware structures and performs , integrated finite impulse response (FIR) filter development environment Highly optimized for Altera® device , FIR filter is a weighted, tapped delay line (see Figure 1). The filter design process involves
Altera
Original

digital FIR Filter verilog code

Abstract: FIR filter matlaB design Data Width 1 Specifications The FIR compiler generates four polyphase filters. Each filter , . After you have created a custom FIR filter, you can use the output files with MATLAB, VHDL, or Verilog , .39 Generate a FIR Filter .39 Variable-Coefficient FIR Filter .42 Fixed-Coefficient FIR Filter
Altera
Original

verilog code for fir filter using DA

Abstract: 4 tap fir filter based on mac vhdl code .0) March 28, 2003 Product Specification Distributed Arithmetic FIR Filter v8.0 The polyphase segments , 0 Distributed Arithmetic FIR Filter v8.0 DS240 (v1.0) March 28, 2003 0 0 Features , response (FIR), half-band, Hilbert transform, interpolated filters, polyphase decimator, polyphase , · The Xilinx filter Core is a highly parameterizable, area-efficient high-performance FIR filter , ) a(N-1) y(n) Figure 1: Conventional Tapped-Delay Line FIR Filter Mechanization © 2003 Xilinx
Xilinx
Original
verilog code for fir filter using DA 4 tap fir filter based on mac vhdl code polyphase interpolator design in verilog verilog code for interpolation filter verilog code for decimation filter VHDL code for polyphase decimation filter using D ASSP-22

convolutional interleaver

Abstract: ipad polyphase FIR filters, one for I and one for Q. Each filter takes a 1-bit input stream and generates four , 0-3. These are the outputs of an M=4 polyphase FIR filter. IY2[9:0], IY3[9:0] QY0[9:0], QY1[9:0 , o Verilog Source Code · All o o User Guide Test Bench Synthesis and Simulation , MC-ACT-DVBMOD Digital Video Broadcast Modulator April 23, 2004 Datasheet v1.2 3721 , Baseband Shaping block · 204/188 Reed-Solomon Outer Coder · Selectable convolutional code rates
Memec Design
Original
convolutional interleaver ipad block interleaver in modelsim randomizer solomon Convolutional Block Interleaver time

verilog code for interpolation filter

Abstract: . The core is available as a register transfer level (RTL) code of the filter, both in Verilog and VHDL , an example of using a FIR filter. Digital samples to be filtered enter the filter input and filtered , . 30 Polyphase Interpolation Filter , . 42 Polyphase Decimation Filter , ) filter is one of the most essential building blocks in digital signal processing (DSP) systems. Digital
Microsemi
Original

VHDL code for polyphase decimation filter using D

Abstract: verilog code for decimation filter this application note reviews polyphase decimating filter architectures and discusses the fractional , .1) March 5, 2007 www.xilinx.com 2 R Polyphase Decimating Filter Architectures Polyphase , ) operation can be implemented in a polyphase architecture by breaking the N-tap low pass filter in Figure 3 , subfilters only operates at 1/Dth the input sample rate, a single FIR filter structure (that is N/D taps , inefficient decimating filter of Figure 3, the polyphase implementation cuts the computational workload (or
Xilinx
Original
XAPP936 DSP48 VHDL code for polyphase decimation filter 16 QAM modulation verilog code qpsk modulation VHDL CODE 16 QAM modulation matlab vhdl code for qam verilog code for decimator 16-QAM DSP48E UG073 UG193

code fir filter in vhdl

Abstract: digital FIR Filter verilog HDL code clock-cycle-accurate FIR filter models (also known as bit-true models) in the Verilog HDL and VHDL languages and in the , provides a fully integrated finite impulse response (FIR) filter development environment optimized for use , FIR Compiler The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1­2. Figure 1­2. Basic FIR Filter xin Z -1 Z -1 Z -1 Z -1 Tapped Delay Line C0 C1 C2 C3 , . A fully parallel, pipelined FIR filter implemented in an FPGA can operate at very high data rates
Altera
Original
code fir filter in vhdl digital FIR Filter verilog HDL code low pass fir Filter VHDL code verilog code for linear interpolation filter 16 QAM adaptive modulation matlab low pass Filter VHDL code

digital FIR Filter verilog code

Abstract: digital FIR Filter VHDL code clock-cycle-accurate FIR filter models (also known as bit-true models) in the Verilog HDL and VHDL languages and in , support Features The Altera® FIR Compiler implements a finite impulse response (FIR) filter MegaCore , impulse response (FIR) filter development environment optimized for use with Altera FPGA devices. You , FIR Compiler includes a coefficient generator. Many digital systems use signal filtering to remove , filters more computationally expensive. The structure of a FIR filter is a weighted, tapped delay line as
Altera
Original
digital FIR Filter verilog code digital FIR Filter VHDL code FIR Filter matlab verilog code for fir filter fir filter coding for gui in matlab FIR filter matlaB design

vhdl code for 16 prbs generator

Abstract: verilog code for pseudo random sequence generator in identical 4x interpolating polyphase FIR filters, one for I and one for Q. Each filter takes a 1-bit input , Filter Out, phases 0-3: These are the outputs of an M=4 polyphase FIR filter. All four buses are updated , Filter test input: Similar to IBIT_IN but drives Q-Channel input to Nyquist filter. Code Rate Select , Experience For the source code version, users should be familiar with Verilog HDL entry, synthesis , convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 · Supports uncoded (1/1) operation · DC to 45+ MHz
Xilinx
Original
vhdl code for 16 prbs generator verilog code for pseudo random sequence generator in EN-300-421 0x47 interleaver by vhdl vhdl code for pseudo random sequence generator V50-4

3 tap fir filter based on mac vhdl code

Abstract: verilog code for parallel fir filter The Altera® FIR Compiler implements a finite impulse response (FIR) filter MegaCore function and , Description The Altera FIR Compiler provides a fully integrated finite impulse response (FIR) filter , finite impulse response (FIR) filters and infinite impulse response (IIR) filters. Typical filter , . The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1­1. Figure 1­1. Basic FIR Filter xin Z -1 C0 Z C1 -1 Z -1 C2 Z C3 -1 Tapped Delay
Altera
Original
3 tap fir filter based on mac vhdl code verilog code for parallel fir filter VHDL code for FIR filter vhdl code hamming polyphase FIR filter interpolation matlaB simulink design FIR Filter verilog code

verilog hdl code for encoder

Abstract: X9013 It is basically two identical 4x interpolating polyphase FIR filters, one for I and one for Q. Each , Filter test input: Similar to IBIT_IN but drives Q-Channel input to Nyquist filter. Code Rate Select , register in the core. I-Channel Nyquist Filter Out, phases 0-3: These are the outputs of an M=4 polyphase FIR filter. All four buses are updated once per symbol clock, CLK. External logic commutates values on , Selectable convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 Supports uncoded (1/1) operation DC to 45
Xilinx
Original
verilog hdl code for encoder X9013 prbs generator using vhdl digital FIR Filter verilog code polyphase 171OCT vhdl code for pseudo random sequence generator in

verilog code for fir filter using DA

Abstract: vhdl code for FFT 4096 point impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and , -1 a(N-1) y(n) Figure 1: Conventional Tapped Delay Line FIR Filter Representation DS795 October , . Table 2: Filter Configuration Support Matrix Filter Configuration Conventional Single-rate FIR Half-band FIR Hilbert Transform [Ref 3] Interpolated FIR [Ref 4] [Ref 5] Polyphase Decimator Polyphase , also optional is available. Table 3 defines the FIR filter port names and port functional descriptions
Xilinx
Original
vhdl code for FFT 4096 point FIR FILTER implementation on fpga FDATOOL AMBA AXI4 verilog code p4826 vhdl code for radix 2-2 parallel FFT 16 point TM-7000

verilog code for interpolation filter

Abstract: verilog code for decimation filter Low Latency CPRI High-Speed Data Conversion FIR Filter Generator Supports the Physical Link , Self-checking test bench with programs to generate golden output Verilog source code is provided to enable , · FIR Filter Generator IP Core · 3GPP-LTE CTC Decoder nd WiMAX 802.16 CTC Decoder IP Cores from , Low-Cost Digital SERDES ·Ideal for low-cost chip-to-chip and small form-factor backplane applications Up , Decimation and Interpolation ratios from 2 to 256 Support for half-band filter Signed or unsigned data
Lattice Semiconductor
Original
JESD204 gsm simulink VITA-57 fmc ECP3-150 ofdm predistortion Lattice ECP3 ECP3-35 JESD204APCI JESD204A 1-800-LATTICE I0197B

dsp ssb hilbert modulation demodulation

Abstract: adc matlab audio block diagram poly-phase decomposition of a FIR filter are equal to the down-sampling factor M. M= Down-sampling vs , band filter is unwanted they can be replaced by a FIR filter decomposed into a poly-phase structure , should be compared to a CORDIC solution, which is computational expensive. FIR Filter Design The , base on the window method. FIR Polyphase decomposition We can take advantage of decomposition the FIR filter, when using down-sampling, by utilizing the properties of the noble identity. Before
Innovate Nordic
Original
dsp ssb hilbert modulation demodulation adc matlab audio block diagram half band filter MATLAB code for halfband filter adc matlab code hilbert 2453V

DSP48

Abstract: digital FIR Filter verilog code in hearing aid names in Chapter 3, "MACC FIR Filters." 07/05/06 2.2 Updated "VHDL and Verilog Instantiation , Filters Using the DSP48." 06/08/07 2.5 Removed duplicate Verilog code implementation information , . . . . . . . . . . . . . . . . . 65 Single-Multiplier MACC FIR Filter . . . . . . . . . . . . . . , 74 Symmetric MACC FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual-Multiplier MACC FIR Filter . . . . . . . . . . . . . . . . . . . . .
Xilinx
Original
digital FIR Filter verilog code in hearing aid transposed fir Filter VHDL code verilog code for barrel shifter MULT18X18_PARALLEL.v Parallel FIR Filter UG-073

UG639

Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR Filter Generation . . . . . . . , UG639 (v 13.1) March 1, 2011 FIR Filter Generation FIR Filter Generation System Generator , FIR Compiler block for filter implementation, and use of the FDATool for filter design. System , an algorithmic operation such as a FIR filter or Matrix inverse. The MCode block provides a , . . . . . . . Generating the HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Xilinx
Original
Abstract: . . . . . 8 FIR Filter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , for DSP Getting Started Guide UG639 (v 14.3) October 16, 2012 FIR Filter Generation FIR Filter , in the Xilinx devices, use of the FIR Compiler block for filter implementation, and use of the , a FIR filter or Matrix inverse. The MCode block provides a convenient and efficient method for , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating the HDL Code . . Xilinx
Original

verilog code for 2-d discrete wavelet transform

Abstract: XAPP921c Digital Video Test Pattern Generators XAPP248 Video Starter Kit Virtex-4SX35 Virtex-EM FIR Filter , · Polyphase Transform · Matched Filter · Baseband Functions XtremeDSP slices are used in the , Vendor FIR Filter using DPRAM eInfochips Inc. FIR Filter, Parallel Distributed Arithmetic , ) Pentek, Inc. Filters FIR Filter Compiler Cascaded Integrator Comb (CIC) MAC FIR Filter , Integrator Comb (CIC) manpack wideband SDR radios Distributed Arithmetic FIR Filter MAC FIR Filter -
Xilinx
Original
verilog code for 2-d discrete wavelet transform XAPP921c simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl

vhdl code for DES algorithm

Abstract: XAPP921c -4SX35 Digital Video Test Pattern Generators XAPP248 JTAG Emulators Virtex-EM FIR Filter for Video , Channelization · DDC · Polyphase Transform · Matched Filter · Baseband Functions XtremeDSP slices are , 2008 AllianceCORE FIR Filter Compiler Vendor 4 Cascaded Integrator Comb (CIC) 4 MAC FIR Filter 4 FIR Filter using DPRAM 4 eInfochips Inc. FIR Filter, Parallel , ) 4 manpack wideband SDR radios Distributed Arithmetic FIR Filter 4 MAC FIR Filter 4 -
Xilinx
Original
vhdl code for DES algorithm FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model XILINX vhdl code REED SOLOMON encoder decoder LMS simulink
Showing first 20 results.