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detailed circuit dc cdi timing

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: CLIPPING IOUTAP DAC A IOUTAN ALIGNP 16 x2 x2 x2 LVDS DDR/ DIF 16 CDI MDS COARSE , bias current DC current maximum VIL Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN) Ibias IO(fs , output voltage data rate compliance range LVDS input timing fdata fs(max) specification must be , 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DAC output timing fs(max) ts , ps ps ps ps ps Test [1] Min Typ Max Unit Internal PLL timing 40-bit NCO frequency Integrated Device Technology
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Abstract: timing of Table 5). The main function of the Clock Domain Interface (CDI) is to resynchronize the input , 16-bit phase adjustment SPI DCMSU cos IO0 LDCLKP CDI FIR 2 x2 FIR 3 x2 , outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN) Ibias bias current DC current IO(fs) full-scale , V auxiliary output voltage LVDS input timing fdata data rate fs(max) specification , Parameter Test[1] Conditions Min Typ Max Unit DAC output timing fs(max) maximum -
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Abstract: / DIF 16 CDI MDS COARSE OFFSET CONTROL REF. BANDGAP AND BIASING GAPOUT VIRES Dual 16 , level = 1 V (p-p). Symbol Ibias IO(fs) Parameter bias current Conditions DC current Test[1] D D Min 8.1 , rate compliance range LVDS input timing fdata fs(max) specification must be C respected (fs = , Msps DAC output timing maximum sampling rate settling time sampling rate NCO frequency to ± 0.5 LSB Internal PLL timing 40-bit NCO frequency range; fs = 1000 Msps +499.99909 0.9095 - Low-power NCO Integrated Device Technology
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Abstract: bias current DC current maximum VIL Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN) Ibias IO(fs , timing fdata fs(max) specification must be respected (fs = fdata interpolation factor) fDATA = 184.32 , Typ Max Unit DAC output timing fs(max) ts fs fNCO sampling rate settling time sampling rate , 1000 Msps ns Msps Internal PLL timing 40-bit NCO frequency range; fs = 1000 Msps +499.99909 , finite resistance and the inductance between the receiver and the driver circuit ground voltages Integrated Device Technology
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detailed circuit dc cdi timing

Abstract: ADS8327 tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use , (500 kHz, +VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC Performance ­ ±1.5 LSB Typ , EOC/INT/CDI 1 Please be aware that an important notice concerning availability, standard , . www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated , Input capacitance 40 No ongoing conversion, DC Input Input leakage current pF nA 108
Texas Instruments
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Abstract: -2 MSB-3 MSB-4 MSB-5 MSB-6 LSB+2 LSB+1 LSB tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing , +VA 5.5 V, 900-kHz Sampling Rate 2.7 V +VA 3 V Excellent DC Performance ­ ±1.0 LSB Typ, ±1.75 LSB , /INT/CDI 1 Please be aware that an important notice concerning availability, standard warranty , rejection ratio Noise PSRR Power-supply rejection ratio At FFFFh output code (3) At dc VI = 0.4 VPP at 1 MHz , +0.75 70 50 33 78 0.25 1.75 2.5 1 2 1 1.25 16 Bits Bits LSB (2) LSB (2) No ongoing conversion, dc input Texas Instruments
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Abstract: x2 - LVDS DDR/ DIF 16 CDI MDS COARSE OFFSET CONTROL REF. BANDGAP AND BIASING , input current input capacitance bias current DC current pins IO0, IO1, SDO, and SDIO pins IO0, IO1, SDO , (aux) auxiliary output voltage data rate compliance range LVDS input timing fdata fs(max , 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DAC output timing fs(max) ts fs fNCO maximum , ] Min Typ Max Unit Internal PLL timing 40-bit NCO frequency range; fs = 1000 Msps +499.99909 Integrated Device Technology
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Abstract: -2 MSB-3 MSB-4 MSB-5 MSB-6 LSB+2 LSB+1 LSB tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing , +VA 5.5 V, 900-kHz Sampling Rate 2.7 V +VA 3 V Excellent DC Performance ­ ±1.0 LSB Typ, ±1.75 LSB , /INT/CDI 1 Please be aware that an important notice concerning availability, standard warranty , rejection ratio Noise PSRR Power-supply rejection ratio At FFFFh output code (3) At dc VI = 0.4 VPP at 1 MHz , +0.75 70 50 33 78 0.25 1.75 2.5 1 2 1 1.25 16 Bits Bits LSB (2) LSB (2) No ongoing conversion, dc input Texas Instruments
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active bandpass filter 300 khz

Abstract: +2 LSB+1 LSB tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While , , Low Power: ­ 10.6 mW (500 kHz, +VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC , CONVST EOC/INT/CDI 1 Please be aware that an important notice concerning availability, standard , . www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated , ratio At FFFFh output code (3) At dc VI = 0.4 Vpp at 1 MHz ­0.25 16 ­2 ­3 ­1 ­1 ­0.5 ­0.8 ±1.2 ±2 ±0.6
Texas Instruments
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detailed circuit dc cdi timing

Abstract: ADS8327 tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use , (500 kHz, +VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC Performance ­ ±1.5 LSB Typ , EOC/INT/CDI 1 Please be aware that an important notice concerning availability, standard , . www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated , Input capacitance 40 No ongoing conversion, DC Input Input leakage current pF nA 108
Texas Instruments
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Abstract: -2 MSB-3 MSB-4 MSB-5 MSB-6 LSB+2 LSB+1 LSB tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing , +VA 5.5 V, 900-kHz Sampling Rate 2.7 V +VA 3 V Excellent DC Performance ­ ±1.0 LSB Typ, ±1.75 LSB , /INT/CDI 1 Please be aware that an important notice concerning availability, standard warranty , rejection ratio Noise PSRR Power-supply rejection ratio At FFFFh output code (3) At dc VI = 0.4 VPP at 1 MHz , +0.75 70 50 33 78 0.25 1.75 2.5 1 2 1 1.25 16 Bits Bits LSB (2) LSB (2) No ongoing conversion, dc input Texas Instruments
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detailed circuit dc cdi

Abstract: detailed circuit dc cdi timing Characteristics - Data Timing - MOD Mode (Figure 20) Characteristics 1 2 3 4 Di/CDi Data Setup Time Di/CDi Data , ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet Features · · · · · · · · · Full duplex transmission over a single twisted pair , allow an easy DSTi/Di CDSTi/ CDi Transmit Interface Prescrambler Scrambler Differentially , RegC Control Register Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing
Zarlink Semiconductor
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detailed circuit dc cdi detailed circuit dc cdi timing MT9171AE MT9171AN MT9171AP MT9171APR MT9171ANR MT9172AE
Abstract: ISO2-CMOS ST-BUSTM FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features · · · · · · · · · DS5130 · · February 1999 Ordering , . DSTi/Di CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Transmit Interface Control , Estimate - DPLL + MUX Receive Filter LOUT LOUT DIS VBias Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Differentially Mitel Semiconductor
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MT9172AN MT9172AP MT9171 MT9172 MT8971 MT8972

DS5130

Abstract: MT9172AE ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features · · · · · · · · · DS5130 · · February 1999 Ordering Information , . DSTi/Di CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Transmit Interface Control , Estimate - DPLL + MUX Receive Filter LOUT LOUT DIS VBias Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Differentially
Zarlink Semiconductor
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cdi circuit diagram

telephone* -"transmission lines" awg attenuation

Abstract: circuit diagram of PPM transmitter and receiver ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features · · · · · · · · · DS5130 · · February 1999 Ordering Information , . DSTi/Di CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Transmit Interface Control , Estimate - DPLL + MUX Receive Filter LOUT LOUT DIS VBias Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Differentially
Zarlink Semiconductor
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telephone* -"transmission lines" awg attenuation circuit diagram of PPM transmitter and receiver symbol period digital communications

Biphase decoder

Abstract: cdi unit ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features · · · · · · · · · DS5130 · · February 1999 Ordering Information , . DSTi/Di CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Transmit Interface Control , Estimate - DPLL + MUX Receive Filter LOUT LOUT DIS VBias Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect Differentially
Zarlink Semiconductor
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Biphase decoder cdi unit zarlink modem C333P
Abstract: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features · · · · · · · · · Full duplex transmission over a single twisted pair Selectable 80 or , 160 kbit/s single chip modem DSTi/Di CDSTi/ CDi Transmit Interface Prescrambler Scrambler , MS1 MS2 RegC Control Register Transmit Timing VBias Address Echo Canceller Error Signal Echo Estimate - DPLL MUX LOUT DIS Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Zarlink Semiconductor
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Telecom

Abstract: detailed circuit dc cdi timing ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet Features March 2006 · Full duplex transmission over a single twisted pair , modem F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Reel Reel Description · CDSTi/ CDi Reel , LOUT LOUT DIS VBias Transmit Timing Transmit/ Clock Receive Timing & Control Sync , NC F0/CLD CDSTi/CDi CDSTo/CDo VSS 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4
Zarlink Semiconductor
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Telecom dc dc for CDI Circuit Philips Varistors MT9171/72AE MT9171/72AN MT9171/72AP MT9171/72APR MT9171/72ANR MT9171/72AE1
Abstract: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet March 2013 Features Ordering Information â'¢ Full-duplex , '¢ 80 or 160 kbit/s single chip modem CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 , Scrambler Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control , Timing - MOD Mode (Figure 18)â' Changed unit from 'ms' to 'us' for items 1, 2, 4, 5, 6, and 7. 23 Microsemi
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MT9171/72AP1 MT9171/72AN1 MT9171/72APR1 MT9171/72ANR1

MT9173

Abstract: MT9173AE ® ISO2-CMOS ST-BUSTM FAMILY MT9173/74 Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB Features · · ISSUE 2 · · · · · Ordering Information , CDSTi/ CDi F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 Transmit Interface Control Register , + MUX Receive Filter LOUT LOUT DIS VBias Transmit Timing Master Clock Phase Locked Transmit/ Clock Receive Timing & Control Sync Detect +85°C Description Applications
Mitel Semiconductor
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MT9173AE MT9173AN MT9173AP MT9174AE MT9174AN MT9174AP MT9173 MT9174
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