I74F112D,602 datasheet
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NXP Semiconductors
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Dual J-K negative edge-triggered flip-flop - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 100 MHz; Logic switching levels: TTL ; Number of pins: 16 ; Output drive capability: -1/+20 mA ; Propagation delay: 5 ns; Voltage: 4.5-5.5 V; Package: SOT109-1 (SO16); Container: Tube (Signetics)
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Original
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