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Part Manufacturer Description Datasheet BUY
EP7312-IV-90Z Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, SRAM:48KB; Number of I/O Pins:27; Number of Timers 8/12/16/32 Bits:0 / 0 / 2 / 0; No. of PWM Channels:2; Clock Speed:90MHz; Interfaces:SSI, UART RoHS Compliant: Yes BUY
EP7311-CB-90Z Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, RAM:48KB; No. of I/O Pins:27; No. of PWM Channels:2; Clock Speed:90MHz; Interface:SSI, UART; Package/Case:256-PBGA; Memory Organization - RAM :48 KB RoHS Compliant: Yes BUY
EP7311-IV-90Z Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, SRAM:48KB; Number of I/O Pins:27; Number of Timers 8/12/16/32 Bits:0 / 0 / 2 / 0; No. of PWM Channels:2; Clock Speed:90MHz; Interfaces:SSI, UART RoHS Compliant: Yes BUY
EP7309M-CVZ Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, RAM:48KB; No. of I/O Pins:27; No. of PWM Channels:2; Clock Speed:74MHz; Interface:SSI, UART; Package/Case:208-LQFP; Leaded Process Compatible:Yes RoHS Compliant: Yes BUY
EP7311-IBZ Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, RAM:48KB; No. of I/O Pins:27; No. of PWM Channels:2; Clock Speed:74MHz; Interface:SSI, UART; Package/Case:256-PBGA; Memory Organization - RAM :48 KB RoHS Compliant: Yes BUY
EP7312-IB-90Z Cirrus Logic 32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, RAM:48KB; No. of I/O Pins:27; No. of PWM Channels:2; Clock Speed:90MHz; Interface:SSI, UART; Package/Case:256-PBGA; Memory Organization - RAM :48 KB RoHS Compliant: Yes BUY

datasheet+of+16450+UART

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 0 PLB 16450 UART (v1.00c) DS432 (v2.3) July 9, 2003 0 0 Product Overview , .3) July 9, 2003 Product Overview www.xilinx.com 1-800-255-7778 1 PLB 16450 UART (v1.00c) UART Background The PLB 16450 performs parallel to serial conversion on characters received from the , , are prioritized and can be identified by reading an internal register. 16450 UART Design Parameters , DS432 (v2.3) July 9, 2003 Product Overview PLB 16450 UART (v1.00c) UART I/O Signals The I/O National Semiconductor
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PC16550D 16450 UART datasheet of 16450 UART UART using VHDL UART DESIGN uart 16450 timing
Abstract: 0 OPB 16450 UART DS433 August 18, 2004 0 0 Product Specification Introduction , Specification www.xilinx.com 1-800-255-7778 1 OPB 16450 UART · System clock frequency of 100 MHz UART Background The OPB 16450 performs parallel to serial conversion on characters received from the , , are prioritized and can be identified by reading an internal register. 16450 UART Design , Product Specification OPB 16450 UART Allowable Parameter Combinations There are no restrictions on Xilinx
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National Semiconductor PC16550D UART IPIF asynchronous uart vhdl vhdl 8 bit parity generator code
Abstract: version of the original N S16450 Universal Asynchronous Receiver/Trans­ mitter (UART). Functionally , running all existing 16450 software. In this mode internal FIFOs are activated allowing 16 bytes (plus , the CPU. â  Pin for pin compatible with the existing 16450 except for C S O U T (24) and NC (29 , registers are identical to the 16450 reg­ ister set. â  Adds or deletes standard asynchronous , the 16450 M ode eliminate the need for precise synchronization between the CPU and serial data -
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PC16550C/NS16550AF 16550C S16550A NS16450 TL/C/8652-1
Abstract: upon power up, the UART is compatible with 16450. When the FIFO mode is activated, it allows 16 bytes , Eureka Technology EP600 UART Product Summary FEATURES · Functionally compatible with 16550. · Supports Character (16450) and FIFO (16550) mode operations. · Designed optimized for ASIC and , register in non-FIFO mode eliminates the need for precise synchronization between the CPU and UART. · Add , Fax: 1 650 960 3805 http://www.eurekatech.com Eureka Technology EP600 UART DESCRIPTIONS Eureka Technology
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of 16450 UART design of UART 16450 16550 uart timing EP600 programming
Abstract: Features 16450/16550 Compatible 16 byte transmit FIFO IPCUART-APB-APB 16450/16550 Compatible UART Core 16 byte receive FIFO Modem control Programmable baud rate gene- rator , Access Modes Loopback Mode The IPC-UART-APB is a 16450/16550 compatible Universal Asynchronous Receiver/Transmitter (UART). The IPC-UART-APB contains a baud rate generator that can be configured to , the UART functions. Status information can be read at any time during operation. The IPC-UART-APB has Cast
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16550 uart timing diagram uart verilog testbench AMBA APB UART 16550 uart UART testbench of a transmitter in verilog
Abstract: MODEM ports are produced independently by the UART for each port using the standard 16450 MODEM Control , TSS4550 provides the standard set of 16450 UART registers which are accessed in much the same way and at , '¢ Control Register 2: CR2. The following standard 16450 UART registers have a slightly modified , Control Register. Only relevant for UART register operations. 3) The use of bits in this standard 16450 , port 1. Operation as specified in 16450 data sheet. bit 1 - RTS1: UART RTS control for MODEM port 1 -
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8432MH 6864M
Abstract: Semiconductor 16550 UART, that works in both 16450 and 16550 UART modes. For complete details please refer the , ddis Note: 1. 16450 UART mode does not support the FIFOs 2. 16450 UART mode does not support the , modem features of UART. The UART 16550 module of XPS 16550 UART can be configured for 16450 or 16550 , _16550 is set to zero, the UART 16x550 module works without FIFOs in 16450 mode. DS577 April 18, 2007 , baudoutN 0 integer G13 Select 16450/16550 UART C_IS_A_16550 0 : 16450 mode 1 : 16550 Xilinx
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uart 16550 XPS 16550 UART v1.00a 0x1008 UART16550 XC4VLX40-FF1148 UART-16550 128-B
Abstract: TSS4550 4. Programming Interface TSS4550 provides the standard set of 16450 UART registers which are , : CR2. The following standard 16450 UART registers have a slightly modified utilisation: D MODEM , standard 16450 register are modified for use in TSS4550. 4) Don't care state. 5) The UART Transmit , . Operation as specified in 16450 data sheet. bit 1 ­ RTS1: UART RTS control for MODEM port 1. Operation as specified in 16450 data sheet. bit 2 ­ DTR2: UART DTR control for MODEM port 2 (standard 16450 OUT1 bit Temic Semiconductors
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diagrams of 16450 UART TFDS3000 Uart led 6864MH
Abstract: EPROM (8031 compatible firmware) and external RAM can be used with the chip. 16450 UART. The 16450 is , is 100% register compatible with a 16450 chip. 16 byte UART FIFO. The 16550 is a FIFO version , YAMAHA' L S I NEW PRODUCT GTM415 FAX VOdem Controller with Built-in High Speed UART 1995.2 , core with a 16550 UART and autobaud circuitry in a single IC designed to operate in 5V, 3.3 V, and mixed 3.3V/5V systems. The integration of the CPU, UART, glue logic, and the 3.3V operation in GTM415 -
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8031 MICROCONTROLLER architecture 8031 serial software interface pc 78dl Autodialer Autodialer with 8051 microcontroller GTM407 YTM403
Abstract: independent asynchronous serial I/O (SIO) channels. Each channel is compatible with the 16450 UART found in , stack and CPU continues from the Instruction Pointer saved on the stack. Design Limits The 16450 , circuit cannot be operated beyond a certain frequency for reliable operation. The limit for the 16450 UART used in the Intel386 EX microprocessor is 17 MHz. This incoming clock will be divided by the , maximum baud rate achievable with the 16450 SIO module used in the Intel386 EX microprocessor is Intel
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386TM
Abstract: RZIReturn-to-Zero-Inverted 1.2 EMMA Mobile1 UART0UART1UART2 3 UART 64 FIFO non-FIFO 16450 16 FIFO , UART EMMA MobileTM1 | S19262JJ3V0UM00 September 2009 2008 2 , 20099 4 S19262JJ3V0UM EMMA Mobile1EM1 UART EM1 UART 1 2 3 4 5 UART , Flash S19260J SPI S19261J UART S19263J S19264J S19265J NEC
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MC-10118A PD77630A S19255J S19266J LSR5000 MSR-500 MSR500 LS29 FCR5000 S19657J S19686J S19253J S19254J
Abstract: original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on , changed to allow signalling of DMA transfers The UART performs serial-to-parallel conversion on data , received from the CPU The CPU can read the complete status of the UART at any time during the functional , performed by the UART as well as any error conditions (parity overrun framing or break interrupt) The UART , are also included to use this 16 c clock to drive the receiver logic The UART has complete National Semiconductor
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AN-628 NS16550A AN-692 AN-739 RS-232C COP800
Abstract: The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put into an , UART register TXRDY Mode 0 In the 16450 Mode (FCR0 e 0) or in the FIFO Mode (FCR0 e 1 FCR3 e 0) and , system efficiency Two pin functions have been changed to allow signalling of DMA transfers The UART , complete status of the UART at any time during the functional operation Status information reported National Semiconductor
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PC16550 PC16550dn V44A PC16550DVEF PC16550DV N40A D-82256
Abstract: Features The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put , UART performs serial-to-parallel conversion on data characters received from a peripheral device or a , complete status of the UART at any time during the functional operation Status information reported includes the type and condition of the transfer operations being performed by the UART as well as any Texas Instruments
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SNLS378B
Abstract: version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put into an alternate mode (FIFO mode) to , UART is fabricated using National Semiconductor's advanced M2CMOS process Can also be reset to 16450 , have been changed to allow signalling of DMA transfers The UART performs serial-to-parallel conversion , data characters received from the CPU The CPU can read the complete status of the UART at any time Texas Instruments
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RRD-B30M75
Abstract: The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put into an , system efficiency Two pin functions have been changed to allow signalling of DMA transfers The UART , complete status of the UART at any time during the functional operation Status information reported includes the type and condition of the transfer operations being performed by the UART as well as any National Semiconductor
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C1995 N-40A DS1488 VEF44A
Abstract: 16450 and 16550 UART modes. For complete details please refer the National Semiconductor data sheet , Transmitter baudoutN Baud Generator Modem Logic Note: 1. 16450 UART mode does not support the FCR. 2. 16450 UART mode does not support the FIFOs. rxrdyN rclk sin sout txrdyN xin xout , UART. The UART 16550 module of XPS 16550 UART can be configured for 16450 or 16550 mode of operation , UART 16550 module works without FIFOs in 16450 mode. In 16550 mode, the FIFOs can be enabled by Xilinx
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XC6SLX16-CSG324 XC6SLX16CSG324 S3ADSP3400 uart fpga 16550 uart national PLBV46
Abstract: Semiconductor 16550 UART, which works in both the 16450 and 16550 UART modes. For complete details, see the , Modem Logic Note: 1. 16450 UART mode does not support the FIFOs 2. 16450 UART mode does not , 0 integer 0 : 16450 mode 1 : 16550 mode 1 integer 25000000 integer 16550 UART , G8 G9 G10 Select 16450/16550 UART C_IS_A_16550 External xin clock frequency in Hz , the National PC16550D 16450 UART mode implementation does not include this register Register Logic Xilinx
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AMBA AXI4 XC6VLX75T-FF784 uart vhdl fpga XC7V855T V6 6D XC7K410T DS748
Abstract: H16450S UART with Synchronous Interface June 14, 2002 Product Specification AllianceCORETM , , SpartanTM-II, and Spartan-IIE devices Capable of running all existing 16450 software Fully Synchronous , . Optimized for speed 2. Assuming all core I/Os are routed off-chip June 14, 2002 1 H16450S UART , Diagram General Description Registers The H16450S is a standard UART that provides complete software compatibility with the Texas Instruments 16450 device. It performs serial-to-parallel conversion Xilinx
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parallel to serial conversion verilog VHDL Bidirectional Bus XC2S50E-7
Abstract: '¢ Schmitt trigger input on reset pin and FDC interface inputs â'¢ Two 16450 compatible UARTs â'¢ One IBM , '¢ IDE interface (for embedded AT and XT hard drives) â'¢ Single 24MHz crystal/oscillator for UART and , inputs â'¢ Two 16450 compatible UARTs â'¢ One IBM PC XT/AT compatible parallel port â'¢ One game port , '¢ Single 24MHz crystal/oscillator for UART and floppy disk controller â'¢ Fully uPD72065B and IBM BIOS , /bi-directional), two 16450 UARTs, one IDE XT/AT hard disk interface and floppy disk controller. The configuration -
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82C721 82C722 82C711/A HARD DISK power supply diagram xt bus 82C812 hard disk drive diagram 82C711 IDE Floppy Disk Controller PD72065B DDG40A3 82C71UA
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