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datasheet of 16450 UART

Catalog Datasheet MFG & Type PDF Document Tags

verilog code for UART baud rate generator

Abstract: H16450S Capable of running all existing 16450 software · Fully Synchronous design. All inputs and outputs are based on the rising edge of clock · Adds or deletes standard asynchronous communication , Features The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating from modems or other , modems and other devices CAST, Inc. April 2002 Page 1 CAST H16450S Megafunction Datasheet
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EPF10K30E EP20K30E EP1K10 verilog code for UART baud rate generator verilog code for baud rate generator baud rate generator vhdl

verilog code for transmitter

Abstract: EP1K10 Capable of running all existing 16450 software · Adds or deletes standard asynchronous , Features The H16450 is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-toparallel conversion on data originating from modems or other , . March 2002 Page 1 CAST H16450 Megafunction Datasheet Pin Description Name MR CLK RCLK RD , *DLAB is the MSB of the Line Control Register Switching Characteristics Register Write The Address
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verilog code for transmitter of 16450 UART vhdl code for serial transmitter

National Semiconductor PC16550D UART

Abstract: diagrams of 16450 UART original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on , changed to allow signalling of DMA transfers The UART performs serial-to-parallel conversion on data , received from the CPU The CPU can read the complete status of the UART at any time during the functional , Capable of running all existing 16450 software Pin for pin compatible with the existing 16450 except for , 6 0 Pin Descriptions The following describes the function of all UART pins Some of these
National Semiconductor
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National Semiconductor PC16550D UART diagrams of 16450 UART PC16550D AN-628 NS16550A AN-692 AN-739 RS-232C

16550A UART texas instruments

Abstract: interfaces are options. UART with FIFOs Core Features · · · · · · · Capable of running all existing 16450 and 16550a software Fully Synchronous design. All inputs and outputs are based on rising edge of , H16550S General Description The H16550S is a standard Universal Asynchronous Receiver/Timer (UART , character mode or in 16550compatible FIFO mode, where an internal FIFO relieves the CPU of excessive , of interrupts presented to the CPU Adds or deletes standard asynchronous communication bits (start
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16550A UART texas instruments APA150-STD AX500-3 A54SX32A-3 RT54SX32S-2

XC6SLX16-CSG324

Abstract: XC6SLX16CSG324 and software functionality of the National Semiconductor 16550 UART, which works in both the 16450 and , conversion on characters received from a modem or serial peripheral. The AXI UART 16550 is capable of , monitored by the internal register set. The AXI UART 16550 is capable of signaling receiver, transmitter and , between a user IP core and the AXI interface standard. To simplify the process of attaching the AXI UART , , programmable Baud Generator and Modem logic modules. The UART16550 module of AXI UART 16550 can be configured
Xilinx
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XC6SLX16-CSG324 XC6SLX16CSG324 uart 16550 HOLDING XC7K410TFFG676-3 16550 uart timing DS748 TM-7000

N82077

Abstract: pc87393 change without notice. All the trademarks of products and companies mentioned in this datasheet belong to , Devices for Portable Applications General Description Winbond's PC8739x family of LPC SuperI/O devices is targeted for a wide range of portable applications. PC99 and ACPI compliant, the PC8739x family , , IrDA 1.1 compliant), GeneralPurpose Input/Output (GPIO) support for a total of 32 ports, Interrupt , . The feature lists for other PC8739x devices may differ. See the table on page 3 for a list of features
Winbond Electronics
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N82077 pc87393 NEC floppy drive UPD765A PC87391 PC87392 PC87393 PC87393F 100-P PC8739

16650 uart

Abstract: uart 16650 timing D16950 Configurable UART with FIFO ver 1.02 OVERVIEW The D16950 is a soft core of a Universal , . The CPU can read the complete status of the UART at any time during the functional operation , registers that gives additional capabilities of configuration of UART work. Data transmission may be , KEY FEATURES Detection of bad data in receiver FIFO Software compatible with 16450, 16550 , features have been included): Transmitter FIFO - the Tx portion of the UART transmits data through SO
Digital Core Design
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16650 uart uart 16650 timing vhdl code for fifo and transmitter uart 16750 baud rate "flow control" test bench verilog code for uart 16550 verilog code for 8 bit shift register OX16C950 D16450 D16550 D16750 D16552 D16752

design IP Uarts using verilog HDL

Abstract: uart vhdl code fpga D16750 Configurable UART with FIFO ver 2.08 OVERVIEW The D16750 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , , change the FIFO size. So in applications with area limitation and where the UART works only in 16450 , BAUD clock line Two modes of operation: UART mode and FIFO mode In the FIFO mode
Digital Core Design
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TL16C750 D16754 design IP Uarts using verilog HDL uart vhdl code fpga verilog hdl code for parity generator verilog code for 8 bit fifo register asynchronous fifo design in verilog D16X50

test bench verilog code for uart 16550

Abstract: verilog code for UART baud rate generator D16550 Configurable UART with FIFO ver 2.20 OVERVIEW The D16550 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , FIFO size. So in applications with area limitation and where the UART works only in 16450 mode , configurable BAUD clock line Two modes of operation: UART mode and FIFO mode Majority Voting
Digital Core Design
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TL16C550A test bench code for uart 16550 vhdl code for 4 bit even parity generator address generator logic vhdl code vhdl code for uart communication vhdl code for binary data serial transmitter parallel to serial conversion verilog

test bench verilog code for uart 16550

Abstract: test bench code for uart 16550 UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic , D16550 Configurable UART with FIFO ver 2.03 OVERVIEW The D16550 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , a number of clock trees in complete system. KEY FEATURES Software compatible with 16450 and
Digital Core Design
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verilog code for uart communication in fpga verilog code for uart communication VHDL Bidirectional Bus verilog hdl code for uart APEX20K APEX20KC

vhdl code for asynchronous fifo

Abstract: verilog hdl code for parity generator D16550 Configurable UART with FIFO ver 2.08 OVERVIEW The D16550 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , FIFO size. So in applications with area limitation and where the UART works only in 16450 mode , capability Separate configurable BAUD clock line Two modes of operation: UART mode and FIFO
Digital Core Design
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vhdl code for asynchronous fifo uart false start uart vhdl fpga vhdl code for Digital DLL APEX20KE FLEX10KE

16750 UART texas instruments

Abstract: vhdl code for fifo and transmitter D16750 Configurable UART with FIFO ver 2.20 OVERVIEW The D16750 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , , change the FIFO size. So in applications with area limitation and where the UART works only in 16450 , BAUD clock line Two modes of operation: UART mode and FIFO mode In the FIFO mode
Digital Core Design
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16750 UART texas instruments uart 16750 uart 16750 baud rate vhdl code for 8 bit shift register TL16C750A vhdl code for 8 bit parity generator

LPC bus

Abstract: winbond tpm GPIOs General Description The PC87381, a member of the Winbond LPC SuperI/O family, is targeted for , total of 11 ports. The PC87381 minimizes the number of legacy devices on the motherboard, thus taking , ) - Software compatible with the 16550A and the 16450 - Shadow register support for write-only bit monitoring - UART data rates up to 1.5 Mbaud 11 General-Purpose I/O (GPIO) Ports - Six support assert IRQ , mechanism Strap Configuration - Base Address (BADDR) strap to determine the base address of the Index-Data
Winbond Electronics
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LPC bus winbond tpm RC6 Infrared PC2001

wpct200

Abstract: winbond* wpct200 Serial Ports and GPIOs General Description Outstanding Features The WPCN381U, a member of the , Serial Ports and General-Purpose Input/Output (GPIO) support for a total of 11 ports. Pin and , CLKRUN and LPCPD signals) The WPCN381U is a "no-frills" solution for the new generation of notebook , 16550A and the 16450 - Shadow register support for write-only bit monitoring - FIR IrDA 1.1 compliant - HP-SIR - ASK-IR option of SHARP-IR - DASK-IR option of SHARP-IR - Consumer Remote Control
Winbond Electronics
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wpct200 winbond* wpct200 WPCT 16550A wpc876xl WPCT200 WPC876

verilog code for UART baud rate generator

Abstract: vhdl code for uart communication compatible with 16450 and 16550 UARTs Two modes of operation: UART mode and FIFO mode , Configurable UART with FIFO ver 1.05 OVERVIEW The D16550 is a soft Core of a Universal , can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART , 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources
Digital Core Design
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VHDL description for an 8-bit even/odd parity vhdl code for 8-bit parity generator interrupt controller verilog code download UART using VHDL vhdl code for 8 bit ODD parity generator vhdl code parity

16550a

Abstract: 87383 compatible with the 16550A and the 16450 - Shadow register support for write-only bit monitoring - UART , change without notice. All the trademarks of products and companies mentioned in this datasheet belong to , Description The PC87383, a member of the Winbond LPC SuperI/O family, is targeted for a wide range of , of 21 ports. Outstanding Features LPC bus interface, based on Intel's LPC Interface , EPP 1.7 and EPP 1.9 - Supports EPP as mode 4 of the Extended Control Register (ECR) - Selection of
Winbond Electronics
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87383

verilog code 16 bit processor

Abstract: uart vhdl code fpga D16450 Configurable UART ver 2.07 OVERVIEW The D16450 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450. D16450 performs , and condition of the transfer operations being performed by the UART, as well as any error , compatible with 16450 UART Configuration capability Separate configurable BAUD clock line , UART Mode Design UARTS number The family of DCD D16X50 UART IP Cores combine a
Digital Core Design
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verilog code 16 bit processor verilog code for ring counter design of UART by using verilog verilog code for uart vhdl code for parallel to serial shift register modem system block diagram

87382DG

Abstract: Winbond LPC compatible with the 16550A and the 16450 - Shadow register support for write-only bit monitoring - UART , Infrared Port, Serial Port and GPIOs General Description The PC87382, a member of the Winbond LPC SuperI/O family, is targeted for a wide range of portable applications. The PC87382 is PC2001 and ACPI , compliant), Serial Port, and General-Purpose Input/Output (GPIO) support for a total of eight ports. The PC87382 enables glueless implementation of an LPCto-LPC Switch between the motherboard LPC bus and the
Winbond Electronics
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87382DG Winbond LPC hot 2727

diagrams of 16450 UART

Abstract: of the PC16550D Universal Asynchronous Receiver Transmitter (UART) The two serial channels are , Dual independent UARTs Capable of running all existing 16450 and PC16550D software After reset all registers are identical to the 16450 register set Read and write cycle times of 84 ns In the FIFO mode , Status Interrupt is enabled two types of DMA transfer via FCR3 When operating as in the 16450 Mode , functionally identical to the 16450 Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO
National Semiconductor
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PC16552D COP800 AN-770 PC16552C AN-798 AN-876

pc87384

Abstract: LPC bus 16450 - Shadow register support for write-only bit monitoring - UART data rates up to 1.5 Mbaud IEEE , change without notice. All the trademarks of products and companies mentioned in this datasheet belong to , of the Winbond LPC SuperI/O family, is targeted for a wide range of notebook and docking applications , , Parallel Port and General-Purpose Input/Output (GPIO) support for a total of 21 ports. Outstanding , mode 4 of the Extended Control Register (ECR) - Selection of internal pull-up or pull-down resistor
Winbond Electronics
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pc87384 clkrun ACPI CIRCUIT DIAGRAM PC87384
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