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Part Manufacturer Description Datasheet BUY
SN65LVDS047DR Texas Instruments Quad LVDS Transmitter with Flow-Through Pinout 16-SOIC -40 to 85 visit Texas Instruments
SN65LVDS048AD Texas Instruments Quad LVDS Receiver with Flow-Through Pinout 16-SOIC -40 to 85 visit Texas Instruments Buy
SN65LVDS047PWG4 Texas Instruments Quad LVDS Transmitter with Flow-Through Pinout 16-TSSOP -40 to 85 visit Texas Instruments
SN65LVDS048ADRG4 Texas Instruments Quad LVDS Receiver with Flow-Through Pinout 16-SOIC -40 to 85 visit Texas Instruments
SN65LVDS047PWR Texas Instruments Quad LVDS Transmitter with Flow-Through Pinout 16-TSSOP -40 to 85 visit Texas Instruments
SN65LVDS048APW Texas Instruments Quad LVDS Receiver with Flow-Through Pinout 16-TSSOP -40 to 85 visit Texas Instruments Buy

da-15 pinout

Catalog Datasheet MFG & Type PDF Document Tags

50-pin lcd connector pinout

Abstract: ) . 23 2 Table â' 15 EMI 0 Connector Pin-out (J27 , 19/12/2012 Notes Initial DSI connector pin-out fixed LVDS connector changed USB OTG connector Reference Designator changed MIPI CSI-2 connector pin-out changed Top view picture changed T C , . 9 1.5 Board Layout , ) . 15 2.3.5 USIM Card (J11
Variscite
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AM 22A

Abstract: MONOLITHIC MEMORIES mil pkg) SA3 AM 110-2 Code 21 AM 130-2 Code 21 AM130-3 Code 21 t DA No. 2 Pinout 1A Switch Pos. 0-7 (63S080) Switch Pos 0-6 (63S081) DA No. 7 Pinout 1B Switch Pos. 0-7 (63S140) Switch Pos. 0-6 (63S141) DA No. 4 Pinout ID Switch Pos. 2-15 (63S240) Switch Pos. 2-14 (63S241) f 635080 635081 635140 635141 , Pinout 1£ Switch Pos. 0-7 (63S440) Switch Pos 0-6 (63S441) t 63S480/81 t t 63RA481 SA31-2 t Pinout 1Ht Switch Pos. 5-14 t 63DA441/42 63S841 f SA4-4 f AM 140-3 Code 21 f t
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AM 22A MONOLITHIC MEMORIES mmi 63S140 pp17 UNIPAK 63S480 MPP-805 MOD16 UP803 F18P02 F18P08 F18P09

mmi "tiw PROM" programming

Abstract: MMI PLE5P8 ) NUMBER TERMS REGISTERS MAX* PLE5P8 5 8 32 25 PLE5P8A 5 8 32 15 PLE8P4 8 4 256 30 PLE8P8 8 8 256 , 4 2048 35 PLE11P8 11 8 2048 35 PLE12P4 12 4 4096 35 PLE12P8 12 8 4096 35 PLE9R8 9 8 512 8 15 PLE10R8 10 8 1024 8 15 PLE11RA8 11 8 2048 8 15 PLE11RS8 11 8 2048 8 15 Clock to output time for , .12 V . -1.5 V to 7 V.7 V . -0.5 V to 5.5 V.12 V -65° to , Vcc = MIN l| = -18 mA -1.5 V 'IL Low-level input current Vcc = MAX V| = 0.4 V -0.25 mA l|H
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PLE10P4 PLE10P8 PLE11P4 63S481 mmi "tiw PROM" programming MMI PLE5P8 22AA PLE9P4 9S054-1592 AM110-2 F18P01

MMi 63S141

Abstract: REGISTERS tpD (ns) MAX* INPUTS OUTPUTS PLE5P8 5 8 32 PLE5P8A 5 8 32 15 , 35 PLE9R8 9 8 512 8 15 PLE10R8 10 8 1024 8 15 PLE11RA8 11 8 2048 8 15 PLE11RS8 11 8 2048 8 15 'C lock to output tim e for , pins. The unprogrammed state of IS words are Low, presenting a CLEAR with 15 pin Low. With all 15 column words (A3-AO) programmed to the same pattern, the 15 function will be independent of both row
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MMi 63S141 PLE5P16 PLE6P16 63S281 63RS881 63S1641 PLE11RS

tsop Shipping Trays

Abstract: /EIAJ standard dimensions and 32-pin pinout Standard and reverse pinout options Maximum package , Standard Pinout Al6 Al5 tz Ai 2 tz A7 1= A6 cz A5 A4 11 12 32 31 30 29 28 27 26 25 24 23 22 21 13 14 15 16 Di Do 20 ID Ao 19 ZI Ai 18 ZI A2 17 ZI A3 ZI Zl ZI ZI ZI ZI ZI : ZI ZI ZI OE CE , Reverse Pinout Da C Vss C D2 C D i C= Do CZ Ao CZ A, C Ä2 d Aa CI 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Z] ZI ZI Ai 1 Ag As ^ ZI ZU ZI
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tsop Shipping Trays 28F010

AMD K10 Processor

Abstract: amd k10 CD010342 Figure 2. Am7971A Pinout for Leadless Chip Carrier (LCC) nnnn i-in n n n nn n n n nn n 61 D *D , C 60 4« 48 47 4« 46 44 43 42 41 40 30 36 37 36 35 3 *15 O ^ i O O Ì Q O < fi O , Figure 3. Am7971A Pinout for Plastic Leaded Chip Carrier (PLCC) 183 A B c 0 E F , ) Pinout for a Pin Grid Array (PGA) Package PIN D E S IG N A T IO N S (S O R T E D B Y PIN NAM E) PIN , a« A7 Ae Ag A 10 A 11 A 12 A13 Au A 15 ad ad ad 16 17 18 a d 19 AD m ADai AD 22 AD23
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AMD K10 Processor amd k10 7971A CGX068 CA2068 AM7971A-3 AM7971A-5 AM7971A-8

EPROM M2764

Abstract: M2128-15 inteT ¿WMK3H DMIFO^MOTCDM M2128 2048 x 8-BIT STATIC RAM MILITARY M2128-15 M2128-20 Max , Compatible Pinout Two Line Control, CE Controls Power-Down, OE Controls Output Buffers-Eliminates Bus , consumption when the device is disabled. The 24-pin industry standard pinout allows easy upgrades to higher , c 7(5) (20)22 L 8(6) (19)21 C »(7) (18)20 L 10(8) (17)19 c 11(8) (16)16 L 12(10)
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M2128-15 M2816 M2732A M2764 M27S4 EPROM M2764 eprom 8k 24pin 2kx8 EPROM

8085 memory organization

Abstract: 8085 microprocessor pin diagram POWER STANDBY â'¢ LOW POWER OPERATION â'¢ FAST ACCESS â'¢ INDUSTRY STANDARD PINOUT â'¢ SINGLE SUPPLY , that keep the active (operating) power low, and also give fast access times. The pinout of the HM , interfacing by allowing the data outputs to be controlled independant: of the chip enable. Pinout TOP VIEW , ] VCC 23 3 A8 22 ]A9 21 20 3G 19 ] AIO 18 DÃ' 17 3DQ7 16 ] DQ6 15 2 DQ5 14 ] DQ4 13 ] DQ3 A DQ T _G
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HM-6516 HM-6515 HM-6518 HM-6551 HM-6561 8085 memory organization 8085 microprocessor pin diagram functional pin diagram of 8085 information IC 8085 pin diagram 6516 2K x 8 CMOS RAM

P802

Abstract: XIP2092 .1 Interface Description Client Interface Signals Figure 3 shows the pinout for a MAC core with the optional , TX_STATISTICS_VECTOR[21:0] TX_STATISTICS_VALID PAUSE_REQ PAUSE_VAL[15:0] RX_CLK Domain RX_CLK RX_DATA[63:0 , HOST_MIIM_RDY RESET XIP2094 Figure 3: Core Pinout with XGMII Interface DS201 (v2.1) June 24, 2002 , or XAUI v2.1 Figure 4 shows the pinout of a MAC core with the optional XAUI interface. TX_CLK , XAUI_TX_L1 XAUI_RX_L1 PAUSE_REQ PAUSE_VAL[15:0] XAUI_TX_L2 XAUI_RX_L2 RX_CLK
Xilinx
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P802 XIP2092 XIP2093 XIP2095 XIP2096 XIP2097 OC-192

80C161

Abstract: D-92224 151 GND 132 152 P1.14 P1.15 GND Pinout des kitCON-Connectors X3 © PHYTEC , Programmspeicher.21 B , /connect-161 .15 3.3 Der Quad-Connector , .33 Tabelle 1: Pinout des kitCON-Connectors X3.14 Tabelle 2: Pinout des ICE/connect-161 X2.16 Tabelle 3
PHYTEC
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80C161 D-92224 kitCON-504 KITCON161 C161 C166 CON-161 L-266 D-55135

6216 sram

Abstract: 6216 ram Pinout - J1 Pin# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 , 58 60 62 64 25 R Mezzanine Pinout - J2 Pin# 1 3 5 7 9 11 13 15 17 19 21 , Mezzanine Pinout - J3 Pin# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 , ) XC6200 Development System Mezzanine Pinout - J5 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 , . 15 REFERENCES
Xilinx
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6216 sram 6216 ram da-15 pinout IC 4013E 6216 static ram pin diagram of IC 4013 n

nsa 1588A

Abstract: 1588A . PINOUT Table NSA XXXX PIN NSA NSA NSA NSA NSA NSA NSA NSA NSA NSA NSA NO. 0038 598 1166 1188 1198 1541A , Da Da c8 14 â'" c7 C7 c6 C7 Ba Ba Aa c9 C9 Ga 15 â'" Ba Ba Ba Ba NC C7 c3 Ga Ga c9 16 â'" c8 c8 c7
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nsa 1588A 1588A NSA 1198 HA 1166 NSA 598 ca c2

LHMN5

Abstract: sharp mask rom 44-pin rise / fall time I 10 ns â'¢ Input reference level I 1.5 V â'¢ Output reference level I 1.5 V â , MasK-HrogrammaDie hum â  Sharp's Product Line-up (32M-bit Mask ROM) Configuration ( wards X bit) * Pinout Model , 48TSOP (I) forward bend/ 48TSOP (I) reverse bend * M ". Mask ROM specific pinout SHARP aiâO?^Ã
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LH5332600 LH5332600N LH5332600T 2MX16 LH5332C00D LHMN5 sharp mask rom 44-pin LH5332600N/T LHMN56XX/LHMN5FXX 304X8 194304X8

U91/U92

Abstract: chemi-con U92F, 10,000 hours for U92L or 15,000 hours for U92X at â'«Ø‡58Ø'â'¬C. The rated lifetime for all , , Longest Life, Pin Options ♠â'«Ø‡52؁â'¬C ~â'«Ø‡58Ø'â'¬C 350~500 150~3,300 15,000 â , Board Pin-out * Brown Insulating Sleeve Negative Mark PC Board Pin-out A* U91F SNAP , * Vent Negative Mark PC Board Pin-out 3.3â'«1.0×¢â'¬ 4.75â'«1.0×¢â'¬ 10 2-2x See Pin , Sleeve Negative Mark A B* C PC Board Pin-out 360° 6 Dâ'«1םâ'¬ * Vent 25 2.5
United Chemi-Con
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U91/U92 chemi-con PET sleeve with end disk E92F501VSN331MR65T E91F351VND122MAA0T E92F351VND222MBA0T SM813

STKK

Abstract: tvp ul 137 160-pin EIAJ PQFP 40MHz 2.0 Pin Description and Pinout Table 2 below lists the pin types found on , number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical , (cont'd) Local Bus Interface Signal Type R Description LAD [31:0] LAD[15:0]b I/04 Z Local , AD27 52 AD7 92 NC 132 LA(Da)30 13 AD26 53 AD6 93 LAD 13 133 LA(Da)31 14 AD25 54 AD5 94 NC 134 ALE 15 , 15 137 HOLD 18 AD23 58 AD1 98 NC 138 HOLDA 19 AD22 59 ADO 99 LA(Da)16 139 ra 20 Vcc 60 Vcc 100 Vcc
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V350EPC V961PBC V960PBC STKK tvp ul 137 AD12 AD14 V350EPC-33 50EPC 16-TC 2348G

I960SX

Abstract: Frequency 33MHz 40MHz 2.0 Pin Description and Pinout Table 2 below lists the pin types found on the , . Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions , Signal LAD[31:0] LAD[15:0]b LA[31:16]b LA[5:2] ALE BE[3:0] BE[1:0]b W/R ADS ASb RDYRCV READYb HOLD HOLDA , 13 14 15 Signal VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 PIN # 41 42 43 , Data Sheet Rev 1.1 7 V350EPC Figure 1: Pinout for 160-pin EIAJ PQFP (top view) 8 V350EPC
V3 Semiconductor
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I960SX

GD16585

Abstract: GD16589 ) application is available. The part number is GD16589. The functionality and the pin-out are identically to , outline, please refer to Figure 14 and 15. In ceramic packages following pin pairs are individually , /K3, J4/K4, J5/K5, J8/K8, J9/K9, and J10/K10, please refer to "Package Pinout" Figure 8 on page 8 , 16 +3.3V VCC DI0.15 DIN0.15 16 VCO OUT OUTN CKI CKIN 0V 10Gbit/s , . Package Pinout 1 2 LX 3 L SE E IG (PH T PC B T VC VE C K TC D VD
GIGA
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GD16585 STM-64 GD16585-EF B1112 GD16585/GD16589 OIF99 GD16585-EB HCGD16585EB
Abstract: intéT M2128 2048 x 8-BIT STATIC RAM M ILITA RY M2128-15 150 150 50 Max. Access Time , Pinout M2128-20 200 150 50 â  Two Line Control, CE Controls PowerDown, OE Controls Output , power-down feature cuts power consumption when the device is disabled. The 24-pin industry standard pinout , . Ds d2 d2 C 13(11) (15)17 â¡ (14)18 J D, GND G ND C d4 14(12) (13)15 J A4 A5 D4 A« DS D# Dr Aio OE WE CE T ï Y Figure 1. Logic -
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M2818

F100K

Abstract: SY100S314 single-ended use s More than twice as fast as Fairchild s Function and pinout compatible with Fairchild F100K , 20 19 18 Da Dd 2 3 17 16 Da Oa 15 14 Oa Ob 13 7 8 9 10 11 12 Ob , View PLCC J28-1 Dd De Db 12 13 14 15 16 17 18 Dd Db Db Db VEE VEES VBB
Micrel Semiconductor
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SY100S314 SY100S314FC SY100S314JC SY100S314JCTR F24-1

LS373

Abstract: 74LS573 . definitions 573 CONNECTION DIAGRAM PINOUT A ÃE [7 2SI Vcc Do [2 Io» D,U 18lo1 D2 [T 13 02 Da [7 , INI 16 15 14 13 I 12 Vcc = Pin 20 PIN NAMES DESCRIPTION 54/74LS (U.L.) HIGH/LOW Do â'"D7 LE , ) 3-State Latch Outputs 0.5/0.25 0.5/0.25 0.5/0.25 65/15 (25)/(7.5) 4-431 This Material Copyrighted
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LS373 74LS573PC 74LS573DC 74LS573FC 54LS573DM 54LS573FM 74LS573 74LS573 LATCH til 431 74LS573 "LATCH" 15J04 54LS/74LS573
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