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Part Manufacturer Description Datasheet BUY
SN74161N-10 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 visit Texas Instruments
SN74161D Texas Instruments Synchronous 4-bit binary counters 16-SOIC 0 to 70 visit Texas Instruments
SN74161J Texas Instruments Synchronous 4-bit binary counters 16-CDIP 0 to 70 visit Texas Instruments
SN74161N3 Texas Instruments Synchronous 4-bit binary counters 16-PDIP 0 to 70 visit Texas Instruments
SN74161N Texas Instruments Synchronous 4-bit binary counters 16-PDIP 0 to 70 visit Texas Instruments
SN74161J-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16 visit Texas Instruments

counter schematic diagram 74161

Catalog Datasheet MFG & Type PDF Document Tags

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 timer is 74161 counter % % register is an octal FF % ) END; Altera Corporation BEGIN % set up , Schematic capture w ith Mentor G raphics' N E T E D software A H D L supporting state machines, Boolean , Features LI General Description Mentor Graphics Schematic Capture EDIF Netlist Writer The , a rd w a re Figure 1. PLS-WS/HP Block Diagram Device Simulation Board Simulation - Shading , supports both schematic and text design entry options. Hierarchical schematic designs are entered with the
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multiplexor 74151

Abstract: counter schematic diagram 74161 System featuring hierarchical schematic capture, 7400 series symbol library, and timing simulation , 68 pin PGA. CONNECTION DIAGRAM 1- HI- 1- I/O I 60 ] I/o i/o: 11 _J 59 ] I , EPM5128 and EPM5127 are designed to replace large amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes only 3% of the 128 Macrocells available in the EPLD. Similarly, a 74151 8 to 1 , which supports hierarchical schematic entry, Boolean equation, and state machine design. The powerful
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multiplexor 74151 counter schematic diagram 74161 74151 PIN DIAGRAM Altera EPM5128 74151 74151 multiplexer EPIVI5128

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER Synchronous Decade Counter (0160) 42 18 74161 Synchronous 4-Bit Binary Counter (0161) 42 19 74162 Synchronous Decade Counter (0162) 42 20 74163 Synchronous 4-Bit Binary Counter (0163) 42 21 74164 8 , Divide-by-twelve Counter (0092) 23 5 7493 4-Bit Binary Counter (0093) 18 6 7494 4-Bit Shift Register (0094) 32 , 8-Bit Shift Register (0166) 52 24 74169 Synchronous 4-Bit Binary Up/Down Counter (0169) 51 25 , Counter with Down/Up Mode Control (0190) 52 29 74191 Synchronous 4-Bit Binary Up/Down Counter with Down
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74139 demultiplexer 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 MSM60300 MSM60700 MSM61000 MSMC0300

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer Divide-by-twelve Counter 4-Bit Binary Counter 4-Bit Shift Register 4-Bit Shift Register 3-Line to 8-Line Decoder , cont'd No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 74157 74158 74160 74161 74162 74163 74164 74165 , Quadruple 2-line to 1-line Data Selector/Multiplexer Synchronous Decade Counter Synchronous 4-Bit Binary Counter Synchronous Decade Counter Synchronous 4-Bit Binary Counter 8-Bit Parallel-Out Serial Shift Register Parallel-LOAD 8-Bit Shift Register 8-Bit Shift Register Synchronous 4-Bit Binary Up/Down Counter
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3-8 decoder 74138 CI 74151 JK Shift Register 74195 Multiplexer 74153 CI 74138 74280 parity generator manual

vhdl code for 4 bit ripple COUNTER

Abstract: design excess 3 counter using 74161 . Four 74161 counters are used to construct this counter as shown in Figure 12. The WR_WCNT sig , process by featuring erview cockpit which appears when you invoke both schematic and VHDL design , Using ViewGen generates schematic symbols from sche matic drawing. The resulting symbol could then be instantiated on other, higherlevel schematics. All designs (schematic and VHDL) are converted to VHDL, so for designs containing schematics, Expt1076 is run to translate the viewdraw schematic into
Cypress Semiconductor
Original
74XXX vhdl code for 4 bit ripple COUNTER design excess 3 counter using 74161 CONVERT E1 USES vhdl vhdl 74161 address generator logic vhdl code VHDL program to design 4 bit ripple counter EXPT1076 DOUT00-DOUT15 CY7C383A

74151 waveform

Abstract: 5128LC MSI logic. For example, a 74161 counter 0.65micron shrinks of the original 0.8mi utilizes only 3% of , . Warp3 is a sophisticated CAE ferent 7400 series part numbers currently tool that includes schematic , interface Schematic capture (ViewDrawt) Max Family Members Feature Macrocells MAX FlipFlops MAX , array is the I/O control block of the LAB. Figure 6 shows the I/O block diagram. The threestate buffer , C3402 ARRAY Figure 2. T ypical LAB Block Diagram Figure 3. 7C344 LAB Block Diagram 3
Cypress Semiconductor
Original
CY7C340 CY7C342B 7C341-30JC 74151 waveform 5128LC 7C340 7C340 programming eprom programmer CY7C34XB AGC-15 5192AGC-20 5192AJC-15
Abstract: it ideal for replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter , '" Schematic capture (ViewDraw) LAB is a group of additional product terms called expander product terms , control block of the LAB. Figure 6 shows the I/O block diagram. The three-state buffer is controlled by , macrocell within the PROGRAMM ABLE IN T ERC O N N EC T ARRAY Figure 2. Typical LAB Block Diagram Figure 3. 7C344 LAB Block Diagram 4 -1 4 7 PLDs Traditionally, PLDs have been divided into -
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CY7C34X CY3340 CY7C341 CY3340F CY3342 CY7C342

16CUDSLR

Abstract: 7474 D flip flop free ] flag 74161; % timer is 74161 counter % DFF; % register is an octal FF % NODE; BEGIN % set up , U S . Figure 1. MAX+PLUS Block Diagram MAX+PLUS Design Processing (Compiler) T h e P L D S-M , "add_cmp" DEVICE IS "EPM5128-2"; FUNCTION 74161 (LDN,A,B,C ,D,ENT,ENP,CLRN,CLK) RETURNS ( QA,QB,QC,QD ,RCO , [ ] != 0); done = f1ag; % connect inputs for timer (74161) % timer.enp = cmpen & flag; timer.elk = clock , List of MAX+PLUS Macrofunctions Type Adder ALU AND -O R Gate Com parator Code Converter Counter
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16CUDSLR 7474 D flip flop free alu 74382 sn 74373 pin diagram of ic 74190 ALU IC 74381

IC TTL 7400 diagram and truth table

Abstract: ideal for replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes , machines â'" Hierarchical schematic capture with 7400 series TTL and custom Macrofunctions â'" State , processing. A hierarchical schematic entry mecha­ nism is used to capture the design. State Machine, T , schematic capture. The powerful De­ sign Processor performs minimization and logic synthesis, then , locator shows exactly where the error occurred by popping the designer back into the schematic at the
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IC TTL 7400 diagram and truth table

74151

Abstract: 74151 pin connection replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes only 3% of the 128 , ® - VHDL synthesis - ViewLogic graphical user interface - Schematic capture (ViewDrawTM) - VHDL , that includes schematic capture (ViewDraw) and timing simulation (ViewSim) in addition to VHDL , AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A C340­3 C340­2 Figure 2. Typical LAB Block Diagram Figure 3. 7C344 LAB Block Diagram 3 CY7C340 EPLD Family 16 MACROCELL FEEDBACKS (32 FOR 7C344) PROGRAMMABLE
Cypress Semiconductor
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5192JM 74151 pin connection C3406 programmer EPLD 22v10 PALC22V10B 5128AJC 7C342B 5192GC 7C341 5128ALC

7486 XOR GATE pin configuration

Abstract: 7486 XOR GATE Beginner's Guide to ispLSI and pLSI Using pDS Software Figure 6. Counter Schematic Diagram D Q , (CE) Pin. · A Synchronous Reset Pin. Figure 6 shows the schematic diagram and Figure 7 shows , . The macro element used to do this is named CBU24. The schematic diagram is shown in Figure 9. 1 , this, the complete design of a simple four-bit counter is discussed from specification through , windows displays a graphical representation of the ispLSI 1032E logic diagram. This window is called the
Lattice Semiconductor
Original
7486 XOR GATE pin configuration 7486 XOR GATE counter schematic diagram 7486 XNOR GATE 7408 half and full adder 7486 full adder circuit diagram RS-232

IC 7400 diagram and truth table

Abstract: IC TTL 7400 diagram and truth table architecture makes it ideal for replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter , the CY7C340 fam ily architecture, providing efficient design processing. A hierarchical schematic , mechanisms are also sup ported, and may be mixed with schematic capture. T he powerful design processor , ping the designer back into the schematic at tile exact error location. General Description The , logic and input latches. PROGRAMMABLE NTEBCONNECT ARRAY Figure 2. typical LAB Block Diagram
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IC 7400 diagram and truth table IC 74151 diagram and truth table programmer manual EPLD cypress pin diagram of 74151 TTL IC rs flip-flop IC 7400 programming manual EPLD 20-MH 20-MB 44-MB CY3200 CY3201 CY3202

epm5032dc

Abstract: 5128A m akes it ideal for replacing large am ounts of T T L SSI and M SI logic. For exam ple, a 74161 counter utilizes only 3% o f the 128 m acrocells available in the CY7C342. Similarly, a 74151 8-to -l m , on PC and Sun platforms Warp3 TM - VHDL synthesis - ViewLogic graphical user interface - Schematic , acrocell array is the I/O control block o f the LAB. Figure 6 shows the I/O block diagram . T he th , buffer com es from a m acrocell w ithin the ARRAY Figure 2. Typical LAB Block Diagram Figure 3
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5130Q epm5032dc 5128A rc 74151 7C340 epld 342B 7C34X 344-20H 344-25H 344-25JC 344-20JC 344-15JC

truth table for ic 74138

Abstract: 16CUDSLR ation. Figure 1. A+PLUS Block Diagram A+PLUS Simulation Virtual Logic Analyzer (V LA) Functional , table design entry. LogiCaps Schematic Capture Logic schem atics are created w ith LogiCaps, w hich , . Partial List of A+PLUS Macrofunctions Type Adder Com parator Converter Counter 7480, 7482, 7483, 74183, 8FADD 7485, 74158, 74518, 8MCOMP 74184, 74185 7493, 74160, 74161, 74162, 74163, 74190, 74191, 74393 , design files or processed directly w ith the A DP to generate a JEDEC File (.JED). Figure 2. Schematic
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truth table for ic 74138 ALU IC 74183 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A
Abstract: exam ple, a 74161 counter utilizes only 3% o f th e 128 m acrocells available in th e CY7C342 , platforms â'¢ Warp3w â'" VHDL synthesis â'" ViewLogic graphical user interface â'" Schematic , block diagram . T h e three-state buffer is controlled by a m acrocell pro d u ct te rm and the drives , 1Tb CY7C340 EPLD Family CYPRESS TERMS (64 FOR 7C344) Figure 4. Macrocell Block Diagram , Diagram Figure 5. Expander Product Terms 3 -4 ESB'ibbE DD13Gb7 DEE â  CY7C340 EPLD Family -
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344-15H 344-20P 344-15P 7C343 343-25H 343-30H

5192LC

Abstract: 5128LC amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes only 3% of the 128 macrocells , - VHDL synthesis - V i e w L o g i c g r a p h i c a l u s e r i nt e r f a c e - Schematic , the macrocell array is the I/O control block of the LAB. Figure 6 shows the I/O block diagram . The , environment. Warp3 fea tures schematic capture (ViewDrawTM ), VHDL waveform sim ulation (ViewSimTM ), a VHDL
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5192LC 25128LI 5130LC 344-25PC 344-20PC 344-15PC 7C344-- 343-35H 343-35HI

rc 74151

Abstract: 7C340 74161 counter utilizes only 3% o f th e 128 m acrocells available in th e CY7C342. Similarly, a 74151 8 , synthesis - ViewLogic graphical user interface - Schematic capture (ViewDraw) - VHDL simulation (ViewSim , block diagram . T h e th ree-state buffer is controlled by a m acrocell pro d u ct term and the drives , ) Figure 4. Macrocell Block Diagram M ACR O CELL P -T E R M S -O o o- £> o - o EXPANDER P -T E R M S Figure S. Expander Product Terms Figure 6. I/O Block Diagram 4 -1 4 8
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IC 7400 SERIES book CY3342F 3342R CY3344 CY33435 7C342

74194 ring counter

Abstract: grid tie inverter schematic diagram support schematic capture and simulation on popular CAE workstations. BLOCK DIAGRAM /OD OO OO DQQ I/O , tools let users produce a complete design, from schematic capture through device customization, on an , define CLBs and their interconnecting networks by automatic translation from a schematic capture logic diagram or, optionally, by installing library or user macros. Each CLB has a combinational logic section , the networks connecting the logic blocks and lOBs. The next figure shows a modulo 8 binary counter
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74194 ring counter grid tie inverter schematic diagram 74299 universal shift register CI 74241 DN 74352 grid tie inverter schematics

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC Boolean gates to complex counter bit slices and arithmetic functions. This makes the SCxD4 series an Ideal , multiplexer (74LS150) 36 M151C 8 to 1 gated multiplexer (74LS151) 19 CB4C 4 bit binary up counter, fast, sync. CLR 52 CB41 4 bit up counter, expandable with CLR 59 CUD42 4 bit up/down counter, expandable with async. LOAD and CLR 87 M160C Synchronous 4 bit BCD counter (74LS160) 69 M161C Synchronous 4 bit binary counter (74LS161) 63 M162C Synchronous 4 bit BCD counter (74LS162) 64 M163C Synchronous 4 bit
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74ls82 74245 BIDIRECTIONAL BUFFER IC ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC TC140G SC12D4

AMD K6

Abstract: 74147 decimal to binary encoder interconnecting networks by automatic translation from a schematic capture logic diagram or, optionally, by , array design tools. AMDâ'™s development tools let users produce a complete design, from schematic , interface software are also available to support schematic capture and simulation on popular CAE , easily BLOCK DIAGRAM g /E x u j u u u u u E I/O Blocks / + , next figure shows a modulo 8 binary counter with parallel enable. It uses one CLB of each type
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AMD K6 74147 decimal to binary encoder C10BCPRD C10BCRD C10BPRD C10JCR C12JCR C16BARD
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