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83056AGI-01LFT Integrated Device Technology Inc TSSOP-20, Reel visit Integrated Device Technology
83052AGI-01LF Integrated Device Technology Inc TSSOP-16, Tube visit Integrated Device Technology
83058AGILFT Integrated Device Technology Inc TSSOP-16, Reel visit Integrated Device Technology
83058AGILF Integrated Device Technology Inc TSSOP-16, Tube visit Integrated Device Technology
83056AGILF Integrated Device Technology Inc TSSOP-16, Tube visit Integrated Device Technology
83056AGI-01LF Integrated Device Technology Inc TSSOP-20, Tube visit Integrated Device Technology

ce 65 s encoder

Catalog Datasheet MFG & Type PDF Document Tags

faulhaber dc motor

Abstract: Faulhaber CE CE CE SC 2804 S SC 2804 S SC 2402 P SC 2402 P SC 2804 S SC 2402 P BL DC BL DC BL , 0,018 3 S C 1801 S 4,0 . 18 1,8 . 18 1 2 0,018 3 S C 2402 P 5 . 24 0 . 24 2 4 0,03 5 S C 2804 S 5 . 28 0 . 28 4 8 0,03 5 V DC V DC A A A - 4 , encoder Scanning rate Resolution of encoder with DC motors 500 . 100 0002) 100 . 30 0002) 500 65 535 rpm rpm µs inc./rev. Operating temperature range Storage temperature 0 . + 60
Faulhaber
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ce 65 s encoder

Abstract: 0.1 -1 .0 -0 .5 0 0.5 1.0 D ista n ce X (mm) (S h iftin g encoder) SHARP D istance X (mm) (S , rl.O - 0 .5 0 0.5 1.0 D ista n ce Y (mm) (S hifting encoder) -1 .0 -0 .5 0 0.5 1.0 D istan ce Y (mm) (S h iftin g encoder) Fig. 11 Duty Ratio vs. Distance (Z direction) V cc= 5V I f = 30m A f= 1 , - -0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 D istan ce Z (mm) (S hifting encoder) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 D ista n ce Z (mm) (S h iftin g encoder
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faulhaber dc motor

Abstract: faulhaber encoder 18 1 2 0,018 3 S C 1801 S 4,0 . 18 1,8 . 18 1 2 0,018 3 S C 2402 P 5 . 24 0 . 24 2 4 0,03 5 S C 2804 S 5 . 28 0 . 28 4 8 0,03 5 V DC V DC A A A , Drehzahlbereich DC-Motoren mit Encoder Regler Abtastrate Auflösung des Encoders bei DC-Motoren 500 . 100 0002) 100 . 30 0002) 500 65 535 rpm rpm µs Inc./Umdr. Betriebstemperaturbereich , . Ausgangsstrom bei 5 V DC SC 1801 .» ICC = 25 mA SC 2402 P » ICC = 20 mA SC 2804 S » ICC = 30 mA
Faulhaber
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L2101

Abstract: SAA7125 o > < o o > x o S g o- Q O (M > > > O â  ce ce Q ' O Ã" I- ' ce < co o â  co < o â , -z XI Ã' CO xi Ã' S CD Q 3 ^ o -Q i= Ã' § XI Ã' CE O co m co CD LU CE o o CE , Encoder (ECO-DENC) SAA7124; SAA7125 O â  ce g Q ' O à I- ' ce < CO o â  CO , Encoder (ECO-DENC) SAA7124; SAA7125 < ko ox o o o > Cvj > O â  ce g Q ' O à I- ' ce < co o , Encoder (ECO-DENC) SAA7124; SAA7125 a> 1- o o LU o co (/) Q < co LU > co > CE H R M M M >v
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L2101 SAA7125WP digital cvbs pattern SAAA7111 LQFP64 PLCC84 QFP52 QFP100 QFP160
Abstract: 69 68 67 S P D S EL R ANG E SE L RFEN TX F U LL CE TX H A LF RXEN T X C LK RXRST V SS DLB VLTN TXBISTEN RXCLK TXH A LT R XFULL v s s 10 11 12 66 65 RXSC/D V DD V SS V DD REFCLK v s s , and 5B/6B encoder/decoder may be by passed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is , · San Jose · CA 95134 · 408-943-2600 May 4, 1999 ,s CYPRESS PRELIMINARY -
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CY7C9689 CY7C9689-AI 100-L
Abstract: rising edge of CE CLK. RSE_OUT (Reed-Solomon Encoder Output) This signal outputs the completed data , S i GEC PLESS EY S E M I C O N D U C T O R S DS3590-3.2 MA1916 RADIATION HARD REED-SOLOMON & CONVOLUTION ENCODER The purpose of the MA1916 is to encode serial data to allow error , contains two encoding elements. The Reed-Solomon encoder appends a checksum to a block of data, guarding against burst errors in a message. The convolution encoder continuously creates two code bits for each -
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023R6
Abstract: 65 R X S C /D REFCLK 12 64 V DD V SS 13 63 V SS V DD 14 62 V , Encoder Modelé TX DATA Bus Input Bit Encoded 8-bit Character S tre a m ^ Pre-encoded 10 , FIFO, and presented to the destination host system. The integrated 4B/5B and 5B/6B encoder/decoder , parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is converted to and , '¢ CA 95134 â'¢ 408-943-2600 May 4, 1999 ,S CYPRESS CY7C9689 PRELIMINARY CY7C9689 -
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AM7968/7969 CY7C9689-AC

CY7C42X5

Abstract: CY7C9689 RXHALF TXSC/D RXEMPTY TXDATA[0] RXCMD[1] RXMODE[1] RXMODE[0] lu Q CE < O lu ^ M S gc Q Z) > O < < w w w w > > g g 5 5 lu râ'" «â â'žVU s S S, 5 q Å" H) X > > o en 100 99 98 97 96 95 1 94 93 , and 5B/6B encoder/decoder may be bypassed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is , 67 10 66 11 12 13 CY7C9689 65 64 63 14 62 15 61 16 60 17 18 59 58 19 57 20 56 21 55
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CY7C42X5 4b/5b encoder

CY7C9689-AC

Abstract: simple LFSR Serializer Data Transmit Encoder 4B/5B, 5B/6B Status Serial Link Transmit Data Control , encoder/decoder may be bypassed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is , additional glue-logic. Receive FIFO · · · · · Encoder 4B/5B, 5B/6B · · · The receive , Output Register Input Register Flags Mode Receive FIFO Flags Transmit FIFO CONTROL CE
Cypress Semiconductor
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simple LFSR 98 UTA ING 100-P

td10 IC

Abstract: 485IM fü HARRIS S E M I C O N D U C T O R HS-15530RH Radiation Hardened CMOS Manchester Encoder-Decoder Pinout 24 PIN DIP C A S E O U T LIN E D-3, CO N FIG U R A TIO N 1 T O P VIEW VALID WORD D e ce m b e r 1992 Features · Functional Total Dose 1 x 10s RAD(SI) · Latch-Up Free to 5 x 101 1 RAD(SI)/s · Support of MIL-STD-1553 · Low Operating Power 50mW at 5V · 1.0 Megabit/s Data Rate · Sync , Military Temperature Range -55°C to +125°C [7 [7 m ] vdd ENCODER SHIFT CLK [ £ TAKE DATA j i
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td10 IC 485IM HS-15530 MILSTD-1553 HS-1553

viterbi convolution

Abstract: Convolutional Encoder (CE), Phase Ambiguity Resolution Encoder (PARE), Symbol Puncture Logic (PL) and the Data Valid , Control Logic (CL) DIN0 Rate 1/2, 1/3 Convolutional Encoder (CE) Rate 2/3, 3/4, 5/6, 7/8 , changes. The differential encoder block may be bypassed if desired. CE: CONVOLUTIONAL ENCODER BLOCK , CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a
Amphion Semiconductor
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CS3410 16-PSK DS3310 viterbi convolution Convolutional Encoder 16psk convolution encoder CS3310AA IESS-308/

servomotor

Abstract: parvex encoder 64 7,6 8,5 17,5 0,167 -5 2 MC 13 S CE 1,2 3000 375 MC 17 H CE , 60 9,7 MC 19 S CE 5,1 3000 1600 171 11,1 24,4 51 0,488 1,6 100 , 170 13 50 53 0,506 0,9 230 8 25 37 40 75 17 MC 23 S CE 10 , 17 MC 24 P Units MC 23 S (2) -5 2 CE 7,3 3000 2300 136 18,9 84 , exception of model MC27P) are marked «CE» in accordance with French directive no. 73/23/CEE dated the 19th
Parvex SAS
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MC13S servomotor parvex encoder TBN 420 SERVOMOTORS F9m4 24v dc servomotor DIN42955 3452GB F-21007

16psk block diagram

Abstract: Implementation of convolutional encoder (CE), Phase Ambiguity Resolution Encoder (PARE), Symbol Puncture Logic (PL) and the Data Valid , Control Logic (CL) DIN0 Rate 1/2, 1/3 Convolutional Encoder (CE) Rate 2/3, 3/4, 5/6, 7/8 , changes. The differential encoder block may be bypassed if desired. CE: CONVOLUTIONAL ENCODER BLOCK , CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a
Amphion Semiconductor
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16psk block diagram Implementation of convolutional encoder differential encoder for psk Convolutional CS3310TK CS3310XE DS3310-

16 line to 4 line coder multiplexer

Abstract: Frame structure for Multiplexing of four E1 streams into E2 stream ppm for the 34368 kbit/s operation as per ITU G.703. 44 MHNRZI HDB3 Encoder #5 NRZ Input , 34368 kbit/s operation as per ITU G.703. 82 DLNRZI1 HDB3 Encoder #1 NRZ Data Input. HDB3 , ±30 ppm for the 8448 kbit/s operation as per ITU G.703. 60 CE Chip Enable. A high signal , /s) E2/E3 Multiplexer (8/34 Mbit/s) E1/E3 Multiplexer (2/34 Mbit/s) Digital Loop Carrier (DLC , Of Signal (LOS) HDB3 Encoder #[1:4] 8 4 HDB3 Pos/Neg Data Output Pairs Multiplexer 4
Intel
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LXT6234 16 line to 4 line coder multiplexer Frame structure for Multiplexing of four E1 streams into E2 stream LXT6234QE LEVEL ONE COMMUNICATIONS HDB3 Frame structure for Multiplexing of four E2 streams into E3 stream LXT305/332 PDS-6234-7/99-2

circuit diagram of 64-1 multiplexer

Abstract: 16 line to 4 line coder multiplexer 34368 kbit/s operation as per ITU G.703. 44 MHNRZI HDB3 Encoder #5 NRZ Input. HDB3 Encoder #5 , /s) E2/E3 Multiplexer (8/34 Mbit/s) E1/E3 Multiplexer (2/34 Mbit/s) Digital Loop Carrier (DLC , NRZ Data Outputs HDB3 Encoder #[1:4] 8 4 HDB3 Pos/Neg Data Output Pairs Multiplexer 4 , ] Elastic Store 4 HDB3 Encoder Refer to www.level1.com for most current information. 4 4 4 , DESCRIPTION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
Level One Communications
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SXT6234 circuit diagram of 64-1 multiplexer E1 HDB3 SXT6234QE multiplexing demultiplexing e2 500E D-85774
Abstract: FIFO, and presented to the destination host system. The integrated 4B/5B and 5B/6B encoder/decoder , parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is converted to and , . 14 Transmit FIFO . 16 Encoder Block , Register Flags Mode Receive FIFO Flags Transmit FIFO CONTROL CE TXEN RXEN TXHALT TXRST , MUX Pipeline Register Receive Control State Machine BIST LFSR 4B/5B, 5B/6B Encoder Cypress Semiconductor
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CY7C9689A 200-MB

MC145034DW

Abstract: decoders. The MC145033 functions as both an encoder and a decoder. The encoders convert parallel address , encoder/decoder has a status output. The status pin, when high, indicates the device is encoding. During , Voltage Range: 2 to 6 V Operating Temperature Range: -4 0 to + 85°C MC145031 Encoder/MC 145032 Decoder Pair: 13 Address and 4 Data Lines or 17 Address Lines MC145033 Encoder/Decoder: 15 Address Lines MC145034 Encoder/MC145035 Decoder Pair: 13 Address and 4 Data Lines or 17 Address Lines Address/Data Inputs
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MC145034DW MC145031/34 MC145032/35 MC145031/2 MC145034/5 MC1450 MC145031/32/33

MP 3389 EF

Abstract: xo 405 me CH7203 CHRONTEL MPEG to TV Encoder with 16-bit Input Features Description · · · · · The CH7203 video encoder integrates a dual PLL clock generator and a digital NTSC/PAL video encoder , operating the CH7203 in master mode. The fully digital video encoder is pin-programmable to generate , sleep mode which turns the encoder off while leaving both PLL's running. · · · · · · · · · , -pin PLCC 5V single-supply operation MOD 0 MOD 1 FS C RSEN* CR S VDD AVDD R SET
Chrontel
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PAL-60 CH7203-V MP 3389 EF xo 405 me MP 3389 SW 2603 NCE variable tuning capacitor PAL01

E1 HDB3

Abstract: 16 line to 4 line coder multiplexer the 8448 kbit/s operation as per ITU G.703. 60 CE Chip Enable. A high signal forces all , .742 recommendation for multi plexi ng four E1 channel s into an E2 frame; and the G.751 recommendation for mul , 4 5 6 7 8 Applications 9 NOTE · E1/E2 Multiplexer (2/8 Mbit/s) · E2/E3 Multiplexer (8/34 Mbit/s) · E1/E3 Multiplexer (2/34 Mbit/s) The SXT6234 will not be avai lable in India , AUXI[1:4] 14 MSYNC 15 MHMUXC DLNRZI [1:4] DLCI[1:4] L1 HDB3 Encoder #[1:4
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HDB3 AMI ENCODER DECODER HDB3 to nrz micron lable information E1 AMI HDB3 decoder E2 hdb3 HDB3 decoder

MP 3389 EF

Abstract: xo 405 me CH7202 CHRONTEL MPEG to TV Encoder with 8-bit Input Features Description · Outputs NTSC, PAL (B,D,G,H,I) and PAL-M (NTSCJ or PAL-60 available as options) The CH7202 video encoder integrates a dual PLL clock generator and a digital NTSC/PAL video encoder. By generating all essential , which enable operating the CH7202 in master mode. The fully digital video encoder is pin-programmable , logic selectable sleep mode which turns the encoder off while leaving both PLL's running. · 8
Chrontel
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Hsync Vsync decoder AN06 AN-19 CCIR601 CCIR656 HSYNC, VSYNC, DE, input, output digital tv
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