500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
TMS664814-12DGE Texas Instruments 8MX8 CACHE DRAM, 8ns, PDSO54 visit Texas Instruments
TMS664814-10DGER Texas Instruments 8MX8 CACHE DRAM, 7.5ns, PDSO54, PLASTIC, TSOP2-54 visit Texas Instruments
TMS664814-12DGER Texas Instruments 8MX8 CACHE DRAM, 8ns, PDSO54, PLASTIC, TSOP2-54 visit Texas Instruments
CP3SP33SMSX/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 224-NFBGA -40 to 85 visit Texas Instruments
CP3SP33SMR/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 144-NFBGA -40 to 85 visit Texas Instruments
CP3SP33SMRX/NOPB Texas Instruments Processor with Cache, DSP,Bluetooth, USB, Dual CAN Interface 144-NFBGA -40 to 85 visit Texas Instruments

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : CACHE-4U-5 Supplier : Chelsio Communications Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : MR CACHECADE OCS Supplier : Broadcom Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Shipping cost not included. Currency conversions are estimated. 

cache

Catalog Datasheet MFG & Type PDF Document Tags

dlock

Abstract: EE-16 core unlocked cache. Any access that misses in the cache is treated as a cacheinhibited access. Cache entries , code performing the cache locking. This area of memory must be cache-inhibited for instruction cache , 0x00000002 0xFFF00022 deÞnes a cache-inhibited memory area used for instruction cache locking, and corresponds to a WIMG of 0b0100. Cache-inhibited memory is not a requirement for data cache locking. A , invalidation of the instruction and data caches. 1.3.1 Invalidating the Instruction Cache Invalidation of
Motorola
Original
MPC8240 dlock EE-16 core FE01 MPC755 AN2129/D MPC603

what is cache memory

Abstract: pentium family developer manual 241428 the video region of main memory is not cacheable. 3 A cache page is not associated with a memory , cost of implementing large caches. Therefore, this type of cache is usually only used for small caches , , while the second part explains how the Pentium Processor implements cache. A simplified model of a , that over 90% of 1 the memory accesses occurs out of the high speed cache. So now the question, why , 2-1 shows a simplified diagram of a system with cache. In this system, every time the CPU performs a
Intel
Original
what is cache memory pentium family developer manual 241428 block diagram of pentium PROCESSOR basic architecture of Pentium 5 Processors cache

block diagram 8085 microprocessor based traffic control system

Abstract: 8085 microprocessor based traffic control system some A Cache Primer, Rev. 1 8 Freescale Semiconductor Multi-Level Caches space in cache. In , shows a diagram of the e500 core and caches. A Cache Primer, Rev. 1 10 Freescale Semiconductor , : The status bits are different in the data and instruction caches.The data cache supports three-state , a Cache? A cache is commonly defined as a secure place of storage, mainly for preserving , . Contents What is a Cache? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Associativity . .
Freescale Semiconductor
Original
AN2663 block diagram 8085 microprocessor based traffic control system 8085 microprocessor based traffic control system 8085 microprocessor simulator 8085 microprocessor ram 4k E500CORERM 8085 based traffic control system

FE01

Abstract: MPC755 that contains the code performing the cache locking. This area of memory must be cache-inhibited for , instruction cache locking, and corresponds to a WIMG of 0b0100. Cache-inhibited memory is not a requirement , the Cache This section describes the invalidation of the instruction and data caches. 1.3.1 , off, cache has been flushed, # the MMU is on, and we are executing in a cache-inhibited # location , cache or for individual ways within the cache. Entire Cache LockingÑWhen an entire cache is locked
Motorola
Original

stream register cache coherency snoop filter

Abstract: RISCwatch contains separate instruction and data caches, along with a unified L2 cache. In order to use the caches , . Assuming the caches are in a disabled state, use the following code sequence to enable the cache. ! ! , Any access that misses in the cache is treated as a cache-inhibited access (i.e. the access attempt , or more of the caches.The code samples presented here are written for the 750GX processor, but , the 750GX and 750FX have two separate 32KB instruction and data caches. The two caches in each of
IBM
Original
750FXTM stream register cache coherency snoop filter RISCwatch PPC750GX The PowerPC Microprocessor Family 750GX-750FX 750GX/FX 750GXTM 750CX 512KB

MPC823

Abstract: undefined. · Read Miss-Data is read from memory, but not placed in the cache. The cache's status is unaffected. · Write Miss-Data is written through to memory, but not placed in the cache. The cache's , are: · Read Miss-Data is read from memory, but not placed in the cache. The cache's status is , cache-inhibit operation. 10 Each line of the data cache can be independently locked by writing the LOCK , SECTION 10 DATA CACHE The MPC823 data cache is a 1K two-way, set-associative cache. It is
Motorola
Original

E300

Abstract: AN2129 Any access that misses in the cache is treated as a cache-inhibited access. Cache entries that are , cache-inhibited for instruction cache locking. · A 256 Mbyte block of memory that contains the data to lock (not , cache locking and corresponds to a WIMG of 0b0100. Cache-inhibited memory is not a requirement for data , data caches. 5.1 Instruction Cache The entire instruction cache for the e300 microprocessor is , interrupts are turned off, cache is flushed, # the MMU is on, and we are executing in a cache-inhibited #
Freescale Semiconductor
Original
AN2129 MPC8349E E300 MPCFPE32B MPC603E-

SuperSPARC

Abstract: MIPS R4000 , 256 Kbytes or 512 Kbytes of secondary cache. Direct-mapped and two-way set associative caches are , processors include on-chip caches. However, it is their off-chip secondary caches that allow these machines , is where any similarity between their secondary caches ends. The secondary cache structures differ in the type, size and speed of SRAM that can be employed in the secondary cache. The organization of , secondary caches: reduction of the primary cache miss penalty. Since the dominant goal of a secondary cache
IXYS
Original
R4000 SuperSPARC MIPS R4000 evolution of intel microprocessor cache R4000SC 486DX AN-01 R10000 PDM44039 390Z55

BX80532KE2667D

Abstract: BX80546KG3600FA pins/90nm/2MB L2 cache/800 MHz Bus/supports uni and dual processing) Active - BX80546KG3600FA , L2 cache/800 MHz Bus/supports uni and dual processing) Active - BX80546KG3600EA Passive - BX80546KG3600EP RK80546KG1041M 1U - BX80546KG3600EU 3.40 GHz (PGA package/604 pins/90nm/2MB L2 cache/800 MHz , RK80546KG0962M 1U - BX80546KG3400FU 3.40 GHz (PGA package/604 pins/90nm/1MB L2 cache/800 MHz Bus/supports , BX80546KG3400EU 3.20 GHz (PGA package/604 pins/90nm/2MB L2 cache/800 MHz Bus/supports uni and dual
Intel
Original
RK80546KG1042M BX80532KE2667D BX80532KE3066E BX80546KG2800EP RN80528KC017G0K PGA PACKAGE RK80532KE0882M BX80546KG3600FP BX80546KG3600FU BX80546KG3400FA BX80546KG3400FP RN80532KC0492M

TAG126

Abstract: MPC821 data cache is a 4-kbyte, two-way set associative physically addressed cache. The caches have 16 , generated. 10.5.3 Data Cache-Inhibited Accesses If the cache access is to a page which has the cache , to cache-inhibit operation. 10.6.3 Data Cache Locking Each line of the data cache may be , cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are , invalid, modified-valid and unmodified-valid states of the data cache. The cache coherency in a
Motorola
Original
MPC821 TAG126

M68060

Abstract: MC68040 line-by-line basis. Only burst mode accesses that successfully read four long words can be cached. A cache line , branch prediction strategy. 1 = The on-chip branch cache is enabled. Branches are cached. A predicted , , for either or both instruction and data caches. CINV allows selective invalidation of cache entries , cache, and the push buffer contents are written to external memory. 5.4.2 Cache-Inhibited Accesses , , then the access is cache inhibited. The caching operation is identical for both cache-inhibited modes
-
OCR Scan
MC68060 M68060 MC68040 MOVE16

cache controller

Abstract: 486DX2 QL12x16­PL84C pASIC QL12x16­PL84C pASIC CACHE_CTL TAG_CTL (Cache Control) (Tag Control) CACHE_CMP TAGSLRU (Cache Compare) (Least Recently Used Tag Marker) TAGSMAIN (Tags Main Sequence , lockout memory areas that dynamically change and are not cacheable. The cache controller design does not , the interaction of the i486 CPU and the cache. The next level down in the hierarchy is the `CACHE_Q , performance is through a large, external data and instruction cache. This versatile cache closely matches the
QuickLogic
Original
486DX2 cache controller i486 DX2 486DX2* circuits cache ram 64k x 8 cpu schematic 1024K

IBM processor

Abstract: PPC401 out of the processor's instruction and data caches. This application note examines these cache , address is marked as cacheable, the block is read from main storage into the data cache. icbt , corresponding address from the data cache and invalidates it in the instruction caches. By using this sequence , frequently accessed items in an on-chip cache memory. Typically, caches greatly increase performance while , Processors and Cores employ separate instruction and data caches. Separate caches provide a performance
IBM
Original
IBM processor PPC401 PPC40x PPC405 PPC401GF PPC40

stream register cache coherency

Abstract: AN3544 a portion of main memory that is also cached. In this case the cache has stale data. · Adjacent , resides in a cache enabled area and matches an address within the cache. If the address is cacheable and , indicator of a cache coherency problem. When the processor writes data, caches respond in one of two ways , execution. Depending on how the caches are managed, PowerQUICCTM Data Cache Coherency, Rev. 0 Freescale , concerned) in cache. The core incorrectly fetches the data from cache (referred to as stale data), not the
Freescale Semiconductor
Original
AN3544 stream register cache coherency

TAG62

Abstract: MPC823 , there are two ways to inhibit the cache-using the MMU cache-inhibit attribute or the cache disable , to the Cache. · Performance Enhanced for Cache-Inhibited Regions by Fetching a Full Line to the , causes code from cache-inhibited regions to be left inside the cache and any reference to these regions will result in a cache hit. If a reference to a cache-inhibited region results in a cache hit, the , if they were from the cache-inhibited memory region. For more information on cache debug support
Motorola
Original
TAG62

ARM600

Abstract: ksp 13 replacement these as: CacheWords=4 CacheAssociativity=64 CacheBlocks=4 whereas ARM710 (8kB, 4-way set-associative) defines them as: CacheWords=8 CacheAssociativity=4 CacheBlocks=64 To reduce the sample cache's size from 8kB to 4kB, the number of sets in the cache could be halved: ARM7XX:CacheWords=4 , block: ARM710a:NoCoprocessorInterface ARM710a:CacheWords=4 ARM710a:CacheBlocks=128 ARM710a:ChipNumber=0x711 | | | | 7 ARM7XX:NoCoprocessorInterface ARM7XX:CacheWords=4 ARM7XX:CacheBlocks=128
Advanced RISC Machines
Original
ARM600 ksp 13 replacement n- 0051A 0051A ARM7 set associative aRm3

Cy7C601

Abstract: c5wg supports memory reflection. M R affects the status o f the M TAG cache tag bits. CM- Cache-mode bit (SCR , CE- Cache-enable bit (SC R (8) indicates w hether the virtual cache is enabled or not. This bit is , signals during CY7C601A normal write accesses, modified cache-line reads from the cache RAM, CY7C605A , clock. They are output signals during cache line loads into the cache RAM and modified cache-line reads , phys ical address translation, and provides control for a 64-Kbyte vir tual cache. As part o f a m
-
OCR Scan
CY7C605 Cy7C601 c5wg CY7C604A CY7C157A 7C601 CY7CC04A

DCFA

Abstract: FE01 contains the code performing the cache locking. This area of memory must be cache-inhibited for , instruction cache locking, and corresponds to a WIMG of 0b0100. Cache-inhibited memory is not a requirement , Invalidating the Cache This section describes the invalidation of the instruction and data caches. 1.3.1 , this bit invalidates the entire data cache. See Section 1.3.2, "Invalidating the Data Cache." SPD , either an entire cache or for individual ways within the cache. This document contains information on
Motorola
Original
MPC750 DCFA AN2071 AN2071/D

MPC860

Abstract: data cache is a 4-kbyte, two-way set associative physically addressed cache. The caches have 16 , is similar to cache-inhibit operation. 10.6.3 Data Cache Locking Each line of the data cache may , cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are , invalid, modified-valid and unmodified-valid states of the data cache. The cache coherency in a , . 10.2 FEATURES The following is a list of the data cache's important features: 10 · 4
Motorola
Original
MPC860

mips r5000

Abstract: qed rm5200 expected values */ nop bne r2,r20,loop addi r2,r2,CACHELINE_SIZE /* goto next cache line , , also supports external cache. This paper is applicable to all four devices, but only the RM5271 will , external cache is a second level cache. For the RM7000 the external cache is a third level cache. The RM5271 provides an on-chip controller for external second level cache. The second level cache is a , transactions on the System Interface reference the external secondary cache. The external cache is not accessed
Quantum Effect Devices
Original
R5000 mips r5000 qed rm5200 GVT7164T18 MCM69T618 RM5200 RM5270 RM5271-AN1161010002
Showing first 20 results.