NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| MC68EC040FE40A | Freescale Semiconductor | 32-BIT W/ CACHE | 
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| MC68EC040RC25A | Freescale Semiconductor | 32-BIT W/ CACHE |
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| MC68EC040FE25A | Freescale Semiconductor | 32-BIT W/ CACHE |
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| MC68EC040BRC33A | Freescale Semiconductor | 32-BIT W/ CACHE |
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| MC68EC040FE20A | Freescale Semiconductor | 32-BIT W/ CACHE |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Speed (MHz) Voltages Max Temps (C) Wattage L1 Cache Size (KB) L1 Cache Count L2 Cache Size (KB) L2 Cache Count L3 Cache Size (KB) CMOS Socket F2 1800 1.35V/1.40V 55-69 62 W 128 1 256 1 0 90nm SOI AM2 ... | Original |
1 pages, |
SDA3400IAA3CW datasheet abstract |
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| Abstract: Microprocessor Includes: Integer Unit and Floating Point Controller, Floating Point Unit, Instruction Cache, Data Cache, Memory Management Unit, Bus Interface Unit. 330k Chapter 2 - TurboSPARC Architecture , 353k Chapter 3 - Memory Management Unit / Caches Includes: MMU Overview, MMU Address Translation , ) 1, Instruction Cache, Instruction Cache Tag RAM, Instruction Cache Flush, Instruction Caching Restrictions, Instruction Cache Snooping, Data Cache, Write Back Mode, Read Cycles in Write-Back Mode, Write ... | Original |
2 pages, |
37MB datasheet abstract |
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| Abstract: Fa c t S h e e t MPC2605FACT/D MPC2605FACT/D Rev. 3 Motor ola MPC2605 MPC2605 Integrated Secondar y Cache for , together all the functions required to implement a level 2 cache design integrated into one chip , look-aside cache with copy-back capability. It integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller. The 32K x 72 bit memory array is organized in a four-way set associative cache design. The 8K x 18 bit integrated tag is associated similarly. The four ways are ... | Original |
2 pages, |
MPC860 MPC8260 MPC740 MPC604 MPC2605 MPC2605FACT/D MPC2605FACT/D abstract |
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| Abstract: MPC2605FACT/D MPC2605FACT/D Fa c t S h e e t Motor ola MPC2605 MPC2605 Integrated Secondar y Cache for PowerPC TM , together all the functions required to implement a level 2 cache design integrated into one chip , look-aside cache with copy-back capability. It integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller. The 32K x 72 bit memory array is organized in a four-way set associative cache design. The 8K x 18 bit integrated tag is associated similarly. The four ways are ... | Original |
2 pages, |
MPC2605FACT/D MPC2605 MPC2605FACT/D abstract |
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| Abstract: , respectively. Implementation of the different cache sizes as well as the arbitration between the caches in a , Integrated Secondar y Cache for PowerPC TM Micr opr ocessor Applications A member of the PowerPC family of components, the MPC2605 MPC2605 groups together all the functions required to implement a level 2 cache design , Description The MPC2605 MPC2605 is a single chip 256 KByte integrated look-aside cache with copy-back capability. It integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller. The 32K ... | Original |
2 pages, |
MPC860 MPC8260 MPC740 MPC604 MPC2605 MPC2605FACT/D MPC2605FACT/D abstract |
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| Abstract: IDT INTRODUCES SECONDARY CACHE MODULES THAT OPTIMIZE CORE LOGIC SPECIFIC SOLUTIONS FOR 3.3V , ), the world's leading supplier of cache modules for the PentiumTM processor and all types of fast SRAM , production, these new low-profile, plug-in cache modules maximize the flexibility of cache options for the , (82C590 82C590), and OPTi (P54AWB P54AWB). "Our dominance in the cache module market combined with strong SRAM , the most optimized cache solution designed for each of the core logic chipset vendors supporting ... | Original |
2 pages, |
82430NX datasheet abstract |
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| Abstract: ARM1020E ARM966E-S XScale StrongARM ARM7 ARM7TDMI ARM7TDMI -S ARM7EJ-S ARM720T ARM720T Cache / 8k , ARM9 Cache TCM / ARM920T ARM920T 16K/16K 16K/16K MMU AHB Thumb DSP Jazelle , Cache TCM / ARM926EJ- ARM926EJ- 4-128K/4MMU 4-128K/4MMU S 128 ARM946E- ARM946E- 4-1MB/4MPU S 1MB ARM966E ARM966E S , ARM1020 ARM1020 E ARM1022 ARM1022 E ARM1026 ARM1026 EJ-S Cache / 32K/32 32K/32 K 16K/16 16K/16 K TCM AHB , ARM11 ARM11 Cache / TCM ARM1136 ARM1136 4-64K 4-64K J-S ARM1136 ARM1136 4-64K 4-64K JF-S AHB ... | Original |
3 pages, |
ARM7EJ-S arm1136 ARM720T ARM1026 ARM922T ARM940T ARM966E- ARM11 ARM920T ARM10E jazelle ARM SecurCore SC100 ARM10E abstract |
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| Abstract: data are already cached, sector read/write operations can be carried out on cache. Flush cache - Flush cached data to device. Buffer Cache Manager caches data at the file system level. When an , caches device data, and try to let device read/write operations carry out on cache instead of on disk , already cached the file data, Buffer Cache Management can return data to user directly, and no device read operations by device driver are needed. If the specified block is not cached, the Buffer cache ... | Original |
3 pages, |
TFS4 samsung tfs4 what is cache memory datasheet abstract |
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| Abstract: different in the MC68EC020 MC68EC020 instruction cache. The MC68020 MC68020, MC68030/EC030 MC68030/EC030, and MC68040/EC040 MC68040/EC040 use all 32 bits , ) is first checked to determine if the word required is in the cache. This check is achieved by first using the index field (A7-A2) of the access address as an index into the on-chip cache. This index selects one of the 64 entries in the cache. Next, A31-A8 A31-A8 and FC2 are compared to the tag of the selected , be cleared. System hardware can assert the CDIS signal to disable the cache. The assertion of CDIS ... | OCR Scan |
4 pages, |
MC68EC020 MC68020 FF000000 A31-A24 M68020 MC68020/EC020 A31-A8 MC68030/EC030 MC68040/EC040 MC68020/EC020 abstract |
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| Abstract: Block Diagram MMU L bus I bus 1 TLB CPU UBC CCN AUD SCI Peripheral bus 1 1.2 TMU CACHE RTC BRIDGE BSC SCIF DMAC CPG/WDT CMT Peripheral bus 2 INTC I bus 2 H-UDI ADC DAC External bus interface Legend ADC : A/D converter AUD : Advanced user debugger BSC : Bus state controller CACHE : Cache memory CCN : Cache memory controller CMT : Compare match timer CPG/WDT : Clock pulse generator/watchdog timer CPU : Central processing ... | Original |
1 pages, |
SH7706 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| CACHE_BYPASS() \ {CSR &= 0xFFFFFF1F; CSR |= 0x80;} #define CACHE_FLUSH() \ {CACHE_DISABLE */ /* CACHE_BYPASS() - Bypass program memory cache */ /* CACHE_FLUSH */ /*-*/ #define CACHE_ENABLE() \ {CSR &= 0xFFFFFF1F; CSR |= 0x40;} #define CACHE_DISABLE /*/ /* CACHE.H - TMS . */ /* */ /* MACRO FUNCTIONS: */ /* CACHE_ENABLE www.datasheetarchive.com/download/28616375-869514ZC/ss130a.zip (CACHE.H) |
Texas Instruments | 08/02/1999 | 591.08 Kb | ZIP | ss130a.zip |
| 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) The 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back (or write-through) for 82434LX 82434LX 82434LX 82434LX) cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache www.datasheetarchive.com/files/intel/design/pcisets/datashts/290479-v1.htm |
Intel | 03/08/1997 | 1.68 Kb | HTM | 290479-v1.htm |
| 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) The 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back (or write-through) for 82434LX 82434LX 82434LX 82434LX) cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache www.datasheetarchive.com/files/intel/design/pcisets/datashts/290479.htm |
Intel | 31/10/1997 | 2.47 Kb | HTM | 290479.htm |
| 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache and Memory Controller (PCMC) The 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX 82434LX/82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back (or write-through) for 82434LX 82434LX 82434LX 82434LX) cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache www.datasheetarchive.com/files/intel/design/pcisets/datashts/290479-v2.htm |
Intel | 10/02/1998 | 2.47 Kb | HTM | 290479-v2.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization schemes. The www.datasheetarchive.com/files/intel/design/intarch/papers/cache6.htm |
Intel | 03/08/1997 | 1.78 Kb | HTM | cache6.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization www.datasheetarchive.com/files/intel/design/intarch/papers/cache6-v2.htm |
Intel | 31/10/1997 | 2.58 Kb | HTM | cache6-v2.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization www.datasheetarchive.com/files/intel/design/intarch/papers/cache6-v5.htm |
Intel | 01/08/1998 | 2.52 Kb | HTM | cache6-v5.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium® processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common www.datasheetarchive.com/files/intel/design/intarch/papers/cache6-v6.htm |
Intel | 30/10/1998 | 2.56 Kb | HTM | cache6-v6.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization www.datasheetarchive.com/files/intel/design/intarch/papers/cache6-v1.htm |
Intel | 10/02/1998 | 2.58 Kb | HTM | cache6-v1.htm |
| An Overview of Cache An Overview of Cache The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization www.datasheetarchive.com/files/intel/design/intarch/papers/cache6-v3.htm |
Intel | 30/04/1998 | 2.52 Kb | HTM | cache6-v3.htm |