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LP55281TL/NOPB Texas Instruments 12-Channel RGB/White-LED Driver with SPI/I2C Interface 36-DSBGA -30 to 85 visit Texas Instruments Buy
LP55281RLX/NOPB Texas Instruments 12-Channel RGB/White-LED Driver with SPI/I2C Interface 36-DSBGA -30 to 85 visit Texas Instruments
LP55281RL/NOPB Texas Instruments 12-Channel RGB/White-LED Driver with SPI/I2C Interface 36-DSBGA -30 to 85 visit Texas Instruments Buy
LP55281TLX/NOPB Texas Instruments 12-Channel RGB/White-LED Driver with SPI/I2C Interface 36-DSBGA -30 to 85 visit Texas Instruments
SN65LVDS315RGETG4 Texas Instruments 8-bit Parallel RGB to MIPI® CSI-1 or SMIA CCP Transmitter/Serializer 24-VQFN -40 to 85 visit Texas Instruments
SN65LVDS315RGET Texas Instruments 8-bit Parallel RGB to MIPI® CSI-1 or SMIA CCP Transmitter/Serializer 24-VQFN -40 to 85 visit Texas Instruments

bt.656 parallel to RGB 565

Catalog Datasheet MFG & Type PDF Document Tags

BT656 to MIPI

Abstract: bt.656 to MIPI support is also ensured through an ITU-R BT.656 parallel video â  Full range of image effects interface. The MC521EA is programmed through a MIPI â  Output formats: RGB 565/555/444/888 compatible two-wire camera control interface (CCI). YUV 422, RAW 8, RAW 10 and ITU-R BT.656 parallel , state-of-the-art 2Megapixel (1600H x 1200V) CMOS image sensor with an advanced image signal processor to enable , VSYNC HSYNC BT.656 BT.656 Y [ 7:0 ] GPIO GPIO GPIO [5:0] Output Output Formatting
MagnaChip Semiconductor
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BT656 to MIPI bt.656 to MIPI bt.656 parallel to RGB 565 bt 656 to MIPI

BT656 to Bayer

Abstract: supports an ITU-R BT.656 parallel video interface with inversion programmable slew rates for low EMI , consumer devices. programmed through a low cost compatible two-wire camera Output formats: RGB 565/555/444, YUV 422, RAW 12 bit and ITU-R BT.656 parallel video interface © 2007 MagnaChip , efficient camera modules image signal processor to enable ultra compact 6x6x4mm camera â  Single 2.4 to 3.1V power supply modules with a single 2.8V power supply for cost sensitive â
MagnaChip Semiconductor
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BT656 to Bayer MC511EA 1280H

aJ-200

Abstract: bt.656 parallel to RGB 565 LCD Controller ·24-bit TFT LCD panel interface ·Resolution up to 1280 x 1280 ·Input modes (RGB, color palette, YcbCr422/420) ·256 entries 16-bit RGB color palette RAM ·Two PiP windows ·Picture out of Picture (PoP) ·Output formats (RGB parallel, ITU-R BT. 656) ·Video Scalar (up & , ·Resolution up 1920 x 1080 ·Input formats (ITU-R BT. 656/.1120, YCrCb 4:2:2) · utput formats (RGB 888/565 , aJ-200 is ideally suited to power the next generation of the mobile POS terminals, handheld devices
aJile Systems
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aJ-200 QCIF LCD Controller 0829 LCD 2.2 QCIF AJILE SYSTEMS ITU-R BT.656 to jpeg J-200TM J-200 IEEE-754
Abstract: panel interface Resolution up to 1280 x 1280 Input modes (RGB, color palette, YcbCr422/420) 256 entries 16-bit RGB color palette RAM Two PiP windows Picture out of Picture (PoP) Output formats (RGB parallel, ITU-R BT. 656) Video Scalar (up & down) Video Output Port (ITU-R BT. 656) Three Image , '¢ Output formats (RGB 888/565, YCbCr 4:4:4, 4:2:2, 4:2:0) MediaCodec â'¢ â'¢ â'¢ â'¢ â'¢ MPEG , aJ-200 is ideally suited to power the next generation of the mobile POS terminals, handheld devices aJile Systems
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BT656 to MIPI

Abstract: bt 656 to MIPI differential Camera Serial Interface. The ITU-R BT.656 8-bit parallel video interface is also supported. On-the-fly JPEG compression reduces interface bandwidth to minimize EMI emissions. optical zoom control â  Output formats: RGB 565/555/444/888 YUV 422, JEPG 8, RAW 10 and ITU-R BT.656 parallel video , to infinity using a three plastic element, fixed position imaging lens for the lowest overall camera , PLL Specifications â  Active Pixels 2,048(H) x 1,536(V) â  Input Clock MCLK: 6 to
MagnaChip Semiconductor
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MC531E 2048H

FPGA-based LCD driver circuit

Abstract: 800x480 resolution ) to an external SDRAM frame buffer. The pixel data is packed to a RGB 565 format, transferring two , Video Input Module The BT-656 video input module (shown in Figure 6) is designed to be compatible with , space conversion (CSC), clipping, de-interlacing, scaling, and an RGB 565 pack. Each operation is , streams to the left and right viewing perspectives. The parallel channels are assignable to either , optional auxiliary RGB decoder or RGB deserializer, and parallel logic or LVDS are available for YCrCb and
Altera
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FPGA-based LCD driver circuit 800x480 resolution graphic lcd panel fpga example GRAPHICAL LCD DIAGRAM bt.656 to RGB LCD display lcd 800x480 driver ram
Abstract: MacrovisionTM. ITU-R BT.656 interlaced video can be input and scan converted to non-interlaced video. In , In ITU-R BT.601/656 TV Encoder mode, interlaced data, sync and clock signals are input to the CH7205 , are supported. CH7205 can output data in S-Video and CVBS format, or as RGB for interface to a SCART , ), (multiplex scheme 2) 8-bit multiplexed RGB input (16-bit color, 565) 8-bit multiplexed RGB input (15 , to the next luminance sample, per ITU-R BT.656 standards (the clock frequency is dependent upon the Chrontel
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CH7205A CH7205A-D

VGA to Y PB PR

Abstract: scart vga Operation CH7015 The CH7015 is capable of being operated as a VGA to TV encoder, an ITU-R BT.601/656 , ) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder (NTSC / (VGA -> XGA) YCrCb1 S-Video PAL) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder (SCART (VGA -> XGA) YCrCb1 RGB format) Interlaced RGB , non-interlaced YPbPr3 (1080p) YCrCb1 (1080p) interlaced RGB / ITU-R BT.601/656 TV Deinterlace non-interlaced YPbPr2 (480i, 576i) YCrCb1 (480p, 576p generation) interlaced RGB / Interlaced CVBS, ITU-R BT.601/656 TV
Chrontel
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VGA to Y PB PR scart vga CH7015A-T

SDIO CARD Layout

Abstract: ITU-R BT.1120 to BT.656 4 in 1 windows PoP display Output Format o RGB parallel (18/24 bits) o Swap of parallel RGB and , o RGB 565 o YCbCr 4:4:4 o YCbCr 4:2:2 o YCbCr 4:2:0 · Edge-base line in average de-interlace · , threading primitives, multimedia functions, and secured networking. It's designed specifically to power a wide range of mobile internet appliances, which allow the mobile media, and edutainment contents to be , on-demand over Internet. The aJ-200 is ideally suited to power the next generation of the mobile internet
aJile Systems
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SDIO CARD Layout ITU-R BT.1120 to BT.656 ITU-R BT.1120 1280 android usb ITU-R BT.1120 BT.1120 J--200
Abstract: -bit) or RGB 5-6-5 (2x8-bit) RGB 5-6-5 (2x8bit) RGB 5-5-5 (2x8-bit) YCrCb 8-8 (2x8-bit) (refer to , color-difference samples and the following Y1 byte refers to the next luminance sample, per ITU-R BT.656 standards , [6] D[5] D[4] P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] 2 RGB 5-6-5 , accepts a graphics data stream over one 12-bit wide variable voltage (1.1V to 3.3V) port. The data stream outputs through an LVDS transmitter to an LCD panel. A maximum of 100M pixels per second can be Chrontel
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CH7304

CH7026B-TF

Abstract: CH7026B-TFI achieved by storing video data to the internal input interface supports various RGB (RGB888, RGB666, RGB565 , Supports flexible input resolution up to 800x800 and 1024x680. different video data formats including RGB , adjustment for each output is supported. (For RGB output, only 656). brightness and contrast adjustment is , SDRAM RGB/YCbCr Input data format decoder MUX CSC (YCbCr to RGB) Scaler MUX CSC (RGB to YUV , . External pull-up resister is required. CVBS, S-video, YPbPr or Analog RGB output Full swing is up to 1.3v
Chrontel
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CH7026B-TF CH7026B-TFI CH7026B bt.656 parallel to serial conversion for vga camera g9sp bt.656 to CVBS small size CH7025/CH7026 CH7025/26 ITU656 CH7025B-GF CH7025B-GFI CH7025B-TF

ADSP-BF561 filter implementation

Abstract: bt.656 parallel to RGB 565 OUTPUT TO "6-6-6" RGB LCD PANEL PACK IN "5-6-5" WORD SCALING Figure 2. Example of system flow , , the ADSP-BF561 Blackfin Processor can directly connect to many TFT- LCD modules through its parallel , panels, the PPI can gluelessly decode ITU-R BT.656 data and can also interface to ITU-R BT.601 video , is straightforward, there are many things to consider in choosing the appropriate RGB data format , each of R and B, and 6 bits of G (5+6+5 = 16) to match the 16-bit data bus. This scenario works well
Analog Devices
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ADSP-BF561 filter implementation lcd 3901 RGB signal converting to vga

Ba 33 bco

Abstract: SMPTE-274M different data formats including RGB and YCrCb. The TV-Out processor will perform non-interlace to interlace , operated as a VGA to TV encoder, an ITU-R BT.601/656 encoder (with or without a de-interlacing function , , VGA to SDTV encoder (NTSC / (VGA -> XGA) YCrCb1 S-Video PAL) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder (SCART (VGA -> XGA) YCrCb1 RGB format) Interlaced RGB / HDTV/EDTV bypass Interlaced , (1080p) interlaced RGB / ITU-R BT.601/656 TV Deinterlace non-interlaced YPbPr2 (480i, 576i) YCrCb1 (480p
Chrontel
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CH7015A-D Ba 33 bco SMPTE-274M 8-32x5 ST T4 3570 rca 8240 CH7015A CH7015A-DF CH7015A-D-TR CH7015A-DF-TR

Ba 33 bco

Abstract: rca 8240 is integrated to create outstanding video quality. Support is provided for MacrovisionTM. ITU-R BT.656 , , YCrCb 720p) Interlaced CVBS, VGA to SDTV encoder (NTSC / non-interlaced RGB / S-Video PAL) (VGA -> XGA) YCrCb1 Interlaced CVBS, VGA to SDTV encoder (SCART non-interlaced RGB / RGB format , interlaced RGB / ITU-R BT.601/656 TV Deinterlace 1 (480i, 576i) YCrCb (480p, 576p generation) Interlaced CVBS, ITU-R BT.601/656 TV Encoder interlaced RGB / S-Video (NTSC / PAL) (480i, 576i
Chrontel
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DAC IC 0804 EIA-770 5R07 720x576i 1920x1080 PAL to ITU-R BT.601/656 Decoder

Ba 33 bco

Abstract: 4 bit dac 0804 including RGB and YCrCb. The TV-Out processor will perform non-interlace to interlace conversion with , . ITU-R BT.656 interlaced video can also be input and scan converted to non-interlaced video. In addition , CH7016A The CH7016A is capable of being operated as a VGA to TV encoder, an ITU-R BT.601/656 encoder , bypass non-interlaced YPbPr2,3 1 (480p, 576p, YCrCb 720p) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder (NTSC / (VGA -> XGA) YCrCb1 S-Video PAL) non-interlaced RGB / Interlaced CVBS, VGA to SDTV
Chrontel
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4 bit dac 0804 CH7016A-DF CH7016A-DF-TR
Abstract: Multi-Mode, 24-Bit Input Port: ­ Supports Parallel RGB With Pixel Clock Up to 33.5 MHz and 3 Input Color , the form of a logic-high, pulsed interrupt flag. PARALLEL RGB MODE BT.656 I/F MODE Pixel clock (2 , :2:2 YCrCb565 ­ Supports 8-Bit BT.656 Bus Mode With Pixel Clock Up to 33.5 MHz Supports Input , DIAGRAM DLPC300 DLP3000 DATA & CONTROL RECEIVER PARALLEL RGB Data Interface DATA(14:0) LOADB TRC , . The DLPC300 takes as input 16-, 18- or 24-bit RGB data at up to 60-Hz frame rate. This frame rate is Texas Instruments
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DLPS023B 4000-H 120-H 166-MH 176-P ISO/TS16949

mx25l800

Abstract: K4X56163PN-FGC6 Multi-Mode, 24-Bit Input Port: ­ Supports Parallel RGB With Pixel Clock Up to 33.5 MHz and 3 Input Color , to INIT-DONE. Reserved for future use. This pin should be left unconnected. PARALLEL RGB MODE VCC , :2:2 YCrCb565 ­ Supports 8-Bit BT.656 Bus Mode With Pixel Clock Up to 33.5 MHz Supports Input , . DLPC300 DLP3000 DATA & CONTROL RECEIVER PARALLEL RGB Data Interface DATA(14:0) LOADB TRC SCTRL , 24-bit RGB data at up to 60-Hz frame rate. This frame rate is composed of three colors (red, green
Texas Instruments
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mx25l800 K4X56163PN-FGC6 bt.656 to RGB888 H5MS2562 rgb888 656 H5MS2562JFR-J3M DLPS023A
Abstract: . ITU-R BT.656 interlaced video can also be input and scan converted to non-interlaced video. Timing , 1 (480p, 576p, YCrCb 720p) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder (NTSC / (VGA -> XGA) YCrCb1 S-Video PAL) non-interlaced RGB / Interlaced CVBS, VGA to SDTV encoder , (1080p) interlaced RGB / non-interlaced YPbPr2 ITU-R BT.601/656 TV Deinterlace 1 (480i, 576i) YCrCb (480p, 576p generation) interlaced RGB / Interlaced CVBS, ITU-R BT.601/656 TV Encoder (480i Chrontel
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esd samsung

Abstract: bt.656 parallel to serial conversion for vga camera -Bit Input Port: ­ Supports Parallel RGB With Pixel Clock Up to 33.5 MHz and 3 Input Color Bit-Depth Options , YCrCb565 ­ Supports 8-Bit BT.656 Bus Mode With Pixel Clock Up to 33.5 MHz Supports Input Resolutions , CONTROL RECEIVER PARALLEL RGB Data Interface DATA(14:0) LOADB TRC SCTRL SAC_BUS CMOS MEMORY ARRAY , interface. The DLPC300 takes as input 16-, 18- or 24-bit RGB data at up to 60-Hz frame rate. This frame rate , reproduced by controlling the amount of time the mirror is on. For a 24-bit RGB frame image inputted to the
Texas Instruments
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esd samsung DLPU004 b34 diodes on semiconductor 3.5 wVGA lcd vga controller BT656 to rgb888 DLPS023
Abstract: : â'" Supports Parallel RGB With Pixel Clock Up to 33.5 MHz and 3 Input Color Bit-Depth Options: â , PARALLEL RGB MODE BT.656 I/F MODE PCLK D13 VCC_ INTF I3 N/A Pixel clock (2) Pixel , YCrCb565 â'" Supports 8-Bit BT.656 Bus Mode With Pixel Clock Up to 33.5 MHz Supports Input Resolutions , GPIO4_INTF PLL_REFCLK DATA & CONTROL RECEIVER PARALLEL RGB Data Interface DLP3000 VCC VSS , -bit RGB data at up to 60-Hz frame rate. This frame rate is composed of three colors (red, green, and blue Texas Instruments
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