500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Direct from the Manufacturer

Part Manufacturer Description PDF & SAMPLES
STELLARIS-3P-CODER-DPROBE430-DEVBD Texas Instruments Red Suite 2
CYCLONE-3-MERCURYCODE-REF Texas Instruments Cyclone III-based MercuryCode
KOKEYCODE10001 E-Switch Inc REPLACEMENT KEY CODE 10001
ADZS-ENCODE-EX3 Analog Devices Inc ADZS-ENCODE-EX3
ADZS-DECODE-EX3 Analog Devices Inc ADZS-DECODE-EX3
SJ-5017 (GRAY) 3M Interconnect BUMPON HEMISPHERE .75X.38 GRAY

binary to gray code converter

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: ) read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag Generation Logic empty_out BlockSelect , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The Xilinx
Original
XAPP131 vhdl code for asynchronous fifo block diagram for asynchronous FIFO testbench verilog ram asynchronous Asynchronous FIFO asynchronous fifo vhdl xilinx asynchronous fifo
Abstract: ) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag , clocks are presented. Signal names in parenthesis are a reference to the name in the Verilog code , . There are primary 9-bit Read and Write binary address counters, which drive the address inputs to the Block RAM. The binary addresses are converted to Gray-code, and pipelined for a few stages to create , application note describes a way to create a common-clock (synchronous) version and an independent-clock Xilinx
Original
Logic diagram for asynchronous FIFO 4 bit gray to binary converter circuit asynchronous fifo code in verilog synchronous fifo synchronous fifo design in verilog vhdl code for a grey-code counter 170MH
Abstract: ) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag , . There are primary 9-bit Read and Write binary address counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code, and pipelined for a few stages to create , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The Xilinx
Original
4 bit gray code counter VHDL 4 bit gray code synchronous counter vhdl code of binary to gray verilog code for 8 bit fifo register FIFO error reset full empty asynchronous fifo vhdl fpga
Abstract: Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (READ) 9-BIT FIFO Status Register read_data_out fifo_gsr_in x258 , presented. Signal names in parenthesis are a reference to the name in the Verilog or VHDL code , convenience, to determine when the FIFO is 1/2 full, 3/4 full, etc, as shown in Table 3. It is a binary count Xilinx
Original
XAPP258 testbench verilog ram 16 x 8 vhdl code for fifo testbench verilog ram 16 x 4 fifo vhdl fifo design in verilog
Abstract: ) read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag Generation Logic empty_out BlockSelect , -bit Read and Write binary address counters, which drive the address inputs to the block RAM. The binary , application note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The Xilinx
Original
4K x 1
Abstract: . fifostatus_out write_clock_in write_enable_in write_data_in full_out WRITE Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter , presented. Signal names in parenthesis are a reference to the name in the Verilog or VHDL code , to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or Xilinx
Original
asynchronous fifo vhdl xilinx XAPP258.ZIP
Abstract: : for Loops Example 25 â'" 4-Bit Binary to Gray Code Converter Example 26 â'" 4-Bit Gray Code to Binary Converter Problems 111 112 112 113 115 116 117 6. Arithmetic Circuits 6.1 Adders , Equations Example 21 â'" 8-to-3 Encoder: for Loops Example 22 â'" 8-to-3 Priority Encoder 5.5. Code , 102 103 103 104 105 107 107 109 109 110 Gray Code Converters Verilog Examples Example 23 , . Introduction to Digital Logic 1.1 Background 1.2 Digital Logic 1.3 Verilog 1 1 5 8 2. Basic Logic Digilent
Original
verilog code of 8 bit comparator full subtractor circuit using decoder verilog code for multiplexer 2 to 1 verilog code of 4 bit comparator verilog code for distributed arithmetic verilog code for binary division
Abstract: Add 3 Algorithm Gray Code Converters VHDL Examples Example 16 â'" 4-Bit Binary-to-BCD Converter: Logic Equations Example 17 â'" 8-Bit Binary-to-BCD Converter: for Loops Example 18 â'" 4-Bit Binary to Gray Code Converter Example 19 â'" 4-Bit Gray Code to Binary Converter 5.4 Comparators Cascading , 5 â'" Map Report Problems 5. Combinational Logic 5.1 Multiplexers 2-to-1 Multiplexer 4-to-1 Multiplexer Quad 2-to-1 Multiplexer VHDL Examples Example 6 â'" 2-to-1 Multiplexer: if Statement Example 7 Digilent
Original
vhdl code for 16 BIT BINARY DIVIDER vhdl code for multiplexer 32 BIT BINARY VHDL code for PWM vhdl code for multiplexer 32 to 1 vhdl code for motor speed control PWM code using vhdl
Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital , A'c' or 'c' Org (Origin) Org tells the Assembler where to start generating code. Normally we start , resolution on any of 11 channels. The converter can be referenced to the device's VDD or an external voltage Microchip Technology
Original
DS51556A DS41262 PICkit 2 Low Pin Count Demo Board PIC16f690 binary clock PIC16F690 LED project DS51556 PIC12F675 asm programs DS51556A-
Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital , assembler where to start generating code. Code may be generated for any area of the part. Mid-range PIC , (ADC) with 10 bits of resolution on any of 14 channels. The converter can be referenced to the device Microchip Technology
Original
P16F887 PIC16F887 POTENTIOMETER ADC DS41291 PIC16F887 LED POTENTIOMETER ADC PIC16F887 Free Projects PIC16F877A Free Projects of LED 44-PIN DS41296B DS41296B-
Abstract: 0111 and 1000. Some ADCs make use of it internally and then convert the Gray code to a binary code for , . The Gray code output is then latched, converted to binary, and latched again at the final output , convert the Gray code output to binary for external use. The conversion from Gray-to-binary and , -2 binary code relative to full-scale (FS), and also the corresponding voltage level for each code (assuming a +10 V full-scale converter. The Gray code equivalent is also shown, and will be discussed -
Original
MT-009 ISBN-0-13-032848-0 bcd to gray code converter Gray to BCD converter BCD Gray Converter bcd to gray code conversion base-10 Analog-Digital Conversion Handbook
Abstract: often been referred to as serial-Gray (since the output coding is in Gray code), or folding converter , GRAY CODE REGISTER 3 GRAY-TO-BINARY CONVERTER 3 OUTPUT REGISTER 3 Figure 6: 3-bit Folding ADC , realizing the Gray code folding transfer function). 4. F. D. Waldhauer, "Analog-to-Digital Converter," , diode switches in the feedback loops to implement the Gray code folding transfer function). 5. J , Gray (or folding) transfer functions required to implement the A/D conversion. Rev.A, 10/08, WK -
Original
Fairchild uA710 ua710 application note HS810 3-bit magnitude comparator folding-ADC uA710 MT-025 AD6645 636B1
Abstract: the 5-bit binary code as shown in Figure 6. SERIAL DATA TO RECEIVER ROTATING COMMUTATOR , errors associated with binary shadow masks were later eliminated by using a Gray code shadow mask as , conversion to binary code is only one least significant bit (LSB). In the case of midscale, note that only , the same effect if straight binary decoding techniques are used. In many cases, Gray code, or "pseudo-Gray" codes are used to decode the comparator bank output before finally converting to a binary code Analog Devices
Original
TDC1014j esaki Diode TDC1007J TDC1014 woodward peak 150 ua711 MT-020 600MH 60MSPS 89CH2771-4
Abstract: -bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion , input range at the converter, to cover code 0 V RT ­ V RB R OB + R L + R OT to 1023 is V I = R L , ; referenced to AGND, VRB = 1.3 V, VRT = 3.7 V; binary/gray codes) Vi(a)(p-p) (V) IR < 1.5 1.5 3.51 > 3.51 0 1 , high impedance active active Gray mode selection OE 1 0 0 D9 to D0 high impedance active; binary , ) output ground gray code input (active HIGH) data output; bit 0 (Least Significant Bit (LSB) data output Integrated Device Technology
Original
gray to binary code converter ADC1005S060
Abstract: ®           10-bit resolution (binary or gray code , - and the full-scale input range at the converter, to cover code 0 RL to 1023 is V I = R L ï , V, VRT = 3.7 V; binary/gray codes) Vi(a)(p-p) (V) IR Binary outputs D9 to D0 Gray outputs D9 , (typical values; referenced to AGND; binary/twos complement codes) Code Vi(a)(p-p) (V) IR Binary , voltage input VI 8 CMOS OUTPUTS LATCHES ANALOG - TO - DIGITAL CONVERTER 21 20 19 Integrated Device Technology
Original
Abstract: DAC must settle to 8-bit accuracy before the bit decision is made, whereas in a 16-bit converter, it , connected to ground, and the converter is ready for another cycle. 3-BIT SWITCHED CAPACITOR DAC BIT1 , array equal to 2C so that binary division is accomplished when the individual bit capacitors are , repetition rate from DC to the converter's maximum conversion rate. In a SAR ADC, the output data for a , more than 13 binary bits to the outside world. Additional bits would carry no useful signal Analog Devices
Original
AD77xx-series AD1853 walt Kester sensor AD1877 AD7725 AD77xx-series audio 150MSPS 50MSPS
Abstract: DEMONSTRATION BOARD The switch K1 corresponding to the gray input GRAY allows the choice either the BINary or , diagram of a binary to gray function is given on Figure 6. B0 G0 B1 B0 B1 G0 0 0 1 1 0 1 , (MSB) G9 - Figure 6. Binary to gray function - The switch K2 corresponding to the output , 0 OEN 1 0 0 0 D9 to D0 IR high impedance binary active gray active two's complement , input signal into 10 bits binary, into two's complement or into gray digital words at a maximum Philips Components
Original
TDA8764ATS t7805ct T7805CT fixed voltage regulator equivalent transistor LM317T t7805ct motorola t7805- SECME 10-BIT AN/99042 TDA8764A TDA8764ATS/TDA8764AHL
Abstract: DEMONSTRATION BOARD The switch K1 corresponding to the gray input GRAY allows the choice either the BINary or , diagram of a binary to gray function is given on Figure 6. B0 G0 B1 B0 B1 G0 0 0 1 1 0 1 , (MSB) G9 - Figure 6. Binary to gray function - The switch K2 corresponding to the output , 0 OEN 1 0 0 0 D9 to D0 IR high impedance binary active gray active two's complement , input signal into 10 bits binary, into two's complement or into gray digital words at a maximum Philips Components
Original
SMD rob motorola LM317T KONY 12V convert to 3.7V 3H DIODE smd smd transistor G9 AN/00018
Abstract: (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only High , specification 10-bit high-speed low-power ADC FEATURES · 10-bit resolution (binary or gray code) · Sampling , voltage (5 V) digital ground supply voltage for output stages (2.7 to 3.6 V) output ground gray code input , input range at the converter, R OB + R L + R OT RL 8375 × ( V ­ V ) to cover code 0 to 1023, is V I = R , to AGND; VRB = 1.3 V; VRT = 3.7 V; binary/gray codes BINARY OUTPUT BITS GRAY OUTPUT BITS VI Philips Semiconductors
Original
hall effect ic 6838 TDA8764ATS/6/C1 TDA8764AHL/6/C1
Abstract: MODE AVSS Converting back to offset binary from Gray code must be done recursively, using the , Float 9 FIGURE 32. GRAY CODE TO BINARY CONVERSION Mapping of the input voltage to the various , 100 00 000 00 0 ···· Gray Code 9 8 7 ···· 1 0 FIGURE 31. BINARY TO GRAY , · Nap and Sleep Modes · Two's Complement, Gray Code or Binary Data Format · DDR LVDS-Compatible or , Divider Control Output Data Format (Two's Comp., Gray Code, Offset Binary) Analog Ground NOTE Intersil
Original
KAD5510P-50 500MSPS KAD5512P-50 KAD5514P-12 KAD5514P-17 KAD5514P-21 FN6811 125MSPS 250MSPS 500MH
Showing first 20 results.