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ICL7135CPIZ Intersil Corporation 4 1/2 Digit, BCD Output, A/D Converter; PDIP28; Temp Range: 0° to 70° ri Buy
LTC1967IMS8#TR Linear Technology LTC1967 - Precision Extended Bandwidth, RMS-to-DC Converter; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C ri Buy
LTC1967CMS8#TR Linear Technology LTC1967 - Precision Extended Bandwidth, RMS-to-DC Converter; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C ri Buy

binary to gray code converter

Catalog Datasheet Type PDF Document Tags
Abstract: ) read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag Generation Logic empty_out BlockSelect , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The ... Original
datasheet

7 pages,
73.69 Kb

XAPP131 asynchronous fifo design in verilog verilog code for asynchronous fifo testbench verilog ram 16 x 4 4 bit gray code counter VHDL vhdl code of binary to gray asynchronous fifo vhdl xilinx xilinx asynchronous fifo asynchronous fifo vhdl Asynchronous FIFO testbench verilog ram asynchronous XAPP131 abstract
datasheet frame
Abstract: fifostatus_out write_clock_in write_enable_in write_data_in full_out WRITE Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter , Signal names in parenthesis are a reference to the name in the Verilog or VHDL code. Synchronous , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code ... Original
datasheet

6 pages,
60.74 Kb

vhdl code for fifo XAPP258.ZIP XAPP131 asynchronous fifo vhdl asynchronous fifo code in verilog Asynchronous FIFO xilinx asynchronous fifo 4 bit gray code synchronous counter asynchronous fifo vhdl xilinx 4 bit gray code counter VHDL XAPP258 vhdl code for asynchronous fifo XAPP258 abstract
datasheet frame
Abstract: ) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag , clocks are presented. Signal names in parenthesis are a reference to the name in the Verilog code , There are primary 9-bit Read and Write binary address counters, which drive the address inputs to the Block RAM. The binary addresses are converted to Gray-code, and pipelined for a few stages to create , application note describes a way to create a common-clock (synchronous) version and an independent-clock ... Original
datasheet

6 pages,
33.16 Kb

XAPP205 XAPP131 asynchronous fifo vhdl xilinx vhdl code for a grey-code counter synchronous fifo design in verilog vhdl code for asynchronous fifo synchronous fifo asynchronous fifo code in verilog block diagram for asynchronous FIFO 4 bit gray to binary converter circuit Logic diagram for asynchronous FIFO binary to gray code converter XAPP131 abstract
datasheet frame
Abstract: read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The , FIFO is 511 x 8 instead of 512 x 8 since one address is dropped out of the FIFO in order to provide ... Original
datasheet

6 pages,
66.84 Kb

XAPP131 Asynchronous FIFO asynchronous fifo vhdl fpga FIFO error reset full empty Logic diagram for asynchronous FIFO synchronous fifo design in verilog testbench verilog ram asynchronous verilog code for 8 bit fifo register vhdl code for a grey-code counter vhdl code of binary to gray synchronous fifo XAPP131 abstract
datasheet frame
Abstract: read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code , counters, which drive the address inputs to the block RAM. The binary 4 www.xilinx.com , application note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The , FIFO is 511 x 8 instead of 512 x 8 since one address is dropped out of the FIFO in order to provide ... Original
datasheet

6 pages,
32.66 Kb

testbench verilog ram 16 x 4 XAPP131 fifo vhdl 4 bit gray code counter VHDL binary to gray code converter 4 bit gray code synchronous counter 4K x 1 block diagram for asynchronous FIFO vhdl code for asynchronous fifo XAPP131 abstract
datasheet frame
Abstract: Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (READ) 9-BIT FIFO Status Register read_data_out fifo_gsr_in , Signal names in parenthesis are a reference to the name in the Verilog or VHDL code. Synchronous , convenience, to determine when the FIFO is 1/2 full, 3/4 full, etc, as shown in Table 3. It is a binary count ... Original
datasheet

6 pages,
69.02 Kb

01072500 asynchronous fifo vhdl xilinx fifo design in verilog fifo vhdl synchronous fifo synchronous fifo design in verilog testbench verilog ram 16 x 4 testbench verilog ram asynchronous verilog code for 8 bit fifo register XAPP131 block diagram for asynchronous FIFO asynchronous fifo vhdl XAPP258 XAPP258 abstract
datasheet frame
Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium , A'c' or 'c' Org (Origin) Org tells the Assembler where to start generating code. Normally we start , resolution on any of 11 channels. The converter can be referenced to the device's VDD or an external voltage ... Original
datasheet

42 pages,
324.58 Kb

LINK30 PIC12F508 PIC16f688 example code LED low pin count lpc PIC12F509 DS51553 PIC12F683 example ASSEMBLER pic16f676 asm code PIC16F690 dip PIC16f690 interrupt binary to gray code converter DS-41262 DS51556A DS51556A DS51556A abstract
datasheet frame
Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium , which to start generating code. Normally we start coding at the Reset vector address `0000', but it , (ADC) with 10 bits of resolution on any of 14 channels. The converter can be referenced to the device's ... Original
datasheet

42 pages,
371.95 Kb

PIC16F887 pclath call PIC18F4520 switch Advantage MPLAB IDE 8.86 pic16f887 full instruction set PIC18F4620 adc example code pic18f4550 icsp binary to gray code converter pic16f887 Applications pic16f877a full instruction set pic16f877a projects PIC16F887 SPECIFICATIONS PIC16F877A led blink source code 44-PIN DS41296B 44-PIN abstract
datasheet frame
Abstract: 0111 and 1000. Some ADCs make use of it internally and then convert the Gray code to a binary code for , The Gray code output is then latched, converted to binary, and latched again at the final output. , convert the Gray code output to binary for external use. The conversion from Gray-to-binary and , binary code relative to full-scale (FS), and also the corresponding voltage level for each code (assuming a +10 V full-scale converter. The Gray code equivalent is also shown, and will be discussed ... Original
datasheet

11 pages,
54.62 Kb

"complementary code" MT-009 gray to bcd code converter ISBN-0-13-032848-0 Analog-Digital Conversion Handbook binary to gray conversion 3 bits gray to binary code converter 4 bit adc base-10 binary to gray code converter bcd to gray code conversion BCD Gray Converter MT-009 abstract
datasheet frame
Abstract: the 5-bit binary code as shown in Figure 6. SERIAL DATA TO RECEIVER ROTATING COMMUTATOR , errors associated with binary shadow masks were later eliminated by using a Gray code shadow mask as , conversion to binary code is only one least significant bit (LSB). In the case of midscale, note that only , the same effect if straight binary decoding techniques are used. In many cases, Gray code, or "pseudo-Gray" codes are used to decode the comparator bank output before finally converting to a binary code ... Original
datasheet

15 pages,
1511.41 Kb

uA709 MC1650 UA711 national semiconductor GALVANOMETER VHS-630 4 bit gray to binary converter circuit tunnel diode analog galvanometer MOD-4100 mercury thermometer binary to gray code converter Fairchild uA711 AM685 MT-020 MT-020 abstract
datasheet frame

Datasheet Content (non pdf)

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Over 1.1 million files (1986-2016): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
The device requires an external source to drive its reference ladder. Features 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock 10-bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and General info The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter (IR) CMOS output TTL and CMOS levels compatible digital inputs 2.7 to 3.6 V CMOS digital outputs
www.datasheetarchive.com/files/philips/pip/tda8764a_1-v2.html
Philips 06/06/2005 3.99 Kb HTML tda8764a_1-v2.html
The device requires an external source to drive its reference ladder. Features 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and ) CMOS output TTL and CMOS levels compatible digital inputs 2.7 to 3.6 V CMOS digital outputs
www.datasheetarchive.com/files/philips/pip/tda8764a_1.html
Philips 23/04/2003 3.22 Kb HTML tda8764a_1.html
external source to drive its reference ladder. 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded CMOS levels compatible digital inputs 2.7 to 3.6 V CMOS digital outputs Low-level AC clock input
www.datasheetarchive.com/files/philips/pip/tda8764a_1-v3.html
Philips 06/12/2000 9.17 Kb HTML tda8764a_1-v3.html
external source to drive its reference ladder. 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded CMOS levels compatible digital inputs 2.7 to 3.6 V CMOS digital outputs Low-level AC clock input
www.datasheetarchive.com/files/philips/pip/tda8764a_1-v1.html
Philips 14/02/2002 9.61 Kb HTML tda8764a_1-v1.html
"thermometer code" is encoded, usually in binary or gray code, to obtain an N-bit digital word which represents from 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35- m m CMOS process code "0, 1, 1," corresponds to a V IN between voltage taps V R3 and V R2 . Note that there is no capacitance of the flash converter. Two distinct enhancements to the flash architecture address this
www.datasheetarchive.com/files/national/htm/nsc02534.htm
National 28/06/2001 27.08 Kb HTM nsc02534.htm
Generator Gray Code (3 pages, updated 1/02) Parameterized IP Core Generator available for the AT40K AT40K AT40K AT40K Application Note describes our enabling technology to make adaptive hardware possible for electronics systems. describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer ) Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. See Software section to download pwm.zip . Implementing a Single-coefficient Multiplier (5
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Atmel 07/05/2002 69.66 Kb BAK prod100.htm-v1.bak
Generator Gray Code (3 pages, updated 1/02) Parameterized IP Core Generator available for the AT40K AT40K AT40K AT40K Application Note describes our enabling technology to make adaptive hardware possible for electronics systems. describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer ) Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. See Software section to download pwm.zip . Implementing a Single-coefficient Multiplier (5
www.datasheetarchive.com/files/atmel/atmel/prod100-v6.htm
Atmel 07/05/2002 69.66 Kb HTM prod100-v6.htm
No abstract text available
www.datasheetarchive.com/download/83212864-549407ZC/demobd.zip (TOP11.DOC)
National 29/04/1997 1334.54 Kb ZIP demobd.zip
No abstract text available
www.datasheetarchive.com/download/56930619-512592ZC/wcd01048.zip (TOP11.DOC)
National 02/04/1998 1334.54 Kb ZIP wcd01048.zip
Editor. To add the HEX2LED Converter template code, click the Use button in the Language Assistant the diagram into either VHDL, Verilog or ABEL code. The resulting HDL file is finally synthesized to added to the project library. The synthesis process encompasses the creation of the HDL code from the To view the HDL code which the State Editor produced, select Tools HDL Editor . Close the template, preview it in the right hand pane by clicking the template. This template provides source code to
www.datasheetarchive.com/files/xilinx/docs/wcd0002c/wcd02c90-v1.htm
Xilinx 04/06/1999 66.71 Kb HTM wcd02c90-v1.htm