NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ) read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag Generation Logic empty_out BlockSelect , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The ... | Original |
7 pages, |
XAPP131 vhdl code of binary to gray xilinx asynchronous fifo asynchronous fifo vhdl xilinx asynchronous fifo vhdl block diagram for asynchronous FIFO vhdl code for asynchronous fifo binary to gray code converter XAPP131 abstract |
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| Abstract: fifostatus_out write_clock_in write_enable_in write_data_in full_out WRITE Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter , Signal names in parenthesis are a reference to the name in the Verilog or VHDL code. Synchronous , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code ... | Original |
6 pages, |
XAPP258.ZIP XAPP258 XAPP131 Asynchronous FIFO asynchronous fifo vhdl xilinx asynchronous fifo asynchronous fifo vhdl xilinx 4 bit gray code synchronous counter vhdl code for asynchronous fifo binary to gray code converter block diagram for asynchronous FIFO XAPP258 abstract |
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| Abstract: ) Binary to Gray Code Converter (WRITE) Binary to Gray Code Converter (READ) FIFO Status Flag , clocks are presented. Signal names in parenthesis are a reference to the name in the Verilog code , There are primary 9-bit Read and Write binary address counters, which drive the address inputs to the Block RAM. The binary addresses are converted to Gray-code, and pipelined for a few stages to create , application note describes a way to create a common-clock (synchronous) version and an independent-clock ... | Original |
6 pages, |
XAPP205 XAPP131 synchronous fifo design in verilog vhdl code for a grey-code counter vhdl code for asynchronous fifo synchronous fifo block diagram for asynchronous FIFO 4 bit gray to binary converter circuit binary to gray code converter XAPP131 abstract |
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| Abstract: read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code , counters, which drive the address inputs to the block RAM. The binary 4 www.xilinx.com , application note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The , FIFO is 511 x 8 instead of 512 x 8 since one address is dropped out of the FIFO in order to provide ... | Original |
6 pages, |
binary to gray code converter XAPP131 fifo vhdl 4K x 1 block diagram for asynchronous FIFO vhdl code for asynchronous fifo XAPP131 abstract |
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| Abstract: read_enable_in READ Counter (Binary) Binary to Gray Code Converter (WRITE) Binary to Gray Code , counters, which drive the address inputs to the block RAM. The binary addresses are converted to Gray-code , note describes a way to create a common-clock (synchronous) version and an independent-clock , code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. Introduction The , FIFO is 511 x 8 instead of 512 x 8 since one address is dropped out of the FIFO in order to provide ... | Original |
6 pages, |
XAPP131 FIFO error reset full empty Logic diagram for asynchronous FIFO synchronous fifo design in verilog vhdl code for a grey-code counter vhdl code of binary to gray 4 bit gray code synchronous counter synchronous fifo 4 bit gray to binary converter circuit vhdl code for asynchronous fifo block diagram for asynchronous FIFO XAPP131 abstract |
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| Abstract: Counter (Binary) Binary to Gray Code Converter (WRITE) FIFO Status Flag Generation Logic empty_out Block RAM 511 x 36 read_clock_in read_enable_in READ Counter (Binary) Binary to Gray Code Converter (READ) 9-BIT FIFO Status Register read_data_out fifo_gsr_in , Signal names in parenthesis are a reference to the name in the Verilog or VHDL code. Synchronous , convenience, to determine when the FIFO is 1/2 full, 3/4 full, etc, as shown in Table 3. It is a binary count ... | Original |
6 pages, |
testbench verilog ram 16 x 8 XAPP131 block diagram for asynchronous FIFO verilog code for 8 bit fifo register fifo vhdl synchronous fifo design in verilog asynchronous fifo vhdl XAPP258 vhdl code of binary to gray vhdl code for asynchronous fifo 4 bit gray to binary converter circuit XAPP258 abstract |
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| Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium , A'c' or 'c' Org (Origin) Org tells the Assembler where to start generating code. Normally we start , resolution on any of 11 channels. The converter can be referenced to the device's VDD or an external voltage ... | Original |
42 pages, |
ASM30 binary to gray code converter DS51025 DS51556A Eye Blink Sensor block LINK30 PIC12F508 PIC12F509 PIC12F675 asm programs pickit 2 PICkit 2 Low Pin Count Demo Board PIC16F690 dip pic16f676 asm code DS51556A abstract |
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| Abstract: breach the code protection feature. All of these methods, to our knowledge, require using the Microchip , evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium , which to start generating code. Normally we start coding at the Reset vector address `0000', but it , (ADC) with 10 bits of resolution on any of 14 channels. The converter can be referenced to the device's ... | Original |
42 pages, |
DS41296 PIC16F877A circuit diagram PIC16F877A Free Projects LED PIC16F882 PIC18f4321 example C18 codes pic18f4550 ram DS41291 PIC16F887 SPECIFICATIONS pic16f887 Applications PIC16F877A led blink source code pic16f877a full instruction set pic16f877a projects 44-PIN DS41296B 44-PIN abstract |
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| Abstract: 0111 and 1000. Some ADCs make use of it internally and then convert the Gray code to a binary code for , The Gray code output is then latched, converted to binary, and latched again at the final output. , convert the Gray code output to binary for external use. The conversion from Gray-to-binary and , binary code relative to full-scale (FS), and also the corresponding voltage level for each code (assuming a +10 V full-scale converter. The Gray code equivalent is also shown, and will be discussed ... | Original |
11 pages, |
4 bit adc base-10 bcd to gray code conversion binary to gray code converter Gray to BCD converter BCD Gray Converter bcd to gray code converter MT-009 MT-009 abstract |
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| Abstract: the 5-bit binary code as shown in Figure 6. SERIAL DATA TO RECEIVER ROTATING COMMUTATOR , errors associated with binary shadow masks were later eliminated by using a Gray code shadow mask as , conversion to binary code is only one least significant bit (LSB). In the case of midscale, note that only , the same effect if straight binary decoding techniques are used. In many cases, Gray code, or "pseudo-Gray" codes are used to decode the comparator bank output before finally converting to a binary code ... | Original |
15 pages, |
IEEE J. Solid State Circuits, Vol. SC GALVANOMETER DATA SHEET dc to gray code converter "computer labs" analog devices mercury thermometer analog galvanometer uA709 AM685 ua711 Fairchild uA711 4 bit gray to binary converter circuit MT-020 MT-020 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| . The device requires an external source to drive its reference ladder. Features 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One -speed low-power ADC General info The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and www.datasheetarchive.com/files/philips/pip/tda8764a_1.html |
Philips | 23/04/2003 | 3.22 Kb | HTML | tda8764a_1.html |
| . The device requires an external source to drive its reference ladder. Features 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9 General info The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter -bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and www.datasheetarchive.com/files/philips/pip/tda8764a_1-v2.html |
Philips | 06/06/2005 | 3.99 Kb | HTML | tda8764a_1-v2.html |
| external source to drive its reference ladder. 10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 5 MHz full The TDA8764A TDA8764A TDA8764A TDA8764A is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded www.datasheetarchive.com/files/philips/pip/tda8764a_1-v1.html |
Philips | 14/02/2002 | 9.61 Kb | HTML | tda8764a_1-v1.html |
| "thermometer code" is encoded, usually in binary or gray code, to obtain an N-bit digital word which represents Rosaria Tursi, Data Conversion Systems Abstract Â- A 100-MS/s 8-b CMOS analog-to-digital converter (ADC 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the reference degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35- m m CMOS process, with double-poly capacitors and no low-threshold devices. Index Terms Â- Analog-to-digital converters www.datasheetarchive.com/files/national/htm/nsc02534.htm |
National | 28/06/2001 | 27.08 Kb | HTM | nsc02534.htm |
| FPSLIC. IP Core Macro Generator Gray Code (3 pages, updated 1/02) Parameterized IP Core Application Note describes our enabling technology to make adaptive hardware possible for electronics systems describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer /01) Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. See Software section to download pwm.zip . Implementing a Single-coefficient Multiplier (5 www.datasheetarchive.com/files/atmel/atmel/prod100.htm-v1.bak |
Atmel | 07/05/2002 | 69.66 Kb | BAK | prod100.htm-v1.bak |
| FPSLIC. IP Core Macro Generator Gray Code (3 pages, updated 1/02) Parameterized IP Core Application Note describes our enabling technology to make adaptive hardware possible for electronics systems describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer /01) Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. See Software section to download pwm.zip . Implementing a Single-coefficient Multiplier (5 www.datasheetarchive.com/files/atmel/atmel/prod100-v6.htm |
Atmel | 07/05/2002 | 69.66 Kb | HTM | prod100-v6.htm |
| in the HDL Editor. To add the HEX2LED Converter template code, click the Use button in the Language Assistant while the HEX2LED Converter template is selected. The code is automatically placed in the diagram into either VHDL, Verilog or ABEL code. The resulting HDL file is finally synthesized to adds the symbol to the SC Symbols toolbox. To view the HDL code which the State Editor produced provides source code to convert a 4-bit value to 7-segment LED display format. Figure 4.25 HDL Language www.datasheetarchive.com/files/xilinx/docsan/fqs/fqs4_4.htm |
Xilinx | 12/11/1998 | 64.77 Kb | HTM | fqs4_4.htm |
| more efficient programs that need to deal with binary input and output conditions inherent in , which permits you to bootstrap code into the RAM to get underway. The loader and on-chip RAM first), and is also binary compatible. The XA is more of a 16 bit micro which also happens to for the MCS-251 MCS-251 MCS-251 MCS-251. The Philips XA is not a drop-in replacement for the 8051. Binary code with you in order to use the 16 bit operations - these are preceded by an escape code (A5H), the www.datasheetarchive.com/files/atmel/atmel/software/8051.faq |
Atmel | 18/05/1998 | 154.99 Kb | FAQ | 8051.faq |
| -in replacement for the 8051. Binary code compatibility is nice, you can move right up to a more powerful efficient programs that need to deal with binary input and output conditions inherent in digital a loader in ROM, which permits you to bootstrap code into the RAM to get underway more of a 16 bit micro which also happens to be source code compatible. One can argue the merits existing designs, and the binary compatibility truly preserves users investment in code and tools www.datasheetarchive.com/files/atmel/atmel/software/8051inf-v1.txt |
Atmel | 18/05/1998 | 151.46 Kb | TXT | 8051inf-v1.txt |
| -in replacement for the 8051. Binary code compatibility is nice, you can move right up to a more powerful efficient programs that need to deal with binary input and output conditions inherent in digital a loader in ROM, which permits you to bootstrap code into the RAM to get underway more of a 16 bit micro which also happens to be source code compatible. One can argue the merits existing designs, and the binary compatibility truly preserves users investment in code and tools www.datasheetarchive.com/files/atmel/atmel/software/8051inf.txt |
Atmel | 30/01/2000 | 151.46 Kb | TXT | 8051inf.txt |