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LTC2925IUF#PBF Linear Technology LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
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LTC4245CG Linear Technology LTC4245 - Multiple Supply Hot Swap Controller with I<sup>2</sup>C Compatible Monitoring; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2925IGN#TRPBF Linear Technology LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC4245CG#PBF Linear Technology LTC4245 - Multiple Supply Hot Swap Controller with I<sup>2</sup>C Compatible Monitoring; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2925IUF#TR Linear Technology LTC2925 - Multiple Power Supply Tracking Controller with Power Good Timeout; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

atm header-error-check multiple bit

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Abstract: RCKI, beginning with the first tw o bytes of the ATM header. W hen EN155 is high (155.52-M bit/s , is low (622.08-M bit/s operation), ATM cells are clocked into the TNETA1600 through T D 0 -T D 1 5 , least-significant bit. TW Ã' I Transm it write enable. A low level on TW E enables the writing of ATM cells , eight bytes during 622.08-M bit/s operation) from the ATM -layer device without overflowing the transm , byte (or first two bytes in 622.08-M bit/s operation) of an incoming ATM cell on the transm it-cell -
OCR Scan
08-MBIT/S 52-MBIT/S SDNS036

transmit g1

Abstract: STM 1 5A2 bit. TWE I Transmit write enable. A low level on TWE enables the writing of ATM cells into , (or first two bytes in a 16-bit cell interface) of an ATM cell. Once the input FIFO receives a high , TNETA1600 SONET/SDH ATM RECEIVER/TRANSMITTER FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION , Frames Carrying ATM Cells; Including: ­ Frame Scrambling/Descrambling ­ Pointer Processing ­ ATM-Cell , -Byte ATM Headers of Incoming ATM Cells D D D D Separate Serial Receive- and Transmit-Data
Texas Instruments
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transmit g1 STM 1 5A2 TNETA151 TD15 TNETA1610 TNETA1611

IDT77155

Abstract: 4413 bit is set in the Status Register. ISAMs are two ATM cells deep, so that the next ATM cell can , 3/1/99 - Section 2, Page 11 Section 2 2.3.2 ATM Cell (53 Byte) DPI Bit Ordering The following figures provide examples of the ATM Cell bit ordering in various DPI configurations. 53 Byte ATM Cell - (8 Bit Utopia) msb#7 3 3 lsb#0 GFC VPI 11 3 7 7 53 Byte ATM Cell - (4 , Byte ATM Cell - (8 Bit DPI) Port#0 msb#3 lsb#0 Port#1 msb#3 lsb#0 msb#7 Byte 0 3
Integrated Device Technology
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IDT77V400 IDT77V500 IDT77155 4413 IDT77V550 IDT79R36100
Abstract: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE , PCBE7 PREQ64 PACK64 PAD0 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT , , TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST , TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , 655303 · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT Texas Instruments
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64-BIT

TNETA1570

Abstract: asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a 64-bit peripheral component , odd-parity bit over SEGDATA7 -SEGDATA0. ATM mode SEGPAR SEGPAR (TXPAR) is the odd-parity bit over , PHY mode RESPAR (TXPAR) is the odd-parity bit over RESDATA7 -RESDATA0. ATM mode RESPAR , 32-bit/64-bit PCI-bus interface. The interface to the ATM layer is the UTOPIA interface , the DMA entry is loaded into the internal transmit FIFO. The EOP bit in the ATM header is set for the
Texas Instruments
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64BIT

be46

Abstract: TNETA1570 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , , TEXAS 75265 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST , · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT , SEGDATA7 ­ SEGDATA0. ATM mode SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7 ­ SEGDATA0
Texas Instruments
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be46

PAD31

Abstract: t1624 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE SDNS033B ­ JUNE , , TEXAS 75265 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST , · DALLAS, TEXAS 75265 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT , SEGDATA7 ­ SEGDATA0. ATM mode SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7 ­ SEGDATA0
Texas Instruments
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PAD31 t1624
Abstract: TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64ÄBIT PCIÄHOST INTERFACE , asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a 64-bit peripheral component , '¢ 3 TNETA1570 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64ÄBIT PCIÄHOST INTERFACE , odd-parity bit over SEGDATA7 â'SEGDATA0. ATM mode SEGPAR SEGPAR (TXPAR) is the odd-parity bit over , ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64ÄBIT PCIÄHOST INTERFACE SDNS033B â' JUNE Texas Instruments
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