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CA3240EZ Intersil Corporation Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output; PDIP8; Temp Range: -40° to 85°C
EL1517IS-T7 Intersil Corporation DUAL LINE DRIVER, PDSO8, SO-8
EL1517ISZ-T13 Intersil Corporation DUAL LINE DRIVER, PDSO8, SO-8
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EL1517ISZ-T7 Intersil Corporation DUAL LINE DRIVER, PDSO8, SO-8

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Part : DEM 1024600A TMH-PW-N Supplier : Display Elektronik Manufacturer : TME Electronic Components Stock : 2 Best Price : $54.84 Price Each : $64.99
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atm header error checking

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: (PLCP) functions and provides for the generation and checking of AAL1/3/4/5 formatted ATM payloads. In , header. Error detection and correction can be provided on the header. A 32-bit masking function is , checking · Separate statistics port · Access to data at each level of processing: PLCP ATM cells, or , network access products CN8223 Multi-Rate ATM PHY ATM Receiver/Transmitter with UTOPIA The CN8223 with UTOPIA (Universal Test and Operations Physical Interface ATM) bus provides a single Conexant Systems
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BP Saturn PB24
Abstract: (B-ISDN) functions of the Transmission Convergence (TC) sublayer. · ATM Header Error Correction (HEC) byte generation/checking · HEC-based cell delineation Line Framer 1 Line Framer 2 TDM Highways · Cell header single error correction/ multiple error detection · Cell , )/Loss of Cell Delineation (LCD) status UTOPIA Level 2 ATM Layer Function Direct cell , 25 MHz UTOPIA Level 2 with parity generation and checking · Supports independent or common Modelware
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error correction code in vhdl E1 vhdl Field Programmable Gate Arrays cell broadband LeonardoSpectrum AP97-050FPGA DS98-022 DS98-163-1
Abstract: ATM and SMDS cell modes 4 FIFO ports with header screening, formatting, and transmit priority , .832 Header Error Control (HEC) alignment. The CN8223 parallel line interface allows octet recovery , CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Conexant Systems
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n8223 N-822 AD6116 CN8223EPF 78P7200 BT8222EPFE TR-TSV-000772 TR-TSV-000773 TR-NWT-000253 T1S1/92-185
Abstract: ATM and SMDS cell modes 4 FIFO ports with header screening, formatting, and transmit priority , framing overhead or G.832 Header Error Control (HEC) alignment. The CN8223 parallel line interface allows , CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Conexant Systems
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BT8222KPF e3 frame formatter
Abstract: TAXITM or external T1/E1 framers ATM and SMDS cell modes 4 FIFO ports with header screening , framing overhead or G.832 Header Error Control (HEC) alignment. The CN8223 parallel line interface allows , Error insertion Conexant 100046D CN8223 1.0 Product Description ATM Transmitter/Receiver , CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Conexant Systems
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bip 109
Abstract: or FIFO Interface 1 ATM UNI 1 8 Header Filter Cell Validation ATM Layer , and error conditions under microprocessor control. 1-6 Conexant N8222DSG Bt8222 ATM , Scrambling · ATM Payload Scrambling · Error Insertion 1.4.1 Cell Generation Functions The Bt8222 ATM cell , -octet payload segments into 53-octet ATM cells, which includes generation of appropriate header octets, HEC, and , Bt8222 ATM Transmitter/Receiver with UTOPIA Interface The Bt8222 ATM Transmitter/Receiver with Conexant Systems
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N8222 28-22-21 bt8222
Abstract: -Cell Buffer Port Rate and Priority Control Idle Cell Tx/Rx Per-Port ATM Header Screening 48-, 52-, 53-, and 57 , Each cell is sent to a buffer to allow for header processing before being output to the ATM interface , llOii) 1.0 Product Description - The Bt8222 ATM Physical Interface (PHY) device is a receiver/transmitter which converts several types of frames to ATM cells and vice versa. The device , octet-wide data to the Bt8222 via the UTOPIA or FIFO ports. This data is assem bled into ATM cells by the PHY -
OCR Scan
L8222 ssy 1920
Abstract: discard · The header of an input cell, after any error correction, is compared with the header contents , correction mask required in order to correct a single bit error in the header. The descrambler module , CRC check specified by the ATM Forum. Upon detection of a possible valid header, the state machine , CRC Header Error Check (HEC) sequence recorded in the 5th byte of each cell. Upon a successful match , Detection. In the Correction state, an attempt is made to correct a cell header with a single bit error Xilinx
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XC4000XL CRC-32 CRC-10 LCD module in VHDL vhdl code CRC32 vhdl code for scrambler descrambler PC84 CC-200 XC4010XL-09
Abstract: validity of the current cell delineation by checking the CRC Header Error Check (HEC) sequence recorded in , delineation indication Idle cell discard The header of an input cell, after any error correction, is compared with the header contents specified in ATM UNI 3.1 for an idle cell; such detected idle cells are , correct a single bit error in the header. The descrambler module descrambles only payload octets using , scrambler procedure specified in ATM UNI 3.1. When an input cell header matches the pattern specified for Xilinx
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Cell phone schematic circuit atm header-error-check multiple bit cell phone scrambler-descrambler
Abstract: an ATM cell contain overhead information, such as destination address, and an error control byte , header error control (HEC) block. The HEC is an 8-bit cyclic redundancy code (CRC), which detects transmission errors in the ATM cell header. ATM Cell Definition Figure 2 shows the definition of the ATM , bytes of addressing and 1 byte of error checking information. The addressing information is one of two , header; the 48-byte payload is not included. The received ATM cell is read from the FIFO at 66 MHz Actel
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AC100 FPGA based dma controller using vhdl ATM machine using microprocessor Applications of "XOR Gate" vhdl code for 4 channel dma controller Controller System NIC design of dma controller using vhdl 3200DX 32200DX
Abstract: an error control byte. When reading the ATM cell from the receive FIFO, the first 5 bytes of the cell are directed to the header error control (HEC) block. The HEC is an 8-bit cyclic redundancy code (CRC), which detects transmission errors in the ATM cell header. ATM Cell Definition An ATM network , 1 byte of error checking information. The addressing information is one of two different types, the , chaining, burst processing, and bandwidth management. Header Error Control Design compute the full 8 Actel
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Dual-Port V-RAM 8 bit XOR Gates signal path designer
Abstract: an ATM cell contain overhead information, such as destination address, and an error control byte , header error control (HEC) block. The HEC is an 8-bit cyclic redundancy code (CRC), which detects transmission errors in the ATM cell header. ATM Cell Definition Figure 2 shows the definition of the ATM , bytes of addressing and 1 byte of error checking information. The addressing information is one of two , header; the 48-byte payload is not included. The received ATM cell is read from the FIFO at 66 MHz Actel
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asynchronous fifo vhdl fpga
Abstract: Error Count Register ­ Byte 3 0xN715 Receive ATM Cell Insertion/Extraction Memory Data Register ­ , FCS Error Count Register ­ Byte 1 0xN717 Receive ATM Cell Insertion/Extraction Memory Data , Receive ATM Controller - Test Cell Header ­ Byte 1 0x00 0xN721 Receive ATM Controller ­ Test Cell Header ­ Byte 2 0x00 0xN722 Receive ATM Controller ­ Test Cell Header ­ Byte 3 0x00 0xN723 Receive ATM Controller ­ Test Cell Header ­ Byte 4 0x00 0xN724 Receive ATM Controller ­ Test Cell Exar
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XRT94L33 led cross reference 0x0382 0x1151 0x1738 0X176C
Abstract: and DS1/E1payloads. · Supports core/payload header error correction and checking along with Tx header , AMUR Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor CONCEPT , Frame Relay, PPP, GFP and ATM data mappings for up to 1024 channels with DS-0 granularity. Additionally , 2 channel m apper 1024 Channels HDLC ATM 168 Ch GFP 4-port SPI-3 8/32-bit 104M Hz OC12 , to PDH framer and 1K Channels HDLC/ATM/GFP processor CONCEPT Product Brief Part Number S1215 Applied Micro Circuits
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AF-UNI-0010 amcc part marking remote control rx tx STS-12/STM-4 P3705
Abstract: Bt8222 can transmit alarm and error conditions under microprocessor control. 1.4 ATM Cell Processing , UTOPIA Port with 4-Cell Buffer Port Rate and Priority Control Idle Cell Tx/Rx Per-Port ATM Header , host data is assembled into ATM cells and then formatted for serial line transmission by the line , line framers and passed to the ATM cell processing block. Octet data is then aligned into ATM cells , HECVPLCP ATM cell alignment block accepts octet data from the line framer block. It generates cells for -
OCR Scan
GG1Q 0G1G073 001DG74 RXIN13
Abstract: consolidation for up to 4K multicast branch points on ingress and egress. s Performs egress ATM header , performs ingress ATM layer header processing. It maps the ingress port address, VPI and VCI into one of , error checking codes for diagnostic purposes. The receive interface controls the reception of cells from the PI-Sched device. The receive interface checks the incoming cells error checking code and , header. Header Translation On egress, the ATM header's VPI (VP switching) or VPI/VCI (VC switching Agere Systems
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TPAT640 tag 8833 Internal diagram of ic 7495 OC-48 30L-15P-BA PN00-036ATM
Abstract: Creation of 53-byte ATM cells by adding a header to the SAR PDU · Encoding of the AUU parameter to indicate the end of the SAR SDU Exception conditions include: · Error in Cell syntax: bad header CRC , Generation of sequence number · CRC-3 and parity in transmit direction · Checking of all header , SARA-ProTM ATM AAL0/1/3/4/5 Segmentation and Reassembly TXC-05551-SCCA PRODUCT INFORMATION SARA-ProTM ATM AAL0/1/3/4/5 SEGMENTATION AND REASSEMBLY SOLUTION INTRODUCTION TranSwitch has introduced the TranSwitch
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TXC-05551-SCBA TXC SPECIFICATION TXC-05551 TXC-05551-SDAN TXC-21252 TXC-05551-SAA1 TXC-05551-SAA2 TXC-05551-SSAU
Abstract: reassembled using the ATM adaptation layer information fields. Per-cell and per-packet error checking , CRC per connection APPLICATIONS = â'¢ B-ISDN header and CRC generation and checking â'¢ Routers , SARA-S and SARA-R Devices ATM/SMDS Segmentation Controller, TXC-05501 ATM/SMDS Reassembly , Controller (TXC-05501) segments packets into ATM/SMDS cells, up to 8000 simultaneously The TranSwitch SARA VLSI chip set provides a versatile, high performance implementation of the ATM adaptation layer -
OCR Scan
TXC-05601 TXC-02050 TXC-02301 TXC-02302 TXC-03003 TXC-03401
Abstract: Physical Interface ATM) Level 2 interface provides ATM service termination according to ATM Forum, ITU, and ANSI standards, and allows for the generation and checking of AAL1/5 formatted ATM payloads. In , error events as specified by the ATM Forum for both B-ICI and UNI interfaces. · Glueless support for , . ATM also plays a key role in next generation B3 Calculated, error insertion Checked, errors , network access products RS825x 155 Mbps ATM PHY 155 Mbps ATM PHY with Clock Recovery Conexant Systems
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RS8250 RS8254 RS8251 RS8255 GR-253-CORE ATM machine working circuit diagram RS825
Abstract: on demand register *CPM 9. Erroneous reception of ATM cell. *CPM 10. Error in ATM underrun report , in indicating IDLE between frame. *CPM 27. Error in heartbeat checking in FCC. CPM 37. Requirement , Fast Ethernet. CPM 8. Error using FCC transmit on demand register CPM 9. Erroneous reception of ATM cell. CPM 10. Error in ATM underrun report. CPM 11. False indication of shared flag. CPM 13. Error , checking in FCC. CPM 37. Requirement for software to disable FCC after Error CPM 38. Heart beat error and Motorola
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MPC8260 1K23A MPC8260CE SIU12 XPC8260 MPC8260CE/D MPC826 XPC8255 SIU11
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