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altera stratix II fpga

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Abstract: capable of up to 100 Mbits per second data rate in an Altera Stratix II FPGA and supports all codes , Altera Stratex II FPGA; however, an ASIC core is also available upon request. LDPC codes provide ... Original
datasheet

2 pages,
51.6 Kb

altera stratix II fpga Encoder/Decoder DVB LDPC decoder Comtech Aha Decoder DVB LDPC aha LDPC Codes LDPC DVB-S2 LDPC encoder datasheet abstract
datasheet frame
Abstract: AT91CAP9A AT91CAP9A Dev Kit Altera® Stratix® II FPGA (equivalent 500K ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA15 AT91CAP9HA15 Dev Kit Altera® Stratix® III FPGA (equivalent 1.5M ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA20 AT91CAP9HA20 Dev Kit Altera® Stratix® III FPGA (equivalent 2M ASIC , Mezzanine Board · AT91CAP9 AT91CAP9 ARM926EJ-S-based microcontroller · Altera® Stratix® III FPGA, equivalent to 2 , microcontroller standard product, coupled to a high-density FPGA, integrating the equivalent of 2 million ASIC ... Original
datasheet

2 pages,
609.43 Kb

DDR PHY ASIC ARM926EJ-S AT91CAP9 AC97 Audio Interfaces cap touch panel controller atmel cap touch controller AT91CAP9A AT91CAP9HA20 AT91CAP9HA15 AT91CAP9HA-DK AT91CAP9HA-DK abstract
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Abstract: Virtex 5 FPGA has an operating range of 0.95V to 1.05V and the Altera Stratix II FPGA has an operating , Switching Regulator Microcontroller, Processor, Digital ASIC, Memory, DSP, FPGA Power for Core , Digital Integrated Circuits Does the system include a DSP, FPGA, microprocessors, or memory? Design , system include a DSP, FPGA, microprocessors, or memory? G What is the design priority? Recommended ... Original
datasheet

4 pages,
226.82 Kb

LP5550 TSSOP-28 details of lm2596 12v 10a regulator ic LM2675 48v 10A regulator lm2596 REGULATOR SMD 12V REGULATOR 48V TO 24 switching regulator 12v 3A linear regulator 48V 48v to 24v buck sot23-5 LDO Regulator Controller datasheet abstract
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Abstract: magnitude more multipliers, and flexible word size. For example, the new Altera® Stratix® II FPGA family , architecture. This paper will discuss the medical application developed by Mango DSP using Altera's Stratix , five Altera Stratix EP1S30 EP1S30 FPGAs with 2-GBytes SDRAM memory. The FPGAs are connected to four , Altera Stratix FPGAs Figure 4. MangoDSP Harrier cPCI DSP Board, featuring Altera Stratix FPGAs , FPGA Co-Processing Solutions for High-Performance Signal Processing Applications Tapan A. Mehta ... Original
datasheet

6 pages,
310.87 Kb

Tomography slip ring Scientific Imaging Technologies mixed signal fpga datasheet fpga radiation disadvantages of multipliers CF-COP031505-1 18X18 CF-COP031505-1 abstract
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Abstract: pins, and memory. Table 1 shows the features of Altera's Stratix II FPGA family [1] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Stratix II Family Device , up-conversion is dependent on the clock speed of the digital device. For example, Altera's Stratix® II FPGAs , Corporation, Stratix II Data Sheet, www.altera.com [2] Analog Devices, AD9736 AD9736 Data Sheet, www.analog.com , DIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM Rob Pelt Altera Corporation 101 ... Original
datasheet

5 pages,
234.67 Kb

AD9736 CF-POL031505-1 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 fpga da altera Fliege MB86064 nyquist CF-POL031505-1 abstract
datasheet frame
Abstract: a matrix multiplication design running in an Altera® Stratix® II EP2S180 EP2S180 FPGA. In [1], the author , design of a double-precision matrix multiplier targeted to and run in an Altera Stratix II FPGA , +- + R R As with the Stratix II FPGA, by using the 1:1 ratio of adds and multiplies and the , performance from a real Stratix II EP2S180 EP2S180 implementation of the AB matrix multiplication with data from a , peak FP analysis is repeated for the Stratix III EP3SE260 EP3SE260 FPGA. Table 3 shows the resources for the ... Original
datasheet

6 pages,
663.39 Kb

EP2S180 clock select adder with sharing EP2S180 abstract
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Abstract: leading-edge Altera® Stratix® II FPGA into a dual Opteron-based system. The FPGA coprocessor module can be , The Altera Stratix II EP2S180 EP2S180 FPGA used as the FPGA coprocessor in this study has 14,3520s ALUTs in , Clock- d2 Clock- d3 When implemented in the Altera Stratix II FPGA, the design will require about 180 , Stratix II FPGA represents a significant improvement in its adaptive logic module (ALM) design [1]. While , of magnitude. References 1. Altera Corporation, Stratix II Device Handbook, 2006 ... Original
datasheet

18 pages,
1134 Kb

WP-01035-1 EP2S180 AMD64 XD1000 introduction to vlsi CS9222 Transistor Substitution Data Book 1993 384-PE 384-PE abstract
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Abstract: research, read Altera's Stratix II FPGA Architecture (the foundation of Stratix IV architecture) white , that enable Stratix IV FPGAs to lower power consumption, see Altera's 40-nm FPGA Power Management and , available, refer to Altera's Stratix IV FPGA Handbook. Conclusion Migrating to smaller geometries , Programmable Power Technology, Altera's 40-nm Stratix® IV FPGAs not only provide increased functionality and , data showing Altera® Stratix IV FPGAs are 35 percent faster than Virtex-5 FPGAs, and detailed ... Original
datasheet

16 pages,
1974.08 Kb

XC5VLX330 VIRTEX-5 DDR2 XC5VLX50 technical spec virtex 5 fpga based image processing datasheet abstract
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Abstract: performance FPGAs such as Altera's Stratix II FPGA, are usually used at the heart of high-bandwidth systems , architectural layout of the industry leading Stratix II FPGA [5]. Figure 4: Stratix II Device Floorplan , , can be effectively addressed with FPGAs. Altera's Stratix II and Cyclone II FPGAs are considered as a , Altera's Stratix II platform [5], contain embedded DSP blocks, TriMatrixTM memory architecture, innovative , evolving standards. Altera's Stratix II FPGAs provide the ability to easily evolve WiMAX systems in ... Original
datasheet

15 pages,
540 Kb

qpsk modulation VHDL CODE simulink mimo LMS 16 QAM adaptive modulation matlab LMS adaptive filter model for FPGA vhdl code for ldpc lms algorithm using vhdl code matlab code for mimo ofdm LMS simulink MIMO OFDM Matlab code OFDM MRC Matlab code simulink model adaptive beamforming datasheet abstract
datasheet frame
Abstract: , and memory. Table 1 shows the features of Altera's Stratix II FPGA family [2] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Altera's Stratix II Family , Corporation, Stratix II Data Sheet, www.altera.com [3] The Mathworks, Simulink Data Sheet , IMPLEMENTING A FPGA-BASED BROADBAND MODEM USING MODEL-BASED DESIGN Rob Pelt Altera Corporation , polyphase modem using current FPGA technology. 3. FPGA OVERVIEW Before describing the implementation of ... Original
datasheet

7 pages,
207.52 Kb

Pelt EP2S180 EP2S30 EP2S60 EP2S90 EP2S15 1E-008 8E-009 FIR filter matlaB simulink design DAC 5754 FPGA FAMILY baseband processor simulink CP-BRDBND05-1 CP-BRDBND05-1 abstract
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: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II Stratix III, Stratix IV, Stratix GX, Stratix II GX node-locked licence (ET1810 ET1810 ET1810 ET1810) ET1812 ET1812 ET1812 ET1812 EtherCAT IP core licence for Altera FPGA ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 | EtherCAT IP core for Altera and Xilinx FPGAs The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA functionality is freely configurable. The IP core can be combined with own FPGA designs and offers the option of
www.datasheetarchive.com/files/beckhoff/catalog/english/ethercat/et1810_et1815.htm
Beckhoff 10/11/2009 7.56 Kb HTM et1810_et1815.htm
verwendet werden: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix IV, Stratix GX, Stratix II GX, Arria GX. Der EtherCAT-Xilinx-IP-Core kann mit folgenden FPGAs verwendet werden ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 | EtherCAT-IP-Core für Altera- und Xilinx-FPGAs Der EtherCAT-IP-Core ermöglicht es, auf einem FPGA (Field Programmable Gate Array - d. h. ein Gerät, das programmierbare logische FPGA-Designs kombiniert werden und bietet unter anderem die Möglichkeit, über das Avalon (Altera)/OPB (Xilinx
www.datasheetarchive.com/files/beckhoff/catalog/german/ethercat/et1810_et1815.htm
Beckhoff 10/11/2009 7.8 Kb HTM et1810_et1815.htm
No abstract text available
www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (CHANGELOG)
Xilinx 11/11/2004 9180.01 Kb ZIP xapp542.zip
No abstract text available
www.datasheetarchive.com/download/66603255-30108ZC/cortex-m_workshop_tour.zip (Cortex M Architecture.pdf)
ARM 29/06/2009 11820.25 Kb ZIP cortex-m_workshop_tour.zip