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Part Manufacturer Description Datasheet BUY
STRATIXIV-GX-REF Texas Instruments Stratix IV GX Development Kit visit Texas Instruments
PMP2543 Texas Instruments Altera Cyclone III visit Texas Instruments
PMP8571 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC visit Texas Instruments
BEMICRONIO-2-PROCSDK-REF Texas Instruments Altera/Arrow BeMicro Nios II Processor SDK with DP83848 in USB Stick Format visit Texas Instruments
PMP8571.3 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC (1.5V@3A) visit Texas Instruments
PMP8571.1 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC (2.5V@3.5A) visit Texas Instruments

altera stratix II fpga

Catalog Datasheet MFG & Type PDF Document Tags

LDPC encoder

Abstract: DVB-S2 capable of up to 100 Mbits per second data rate in an Altera Stratix II FPGA and supports all codes , Altera Stratex II FPGA; however, an ASIC core is also available upon request. LDPC codes provide
Comtech AHA
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AT91CAP9HA15

Abstract: AT91CAP9HA20 AT91CAP9A Dev Kit Altera® Stratix® II FPGA (equivalent 500K ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA15 Dev Kit Altera® Stratix® III FPGA (equivalent 1.5M ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA20 Dev Kit Altera® Stratix® III FPGA (equivalent 2M ASIC , Mezzanine Board · AT91CAP9 ARM926EJ-S-based microcontroller · Altera® Stratix® III FPGA, equivalent to 2 , microcontroller standard product, coupled to a high-density FPGA, integrating the equivalent of 2 million ASIC
Atmel
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atmel cap touch controller Audio Interfaces DDR PHY ASIC cap touch panel controller AC97 ARM926EJ-S AT91CAP9HA-DK ARM926EJ-STM-

Digital Signal Processors

Abstract: Scientific Imaging Technologies magnitude more multipliers, and flexible word size. For example, the new Altera® Stratix® II FPGA family , architecture. This paper will discuss the medical application developed by Mango DSP using Altera's Stratix , five Altera Stratix EP1S30 FPGAs with 2-GBytes SDRAM memory. The FPGAs are connected to four , Altera Stratix FPGAs Figure 4. MangoDSP Harrier cPCI DSP Board, featuring Altera Stratix FPGAs , FPGA Co-Processing Solutions for High-Performance Signal Processing Applications Tapan A. Mehta
Altera
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Digital Signal Processors Scientific Imaging Technologies disadvantages of multipliers fpga radiation mixed signal fpga datasheet slip ring 800-EPLD

Fliege

Abstract: nyquist pins, and memory. Table 1 shows the features of Altera's Stratix II FPGA family [1] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Stratix II Family Device , up-conversion is dependent on the clock speed of the digital device. For example, Altera's Stratix® II FPGAs , Corporation, Stratix II Data Sheet, www.altera.com [2] Analog Devices, AD9736 Data Sheet, www.analog.com , DIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM Rob Pelt Altera Corporation 101
Altera
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Fliege nyquist MB86064 CF-POL031505-1 frequency sampling method of digital fir filter fpga da altera

voltage regulator, 0 to 48V, 0 to 15 amps

Abstract: 12v 10A regulator band gap of 1.2V and require tight operating tolerances. For example, the Xilinx Virtex 5 FPGA has an operating range of 0.95V to 1.05V and the Altera Stratix II FPGA has an operating range of 1.15V to 1.25V , Switching Regulator Microcontroller, Processor, Digital ASIC, Memory, DSP, FPGA Power for Core , the system include a DSP, FPGA, microprocessors, or memory? Design Considerations Efficiency , DSP, FPGA, microprocessors, or memory? G What is the design priority? Recommended topologies
National Semiconductor
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voltage regulator, 0 to 48V, 0 to 15 amps 12v 10A regulator 24v 12v 10A regulator regulator 48V simple switcher 24V to 15V REGULATOR IC LLP-10 LM2770 LP38856/9 LP5951 SC70-5
Abstract: innovative and flexible feature set provided in TREX-S2 module, using large Altera Stratix II FPGA devices , Terasic TREX-S2 TREX-S2 Stratix II FPGA Module Data Book TREX-S2 Document Version 1.3 , Figure 1.1 shows the photo of the TREX-S2 FPGA module. The important features are listed below: Altera Stratix II FPGA (60-180) with 1020 FBGA package Provides 695 Free IO pins via high-speed connectors. 12 , . 25 ii Introduction 1 Chapter Chapter 1 Introduction TREX-S2 is an innovative FPGA TerasIC Technologies
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EP2S60 EPCS16SI16N PI3VT3245LE SFC-135-T2-L-D-A EP2S180 EPCS64SI16N

clock select adder with sharing

Abstract: EP2S180 Altera® Stratix® II EP2S180 FPGA. In [1], the author references the double-precision general matrix , to and run in an Altera Stratix II FPGA. Further Information 1. Dave Strenski, "FPGA , the Stratix II FPGA, by using the 1:1 ratio of adds and multiplies and the same resource utilization , Stratix II EP2S180 implementation of the AB matrix multiplication with data from a locally attached SRAM , for the Stratix III EP3SE260 FPGA. Table 3 shows the resources for the EP3SE260, while Table 4 shows
Altera
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clock select adder with sharing

abstract for wireless technology in ieee format

Abstract: abstract for mobile bug . State-of-the-art high-end, high performance FPGAs such as Altera's Stratix II FPGA, are usually used at the heart , an overview of the architectural layout of the industry leading Stratix II FPGA [5]. Figure 4 , previous section, high performance FPGAs such as Altera's Stratix II platform [5], contain embedded DSP , Altera Corporation Accelerating WiMAX System Design with FPGAs Figure 5: Stratix II DSP Block , System Design with FPGAs Altera Corporation Figure 6: Remote Upgrade Systems with a Stratix II
Altera
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abstract for wireless technology in ieee format abstract for mobile bug LMS adaptive filter simulink model simulink model adaptive beamforming mimo model simulink matlab code for mimo ofdm stc

Transistor Substitution Data Book 1993

Abstract: CS9222 leading-edge Altera® Stratix® II FPGA into a dual Opteron-based system. The FPGA coprocessor module can be , The Altera Stratix II EP2S180 FPGA used as the FPGA coprocessor in this study has 14,3520s ALUTs in , Clock- d2 Clock- d3 When implemented in the Altera Stratix II FPGA, the design will require about , Stratix II FPGA represents a significant improvement in its adaptive logic module (ALM) design [1]. While , of magnitude. References 1. Altera Corporation, Stratix II Device Handbook, 2006
Altera
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XD1000 Transistor Substitution Data Book 1993 CS9222 introduction to vlsi WP-01035-1 require-40 384-PE

baseband processor simulink

Abstract: simulink design using FIR filter method , and memory. Table 1 shows the features of Altera's Stratix II FPGA family [2] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Altera's Stratix II Family , Corporation, Stratix II Data Sheet, www.altera.com [3] The Mathworks, Simulink Data Sheet , IMPLEMENTING A FPGA-BASED BROADBAND MODEM USING MODEL-BASED DESIGN Rob Pelt Altera Corporation , polyphase modem using current FPGA technology. 3. FPGA OVERVIEW Before describing the implementation of
Altera
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baseband processor simulink simulink design using FIR filter method DAC 5754 FPGA FAMILY FIR filter matlaB simulink design fir compiler Pelt

XC5VLX50 technical spec

Abstract: virtex 5 fpga based image processing For an in-depth description of the ALM design and research, read Altera's Stratix II FPGA Architecture , that enable Stratix IV FPGAs to lower power consumption, see Altera's 40-nm FPGA Power Management and , information on the resources available, refer to Altera's Stratix IV FPGA Handbook. Conclusion Migrating , Programmable Power Technology, Altera's 40-nm Stratix® IV FPGAs not only provide increased functionality and , data showing Altera® Stratix IV FPGAs are 35 percent faster than Virtex-5 FPGAs, and detailed
Altera
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XC5VLX50 technical spec virtex 5 fpga based image processing XC5VLX330 ddr2 sdram interface to virtex for image processing VIRTEX-5 DDR2

0.18um structured ASIC

Abstract: astro tools 2004 reveals that the highest density 90nm product, specifically, Altera's Stratix II FPGA device can , will be synthesized to an Altera Stratix FPGA and remapped to a HardCopy Structured ASIC. 5.1 Design , FPGAs 3.0 Background of Synopsys' DC FPGA Synthesis Tool and Altera's HardCopy Structured ASIC 3.1 Synopsys' DC FPGA 3.2 Altera HardCopy Structured ASIC 4.0 Designing an Altera HardCopy Device in a , 5.2 Synthesizing with DC FPGA 5.3 Setting up Quartus II Project 5.4 Quartus II Results for FPGA
Altera
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0.18um structured ASIC astro tools asic design flow N326 EP1S30F780C5 altera 48 fpga CF-ASIC05-1

DDR3 pcb layout

Abstract: Micron TN-47-01 Stratix III FPGA interfacing with a 400-MHz DDR2 SDRAM unbuffered DIMM Altera Stratix II FPGA , Development Kit Board with DDR2 SDRAM DIMM Interface The Altera Stratix II FPGA is interfacing with a 267 , validation and testing of memory interfaces with Stratix II devices. © November 2009 Altera Corporation , Stratix II boards. The simulation files, Simulation Example are on the Altera website. Board Layout , obtained from the Stratix II Memory Board 2. The FPGA is using a 16 mA drive strength to drive the DDR2
Altera
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DDR3 pcb layout Micron TN-47-01 DDR3 pcb layout guide DDR3 pcb layout guidelines DDR3 phy DDR3 sodimm pcb layout

5AGX

Abstract: lpddr2 tutorial 69 Altera Product Catalog · 2011 · www.altera.com 3 Devices Stratix V GX FPGA , . 10 Altera Product Catalog · 2011 · www.altera.com Devices Stratix III E FPGA , · 2011 · www.altera.com 11 Devices Stratix II GX FPGA Features Stratix II GX FPGAs , . 2 . Stratix® FPGA Series. 3 . HardCopy® ASIC Series , Devices Stratix V GT FPGA Features www.altera.com/selector The following features, packages, and I
Altera
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5AGX lpddr2 tutorial EP4CE22F17 solomon 16 pin lcd display 16x2 Altera MAX V CPLD DE2-70 SG-PRDCT-11

v-by-one hs

Abstract: camera-link to 3G-SDI converter MLAB RAM. Altera Product Catalog · 2010 · www.altera.com 9 Devices Stratix II GX FPGA Features Stratix II GX FPGAs (1.2 V), 6.375-Gbps Transceivers1 EP2SGX60 EP2SGX90 , . Altera Product Catalog · 2010 · www.altera.com 19 Devices Arria II GX FPGA Package and I , . 2 . Stratix® FPGA series. .3 . HardCopy® ASIC Series , -in a sum or independent mode. Devices Stratix V FPGA Features www.altera.com/selector The
Altera
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v-by-one hs camera-link to 3G-SDI converter Netlogic camera-link to HDMI converter camera-link to hd-SDI converter serdes hdmi optical fibre

DDR3 pcb layout

Abstract: DDR2 sdram pcb layout guidelines Stratix III FPGA interfacing with a 400-MHz DDR2 SDRAM unbuffered DIMM Altera Stratix II FPGA , with DDR2 SDRAM DIMM Interface The Altera Stratix II FPGA is interfacing with a 267-MHz DDR2 SDRAM , Stratix II Memory Board 2 is a memory test board available only within Altera for the purpose of testing , memory interfaces with Stratix II devices. © July 2010 Altera Corporation Board Layout , . . . . . . . 2­14 DQS, DQ, and DM for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . .
Altera
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DDR2 sdram pcb layout guidelines DDR2 pcb layout DDR3 jedec JESD8-15A dimm pcb layout DDR3 DIMM 240 pin names

DDR3 DIMM 240 pinout

Abstract: DDR2 sdram pcb layout guidelines FPGA core fabric. (3) This register is not available for Altera megafunctions that use Stratix V , . . . . . . . . 2­1 OCT Support for Arria II GX, Stratix III, Stratix IV, and Stratix V Devices . . , Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II GX, Stratix III, Stratix IV, and , for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­14 Memory Clocks for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . .
Altera
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DDR3 DIMM 240 pinout DDR3 slot 240 pinout samsung ddr3 DDR3 ECC SODIMM Fly-By Topology DDR2 DIMM 240 pinout micron

digital clock project

Abstract: HC1S60F1020 5. Quartus II Support for HardCopy Stratix Devices H51014-3.4 Introduction Altera® HardCopy , eight weeks Altera's Quartus II software has built-in support for HardCopy Stratix devices. The , Architecture identical to Stratix FPGA Altera Corporation September 2008 5­3 Preliminary HardCopy , than Stratix FPGA in some devices Ordered through Altera part number Cannot be ordered, use the Altera Stratix FPGA part number Ordered by Altera part number Table 5­2 lists the resources
Altera
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digital clock project HC1S60F1020 digital clock project report to download sample project of digital signal processing digital clock project report fpga altera

HC1S80F1020

Abstract: digital clock project report 13. Quartus II Support for HardCopy Stratix Devices H51014-3.3 Introduction Altera , Architecture identical to Stratix FPGA Altera Corporation June 2007 13­3 Preliminary HardCopy , than Stratix FPGA in some devices Ordered through Altera part number Cannot be ordered, use the Altera Stratix FPGA part number Ordered by Altera part number Table 13­2 lists the resources , Preliminary Altera Corporation June 2007 HardCopy Design Flow Stratix FPGA for your design. The
Altera
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HC1S80F1020 HC1S40F780 digital clock project program

HC1S80F1020

Abstract: HC1S30F780 : Altera Corporation May 2007 Prototyping using a Stratix II FPGA for functional verification and , project revisions, Altera recommends that you maintain only one Stratix II FPGA revision once you have , Stratix II FPGA. Altera verifies that the HardCopy II Companion Device timing requirements are met in the , 4­1 "HardCopy Stratix Device Support" on page 4­35 Altera® HardCopy II devices feature 1.2-V, 90 , , you can leverage a Stratix II FPGA as a prototype and seamlessly migrate your design to a HardCopy II
Altera
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QII51004-7 HC1S30F780 electrical engineering projects encounter conformal equivalence check user guide AN432 EP2S130F1020C4 HC230F1020
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