NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| EP2SGX90FF40C5N | Altera Corporation | Stratix II GX FPGA 90K FPGA-40 | 
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| EP2S130F1020I5 | Altera Corporation | Stratix II FPGA 130K FBGA-1020 |
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| EP2S130F1508I5 | Altera Corporation | Stratix II FPGA 130K FBGA-1508 |
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| EP2SGX130GF40C5 | Altera Corporation | Stratix II GX FPGA 130K FPGA-40 |
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| EP2SGX130GF40C3N | Altera Corporation | Stratix II GX FPGA 130K FPGA-40 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: capable of up to 100 Mbits per second data rate in an Altera Stratix II FPGA and supports all codes , Altera Stratex II FPGA; however, an ASIC core is also available upon request. LDPC codes provide ... | Original |
2 pages, |
altera stratix II fpga LDPC decoder Encoder/Decoder DVB Comtech Aha LDPC aha Decoder DVB LDPC Codes LDPC LDPC encoder DVB-S2 datasheet abstract |
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| Abstract: AT91CAP9A AT91CAP9A Dev Kit Altera® Stratix® II FPGA (equivalent 500K ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA15 AT91CAP9HA15 Dev Kit Altera® Stratix® III FPGA (equivalent 1.5M ASIC gates) 1.8V Memory Board 3.3V Memory Board AT91CAP9HA20 AT91CAP9HA20 Dev Kit Altera® Stratix® III FPGA (equivalent 2M ASIC , Mezzanine Board · AT91CAP9 AT91CAP9 ARM926EJ-S-based microcontroller · Altera® Stratix® III FPGA, equivalent to 2 , microcontroller standard product, coupled to a high-density FPGA, integrating the equivalent of 2 million ASIC ... | Original |
2 pages, |
DDR PHY ASIC atmel cap touch controller AT91CAP9 ARM926EJ-S AC97 AT91CAP9A AT91CAP9HA20 AT91CAP9HA15 AT91CAP9HA-DK AT91CAP9HA-DK abstract |
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| Abstract: Virtex 5 FPGA has an operating range of 0.95V to 1.05V and the Altera Stratix II FPGA has an operating , Switching Regulator Microcontroller, Processor, Digital ASIC, Memory, DSP, FPGA Power for Core , Digital Integrated Circuits Does the system include a DSP, FPGA, microprocessors, or memory? Design , system include a DSP, FPGA, microprocessors, or memory? G What is the design priority? Recommended ... | Original |
4 pages, |
12v 10a regulator ic LM2595 TO220-7 package TSSOP-28 details of lm2596 lm2596 REGULATOR 48V TO 24 REGULATOR SMD 12V 48v 10A regulator switching regulator 12v 3A linear regulator 48V 48v to 24v buck sot23-5 LDO Regulator Controller datasheet abstract |
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| Abstract: magnitude more multipliers, and flexible word size. For example, the new Altera® Stratix® II FPGA family , architecture. This paper will discuss the medical application developed by Mango DSP using Altera's Stratix , five Altera Stratix EP1S30 EP1S30 FPGAs with 2-GBytes SDRAM memory. The FPGAs are connected to four , Altera Stratix FPGAs Figure 4. MangoDSP Harrier cPCI DSP Board, featuring Altera Stratix FPGAs , FPGA Co-Processing Solutions for High-Performance Signal Processing Applications Tapan A. Mehta ... | Original |
6 pages, |
Tomography slip ring Scientific Imaging Technologies mixed signal fpga datasheet fpga radiation CF-COP031505-1 18X18 CF-COP031505-1 abstract |
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| Abstract: pins, and memory. Table 1 shows the features of Altera's Stratix II FPGA family [1] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Stratix II Family Device , up-conversion is dependent on the clock speed of the digital device. For example, Altera's Stratix® II FPGAs , Corporation, Stratix II Data Sheet, www.altera.com [2] Analog Devices, AD9736 AD9736 Data Sheet, www.analog.com , DIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM Rob Pelt Altera Corporation 101 ... | Original |
5 pages, |
AD9736 CF-POL031505-1 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 fpga da altera Fliege MB86064 nyquist CF-POL031505-1 abstract |
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| Abstract: a matrix multiplication design running in an Altera® Stratix® II EP2S180 EP2S180 FPGA. In [1], the author , design of a double-precision matrix multiplier targeted to and run in an Altera Stratix II FPGA , +- + R R As with the Stratix II FPGA, by using the 1:1 ratio of adds and multiplies and the , performance from a real Stratix II EP2S180 EP2S180 implementation of the AB matrix multiplication with data from a , peak FP analysis is repeated for the Stratix III EP3SE260 EP3SE260 FPGA. Table 3 shows the resources for the ... | Original |
6 pages, |
EP2S180 clock select adder with sharing EP2S180 abstract |
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| Abstract: leading-edge Altera® Stratix® II FPGA into a dual Opteron-based system. The FPGA coprocessor module can be , The Altera Stratix II EP2S180 EP2S180 FPGA used as the FPGA coprocessor in this study has 14,3520s ALUTs in , Clock- d2 Clock- d3 When implemented in the Altera Stratix II FPGA, the design will require about 180 , Stratix II FPGA represents a significant improvement in its adaptive logic module (ALM) design [1]. While , of magnitude. References 1. Altera Corporation, Stratix II Device Handbook, 2006 ... | Original |
18 pages, |
WP-01035-1 EP2S180 AMD64 XD1000 introduction to vlsi CS9222 Transistor Substitution Data Book 1993 384-PE 384-PE abstract |
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| Abstract: research, read Altera's Stratix II FPGA Architecture (the foundation of Stratix IV architecture) white , that enable Stratix IV FPGAs to lower power consumption, see Altera's 40-nm FPGA Power Management and , available, refer to Altera's Stratix IV FPGA Handbook. Conclusion Migrating to smaller geometries , Programmable Power Technology, Altera's 40-nm Stratix® IV FPGAs not only provide increased functionality and , data showing Altera® Stratix IV FPGAs are 35 percent faster than Virtex-5 FPGAs, and detailed ... | Original |
16 pages, |
XC5VLX330 VIRTEX-5 DDR2 virtex 5 fpga based image processing datasheet abstract |
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| Abstract: performance FPGAs such as Altera's Stratix II FPGA, are usually used at the heart of high-bandwidth systems , architectural layout of the industry leading Stratix II FPGA [5]. Figure 4: Stratix II Device Floorplan , , can be effectively addressed with FPGAs. Altera's Stratix II and Cyclone II FPGAs are considered as a , Altera's Stratix II platform [5], contain embedded DSP blocks, TriMatrixTM memory architecture, innovative , evolving standards. Altera's Stratix II FPGAs provide the ability to easily evolve WiMAX systems in ... | Original |
15 pages, |
NLMS Algorithm using matlab soft 16 QAM modulation matlab code simulink mimo LMS matlab code for mimo ofdm stc baseband processor simulink LMS adaptive filter model for FPGA vhdl code for ofdm transmitter simulink model adaptive beamforming vhdl code for ARQ vhdl code for ldpc lms algorithm using vhdl code datasheet abstract |
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| Abstract: , and memory. Table 1 shows the features of Altera's Stratix II FPGA family [2] as an example of the rich feature set that can be found in today's advanced FPGAs. Table 1: Altera's Stratix II Family , Corporation, Stratix II Data Sheet, www.altera.com [3] The Mathworks, Simulink Data Sheet , IMPLEMENTING A FPGA-BASED BROADBAND MODEM USING MODEL-BASED DESIGN Rob Pelt Altera Corporation , polyphase modem using current FPGA technology. 3. FPGA OVERVIEW Before describing the implementation of ... | Original |
7 pages, |
FIR filter matlaB simulink design EP2S90 EP2S60 EP2S30 EP2S180 EP2S15 DAC 5754 FPGA FAMILY baseband processor simulink CP-BRDBND05-1 CP-BRDBND05-1 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| following FPGAs: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II Stratix III, Stratix IV, Stratix GX, Stratix II GX, Arria GX. The EtherCAT Xilinx IP core can be used with the following FPGAs: Spartan-3 ) ET1812 ET1812 ET1812 ET1812 EtherCAT IP core licence for Altera FPGA "Floating Licence" ET  Beckhoff EtherCAT IP core for Altera and Xilinx FPGAs ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 | EtherCAT IP core for Altera and Xilinx FPGAs ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 www.datasheetarchive.com/files/beckhoff/catalog/english/ethercat/et1810_et1815.htm |
Beckhoff | 10/11/2009 | 7.56 Kb | HTM | et1810_et1815.htm |
| folgenden FPGAs verwendet werden: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix IV, Stratix GX, Stratix II GX, Arria GX. Der EtherCAT-Xilinx-IP-Core kann mit folgenden FPGAs ET1812 ET1812 ET1812 ET1812 EtherCAT-IP-Core-Lizenz für Altera-FPGA "Floating Licence" ET  Beckhoff EtherCAT-IP-Core für Altera- und Xilinx-FPGAs ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 | EtherCAT-IP-Core für Altera- und Xilinx-FPGAs ET1810 ET1810 ET1810 ET1810, ET1815 ET1815 ET1815 ET1815 www.datasheetarchive.com/files/beckhoff/catalog/german/ethercat/et1810_et1815.htm |
Beckhoff | 10/11/2009 | 7.8 Kb | HTM | et1810_et1815.htm |
| 40% performance advantage over their nearest competitor, Altera™ Stratix™ FPGAs, to further realize expander for the Virtex-II Pro architecture). The same function requires three LUTs for the Stratix /write performance of Virtex-II Pro block RAM configured to the same width and depths as the Stratix Mega % faster than Stratix FPGAs, respectively. Table 1 Â- Virtex-II Pro(-7) and Stratix(-5) block RAM ] Stratix [MHz] Virtex-II Pro [MHz] Deep Single-Port Memory 64k x 8 1 287 282 199 282 2 287 www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_49/xc_38percent49.htm |
Xilinx | 26/04/2004 | 21.14 Kb | HTM | xc_38percent49.htm |
| Area 130nm 90nm 65nm 90nm 65nm FPGA type 2900100 MHzAltera Cyclone III 4300 tiles70 MHzActel ProASIC3 Actel Fusion 260080 MHzAltera Cyclone II Xilinx Spartan-3 2300150 MHzAltera Stratix II Xilinx Virtex-4 1900200 MHzAltera Stratix III Xilinx Virtex-5 Area (LUTS)SpeedExample  Results below are Igloo and Actel Fusion  Altera Cyclone-III, Altera Stratix-III  Xilinx Spartan-3, Xilinx Virtex-5. 12 -M1 Introduction to the ARM® Cortex™-M Architecture 11 ARM Cortex-M1  Soft processor for FPGA www.datasheetarchive.com/download/66603255-30108ZC/cortex-m_workshop_tour.zip (Cortex M Architecture.pdf) |
ARM | 29/06/2009 | 11820.25 Kb | ZIP | cortex-m_workshop_tour.zip |
| : FPGA device configuration driver N: Gary Jennejohn E: garyj@jennejohn.org, gj@denx.de D: Support for Krishnaprasad E: Raghu.Krishnaprasad@fci.com D: Support for Adder-II MPC852T MPC852T MPC852T MPC852T evaluation board W: http ://www.leox.org N: Stephan Linz E: linz@li-pro.net D: Support for Nios Stratix Development Kit (DK-1S10 DK-1S10 DK-1S10 DK-1S10) D: Support eval board N: Scott McNutt E: smcnutt@psyent.com D: Support for Altera Nios-32 CPU, for Nios Cyclone www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (CREDITS) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| .c consistent with uses elsewhere in the source. * Patch by Steven Scholz, 25 Feb 2004: - Timeouts in FPGA code should be based on CFG_HZ - Minor cleanup in code for Altera FPGA ACEX1K * Patch by Steven Development Kit NIOS CPU configuration at the Altera Nios Development Kit, Stratix Edition (DK-1S10 DK-1S10 DK-1S10 DK-1S10) 5: - Add documentation for the Altera Nios Development Kit, Stratix Edition (DK-1S10 DK-1S10 DK-1S10 DK-1S10 Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003 www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (CHANGELOG) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |