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PMP2543 Texas Instruments Altera Cyclone III visit Texas Instruments
PMP8571 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC visit Texas Instruments
BEMICRONIO-2-PROCSDK-REF Texas Instruments Altera/Arrow BeMicro Nios II Processor SDK with DP83848 in USB Stick Format visit Texas Instruments
PMP8571.3 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC (1.5V@3A) visit Texas Instruments
PMP8571.1 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC (2.5V@3.5A) visit Texas Instruments
PMP8571.4 Texas Instruments Power for Altera Cyclone V (Cyclone 5) SOC (1.1V@6A) visit Texas Instruments

altera flex10k

Catalog Datasheet MFG & Type PDF Document Tags

altera flex10k

Abstract: Intel MCS-86 FLEX10K series of FPGAs. Table 3. Altera FLEX10K to Atmel Device Cross Reference FLEX10K Part Number , the EPC1441/EPC1/EPC2 in an Altera FLEX10K/6K Application VCC VCC VCC AT17C512A/010A/020A , .) Figure 5. Drop-in Replacement of Cascaded EPC1441/EPC1/EPC2 OTPs in an Altera FLEX10K Application VCC , system reset signal for Altera FLEX10K/6K applications. This ensures that the VCC has entered into the , 10. ISP of the AT17C512A/010A/020A in an Altera FLEX10K/6K Application VCC VCC DATA 1 DCLK 3 5
Atmel
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EPC1064 EPC1441 FLEX8000 altera flex10k Intel MCS-86 epf10k plcc 20pin socket EPF6024 10 k resistors AT17A EPC1213 0910B

FT245BM Bit-Bang Mode

Abstract: AN232BM-01 Note AN232BM-01 Example : Programing an Altera FLEX10K FPGA This example interfaces to an Altera FLEX10K FPGA. A cable was made up in the following manner : Bit Bang bit 0 1 2 3 4 5 6 7 Mode ALTERA Pin OUT OUT OUT IN IN IN IN IN CLK nCONFIG DATA0 nSTATUS CONF_DONE not used not
FTDI
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FT232BM FT245BM FT8U232 245BM FT245BM Bit-Bang Mode fpga altera cable DELPHI Set_USB_Device_BitMode RS232

altera 10 k series cpld

Abstract: MACH3 cpld process obsolescence with their current ASIC vendor. FPGA/CPLD FPGA Altera FLEX10K STRATIX , Supported All Altera® and Xilinx® DPRAM blocks CMOS, TTL, LVCMOS, LVTTL, PECL, and others (Actel , : Reed-Solomon® decoder, PLL/DLL Viterbi® decoder, HDLC, APCM. 100% compatible with Altera and Xilinx , Altera. Core (MHz) Periphery (MHz) 150 250 < 200 312 Pin Count: from 100 up to 1156. Body , programmable logic vendors. Others 3% If the device or version of the device you are inter- Altera 40
Atmel
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altera 10 k series cpld MACH3 cpld ulc 2003 MACH1 schlumberger ispLSI3000 4011B-ULC-11/03/15M

Atmel eeprom Cross Reference

Abstract: altera flex10k memory requirements to program the Altera Flex10K series of FPGAs. The Atmel AT17CXXX Configurators , memory can be used in several cases. Table 3. Altera to Atmel Device Cross Reference Flex10K Part , possible to use Atmel Configurators to replace the EPC1 that Altera recommends for use with the Flex10K , AT17CXXX Conversions from Altera FPGA Serial Configuration Memories Introduction The Atmel , place of the EPC1064, EPC1213, EPC1441 and EPC1 devices when used with Altera FPGAs. There are
Atmel
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Atmel eeprom Cross Reference 74hct157 socket plcc-2 ALTERA 0910A ATMEL Cross Reference AT17C256A AT17C65/128/256/512/010A-10JC 05/98/15M

FLEX10K100

Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 that the XC4000XL-09 FPGA family significantly outperforms the Altera FLEX10K-2 FPGA family , . Performance data also is provided for equivalent implementations in the Altera FLEX 10K-2 family devices , , and the Altera EPF10K130V device contains 6,656 1 Speed Metrics For High-Performance FPGAs , implemented in both Xilinx XC4000XL-09 and Altera FLEX 10K-2 devices, representing the fastest FPGA devices , hardware description language, developed by Altera. The FLEX designs were synthesized and implemented
Xilinx
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XC4000XL FLEX10K100 vhdl code for multiplexer 64 to 1 using 8 to 1 x7160 32 bit ripple carry adder vhdl code vhdl code for 4 bit ripple carry adder Floorplanner XBRF015 FLEX10K-2

EPM7128Q

Abstract: VMIC reflective The FLEX 10KA family will extend the Altera FLEX10K architecture to a projected 250,000 gates. As , reduced prices for the FLEX10K family up to 50%. The price reductions are a result of Altera , high-density, high-performance devices. Therefore, Altera has teamed with Amkor/Anam to offer FLEX10K devices , FLEX 10K Price Reductions See page 4 Newsletter for Altera Customers x Fourth Quarter x November 1996 Altera Announces the 3.3-V FLEX 10KA Family Altera® announces the FLEX®10KA family of
Altera
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EPM7128Q VMIC reflective EPM7160 Transition amd 9513 xilinx FPGA IIR Filter EPF10K20A 104MH FLEX10KA EPF10K50A

LATTICE plsi 3000 SERIES cpld

Abstract: TEMIC PLD Device Specific RAM ULCs do support ALTERA FLEX10K RAM blocks. As large blocks of RAM can significantly , , FLEX6000 and FLEX10K series, Altera claims that the timing characteristics offer greater predictability , preferred format. Please refer to Test Vectors chapter in this data book. Altera EPLD Conversion Altera , conversions are supported. Altera refers to the CPLDs and EPLDs (Erasable PLD). Dedicated Pins There are , registers, flip­flops and latches. An Altera design which does not meet this requirement cannot be converted
Temic Semiconductors
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A1415-A14100 LATTICE plsi 3000 SERIES cpld TEMIC PLD EPM9000 temic ulc products EPM5000 actel act1 family A1010 A1020 A1225 A1240 A1280

Date Code Formats Altera EPF10K

Abstract: altera flex10k Cascaded AT17C/LV512A/010A/002As in an Altera FLEX10K Application VCC VCC DATA 1 DCLK 3 5 EPF10K , Altera pinout variants except where stated.) 8 Note: The Manufacturer's Code and Device Code , AT40K 2. Xilinx XC4000 3. Altera EPF6K, EPF8K, and EPF10K · Pinout compatibility and package , Altera Applications Altera FLEX® devices (e.g., EPF10K, EPF6K, EPF8K) can be configured with AT17A , system reset signal for Altera EPF10K/6K applications to ensure that the VCC has entered into normal
Atmel
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Date Code Formats Altera EPF10K AT17C65 0437H-03 AT17/AT17A AT17 0437H

FPGA Virtex 6 pin configuration

Abstract: spartan 3a . Figure 13. ISP of 2 Cascaded AT17C512A/010As in an Altera FLEX10K Application VCC VCC DATA 1 DCLK 3 , protocol and operations are used for both 5V and 3.3V devices, as well as for the Altera pinout variants , contention on the clock line during ISP 3. Altera EPF6K, EPF8K, and EPF10K · Avoiding contention on the , Configurator Programming Altera Applications Altera FLEX devices (e.g. EPF10K, EPF6K, EPF8K) can be , signal for Altera EPF10K/6K applications; to ensure that the VCC has entered into normal operating
Atmel
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FPGA Virtex 6 pin configuration spartan 3a eeprom programmer schematic spartan 2 spartan application note eeprom programmer schematic diagram 0437G

full adder 7483

Abstract: 8count macrofunction Table 3. FLEX 8000 & FLEX10K Technology & Synthetic Libraries Altera Device Family FLEX 8000 Synthetic , Synopsys version 3.4 design tools and the Altera MAX+PLUS II development software together provide a , both the IEEE 1076-1987 and 1076-1993 standards), Verilog HDL, and the Altera Hardware Description , , fitting, and multi-device partitioning Device programming with Altera or third-party programming hardware Design environment certified by Altera and Synopsys This software interface guide describes how to
Altera
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full adder 7483 8count macrofunction 81MUX DW03D Altera 8count vhdl code for 8-bit serial adder

DesignWare

Abstract: Synopsys Compiler FPGA Compiler MAX+PLUS II http://www.altera.com MAX+PLUS II Altera Technical Support AtlasSM Altera Commitment to Cooperative EnSM gineering Solutions ACCESS Key Guidelines AC CESS Key Guidelines MAX+PLUS II CD-ROM 8.2 \lit\html\maxkey HTML Altera Corporation M-TB-039-01/J TB 39 , search_path={./ synopsys/library/alt_syn/flex10k/lib} target_library = , /library/alt_syn/flex10k/lib /dw_flex10k_fpga edifout_netlist_only = "true"
Altera
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DesignWare Synopsys M-TB-039-01 FLEX10

smd transistor 43t

Abstract: altera flex10k settings for line control. The design can be fitted into an Altera Flex10K device and is compiled with , configuration via the dip switches. Both examples are implemented in an Altera CPLD (complex programmable logic , Texas Instruments. Altera is a trademark of Altera Corporation. iv Running Title-Attribute , (CPLD) Altera EPM7128 on the board. The CPLD is used to generate the sync/blanking control signals and , cable, such as the Altera Byteblaster or Bitblaster. Alternatively, the user can supply digital (video
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smd transistor 43t SMPTE274 EPM7128* kit EPM7128SLC84 CPLD THS8133B THS8134B THS8133B/34B SLVU020C

smd transistor 43t

Abstract: on line ups circuit schematic diagram settings for line control. The design can be fitted into an Altera Flex10K device and is compiled with , dip switches. Both examples are implemented in an Altera CPLD (complex programmable logic device). , Texas Instruments Incorporated. Altera is a trademark of Altera Corporation. iv Running , provides the clocking to the DAC and the complex programmable-logic device (CPLD) Altera EPM7128 on the , the part if he has access to third-party development tools1 and a download cable, such as the Altera
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on line ups circuit schematic diagram capacitor 103 .01uf 1080i field pattern black capacitor X7R-805 2d2 smd transistor AMP 103309-1 THS8133/34 SLVU020A

format .acf

Abstract: MAX PLUS II free , CA 94043 (650) 962-5000 http://www.synopsys.com The Altera¨ MAX+PLUS¨ II software easily , target Altera programmable logic devices (PLDs). The Altera/Synopsys interface is available , provides all the necessary files and libraries needed to support the Altera/Synopsys interface. The Altera/Synopsys tools let you quickly synthesize and implement designs for Altera devices, and even , Set up the Synopsys design environment Generate an EDIF netlist file for Altera devices Pass timing
Altera
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format .acf MAX PLUS II free TB-39 50 format .acf to format .pof 800-EPLD

DW03D

Abstract: full adder 7483 Synopsys version 3.4 design tools and the Altera MAX+PLUS II development software together provide a , behavioral design entry with VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL) Full , , fitting, and multi-device partitioning Device programming with Altera or third-party programming hardware Design environment certified by Altera and Synopsys This software interface guide describes , Contacting Altera .71
Altera
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8count VHDL program 4-bit adder vhdl code for carry select adder 8fadd a_8fadd FLEX10K equivalent

format .acf to format .pof

Abstract: MAX PLUS II free , CA 94043 (650) 962-5000 http://www.synopsys.com The Altera® MAX+PLUS® II software interacts , target Altera programmable logic devices (PLDs). The Altera/Synopsys interface is included with the , libraries needed to support the Altera/Synopsys interface. The Altera/Synopsys tools let you quickly synthesize and implement designs for Altera devices, and perform multiple design iterations in a single day , EDIF netlist file for Altera devices Pass timing constraints from the Synopsys design environment to
Altera
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synopsys memory

EPM7160 Transition

Abstract: 6402 uart for FLEX10K devices in the -3 speed grade. Altera used the following methodology to demonstrate , Newsletter for Altera Customers x Third Quarter x August 1996 ClockLock & ClockBoost Circuitry for High-Density PLDs Altera is introducing two new options for high-density programmable logic , enables clock multiplication in Altera devices. Popularly used in microprocessors, clock multiplier , and quadrupled in some Altera devices. See Figure 3 on page 3. ClockBoost allows designers to run
Altera
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6402 uart 4 bit updown counter vhdl code EPM7064L-84 EPM7160L-84 ep330 EPM7192 Date Code Formats

8251 uart in vhdl code

Abstract: verilog code for parallel fir filter approach. Altera addresses this design need w ith Altera-created megafunctions, called MegaCoreTM functions, and megafunctions developed through the Altera Megafunction Partners Program (AMPPTM). Megafunctions , , pre-tested, documented, and licensed by Altera as MAX+PLUS® II add-on migration products. These functions are optim ized for target Altera device architectures, including FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000 , function's optimization is preserved. Altera provides all files necessary to design with MegaCore functions
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OCR Scan
8251 uart in vhdl code verilog code for parallel fir filter VHDL CODE FOR 8255 PLSM-8251 microprocessors architecture of 8251

MACH3 cpld

Abstract: APEX20K 2002 Memory Blocks Supported Special IO's Supported All Altera® and Xilinx® DPRAM blocks , , HDLC, APCM. PLL/DLL Others: 8051, FFT, PWM, etc. 100% compatible with Altera and Xilinx , 0.35 µm 0.25 µm 0.18 µm Xilinx and Altera. Core (MHz) Periphery (MHz) 150 200 250 , . FPGA/CPLD FPGA Altera WWW.ATMEL.COM FLEX8000 MAX7000/A/B/S MAX5000 FLEX6000 , programmable logic vendors. Others 1% If the device or version of the device you are inter- Altera 30
Atmel
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APEX20K DPRAM verilog code for DFT MAX9000 XC3000 XC5200

MACH3 cpld

Abstract: actel core 8051 S U P P O R T E D V I S I T U S AT www.atmel-wm.com FPGA Altera CPLD FLEX10K , Memory blocks supported IPs All Altera and Xilinx DPRAM blocks Telecommunication: PCI core, PCI , . Extensive packaging capabilities Latest fine pitch BGA compatible with Xilinx and Altera. Special IO , the device or version of the Cypress 1% Philips 1% Altera 30% Actel 12% device you are
Atmel
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actel core 8051 MAX7000 circuit diagram of sound wireless XC4000E CCT 8051 cypress FLASH370 D-74025
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