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OPA2314ASDRBTEP Texas Instruments Enhanced Product Low-Power Low-Noise RRIO 1.8V CMOS Op Amp 8-SON -40 to 150 visit Texas Instruments Buy
OPA2314AIDGKT Texas Instruments DUAL OP-AMP, 2500uV OFFSET-MAX, 3MHz BAND WIDTH, PDSO8, PLASTIC, MSOP-8 visit Texas Instruments
PGA2311PA Texas Instruments +/-5V Stereo Audio Volume Control 16-PDIP visit Texas Instruments Buy
PGA2311UG4 Texas Instruments +/-5V Stereo Audio Volume Control 16-SOIC -40 to 85 visit Texas Instruments
TS5A23157DGSRE4 Texas Instruments Dual 10-Ohm SPDT Analog Switch 10-VSSOP -40 to 85 visit Texas Instruments
TS5A23159DGST Texas Instruments 1-Ohm 5-V/3.3-V 2-Channel SPDT Switch 10-VSSOP -40 to 85 visit Texas Instruments Buy

a231 ax hen no

Catalog Datasheet MFG & Type PDF Document Tags

a231 ax hen no

Abstract: A225 O I/03 O Vcc I f * D- I/04 O î WRITE O- Î £ » NO.2 CLOCK GENERATOR DATA , m e NO. I CLOCK GENERATOR SUBSTRATE BIAS GENERATOR ABSOLUTE M A X IM U M RATINGS ITEM In p , p u t Low V o ltage M IN. 4.5 2.4 - 1.0 TY P. 5.0 M AX. 5.5 6.5 0.8 UNIT V V V NOTES 2 2 2 A , MODE CURRENT kC 4 SYMBOL M IN. M AX. UNITS NOTES 3. 4 TC514258BP/BJ/ 0Z/BFT-6O 90 mA , ÎRCD *RAD *CRP *C P - UNIT M AX. 60 20 30 55 0 0 5 3 40 60 60 20 60 20 20 20 15 5 10 0 10 0 15
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a231 ax hen no A225 BFT te 04 TC514258BP/BJ/BZ/BFT-60 TC514258BP/BJ/BZ/BFT TC514258BP/ 2G/20 TC514258BP/BJ
Abstract: in V SS G ro u n d D a ta O u t N .C. BLO C K D I A G R A M P o w e r { + 5V) No , V cc Low P o w e r 6 6 0 m W M AX . O p e r a t i n g (T C 5 1 4 1 0 2 A P /A J /A S J /A Z â , c. A! 3A 4 A3 A-231 TC514102AP/AJ/ASJ/AZ-60 ABSOLUTE M A X IM U M RATINGS ITEM , SYMBOL M AX. UNITS - 120 mA OPERATING CURRENT â cci NOTES 3 ,4 TC514102AP/AJ , PARAMETER UNIT MIN. NOTES M AX. tRC Random Read o r W rite Cycle Time 110 - ns -
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TC514102 TC514102AP/AJ/ASJ/AZ 512KDRAM AP/AJ/ASJ/AZ-60
Abstract: N D p in s and de co u p lin g c a p a c ito rs fo r m a xi m um no ise im m u nity · Inp uts/o utpu , noise. FUNCTIONAL BLOCK DIAGRAM*1 » ADDRESS BUS A2-31 CONTROL BUS C ontrol CLK DATA BUS , '01993 Integrated Device T ech no log y, Inc AUGUST 1993 D SC-7109/1 IDT7MP6118/19 128KB/256KB , and da ta buses. W hen S B O F F # is asse rted , th e cach e w ill on ly re cognize in va lid a tion , evicte d from the cache. If S B O F F # is asse rted the cach e w ill no t a sse rt C B O F F #, exce p t -
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486TM IDT7MP6118 IDT7MP6119 7MP6118 7MP6119 128KB
Abstract: Interface. A2-31 Address Bus (Input) TINT Timer Interrupt (Output) (Output; 12mA; Active Low , ) These signals are the write strobes for the DR AM W hen enabled, a Bus Error is generated if D E N is , CA bus specification and requires no external bus interface logic. Thus, it avoids the propagation , for the next datum of the burst. This feature is provided so that systems employing no latching , 0 1 0 1 2 0 0 0 1 1 0 0 0 0 Operation No Operation (Access other Configuration -
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V96BMC
Abstract: -bit peripheral devices control signals E, VPA and VMA are no t used. Those already fam iliar w ith the , NEG NOP NOT Negate Decimal with Extend Negate No Operation One's Complement OR Logical , support the sized operands. Therefore, w hen an address register is used as a source operand, either the low order word or the entire long word operand is used depending upon the operation size. W hen an , '" »An 8,16,32 ADD 16,32 ADDX 8,16,32 16,32 Dx + Dy + X ~*Dx - (Ax) + - (Ay) + X -»(Ax -
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TMP68303 68HC000 TMP68HC000 MPU-198 MPU-199 MPU-200

M80286

Abstract: D8086 and O utput signal - No electrical connection Sym bol CLK2 RESET Type I I Nam e and Function CLK2 , processor Interface Signals fo r additional information. No Connects should always be left unconnected , Vss B11 C2 D1 M1 N4 N9 N11 A2 A12 B1 B13 M13 N2 N6 N12 N /C L1 NOTE: N /C (No Connect) pins , /C (No Connect) pins must not be connected. 6 0MF©[^[MATD®[K] MILITARY ¡386TM SX , hen set, m askable interrupts will cause the CPU to transfer control to an interrupt vector specified
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M80286 D8086 271110 M8086 M80186 387TM

Lmb204

Abstract: 441L204 HITACHI 4 4TbE04 0 0 4 4 7 ^ 3 TEÃ" ADE-602-074 fl Notice W hen using this document, keep , . 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole , . Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by , 00447T4 Tb4 â  Q, W hen using this document, keep the following in mind: 1. This document
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Lmb204 441L204 SH7020 SH7021 HD6437020 HD6437021 TFP-100B

TLCS-68000

Abstract: TMP68303F-16 when no vector num ber is autom atically generated in an external in te rru p t. W hen a vector num , , H : High Y : Yes In/out: Input/output L : Low N : No 303-8 TOSHIBA 2.4 TMP68303 , core processor starts loading the vector number. At this time, no area selection signal is generated, even when the address generated attem pts to access an area. (No register area access signal or CSn , DRAM controller * inserted: 5 CS1 pin No memory space specified vZv//. Parallel/SMC CS1
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TMP68303F-16 TLCS-68000 tmp-68303f-16 TMP68301 TMP68303F A12-23 TC74ATC541F A1-11

CR05A

Abstract: uPD70423 prior to its production. The m ark Document No. (O.D.No. ID-S206A) Date Published M arch 1993 P Pnnted , IM E C ¿¿PD70423 No. FI F2 F3 F12 F13 F14 G1 G2 G3 G12 G13 G14 H1 H2 H3 H12 H13 H14 J1 J2 J3 , POO - - - - - - - - - No. K3 K12 K13 K14 L1 L2 L3 LI 2 L13 L14 Ml M2 M3 M4 M5 M6 M7 M8 M9 , - - - No. N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 , //PD70423 Remarks The locator pin is not included in the pin numbers. No. Ai A2 A3 A4 A5 A6 A7 A8
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V55SC CR05A uPD70423 CR04A CR08B TCS4H ND3N V55SCTM 16-BIT PD70322 V25TM V35TM

MICROPROCESSOR 68000

Abstract: signetics 68000 extend NEG Negate NOP No operation NOT One's complement OR Logical OR PEA Push effective address , Dy + X -> Dx -(Ax) + -(Ay) + X â'"» (Ax) CLR 8,16, 32 0-> EA 8,16,32 Dn-(EA) CMP (EA) - #xxx (Ax) + -(Ay)- 16,32 An - (EA) DIVS 32+ 16 Dn + (EA) â'"» Dn DIVU 32+ 16 Dn + (EA) â'"» Dn EXT 8 , » Dx - (Ax) - (Ay) - X â'"» (Ax) TAS 8 (EA) - 0,1 EA[7] TST 8, 16, 32 (EA) - 0 Integer Arithmetic , INSTRUCTION OPERAND SIZE OPERATION ABCD 8 Dx10+ Dy,o + X -> Dx - (Ax)10 + - (Ay),0 + X (Ax) SBCD 8 Dx,o-Dy
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MICROPROCESSOR 68000 signetics 68000 SF4 357 scn68000 32bu 48DIP 16-/32-B 0D01114 B00000
Abstract: Port PO0-P O 7 pull-down bit 1 Port P1o-P1 7 pull-down bit 0 : No pull-down 1 : Pull-down 1 O 0 2 Port P2o-P27 pull-up bit 0 : No pull-up 1 : Pull-up 0 O 0 3 Port P3o-P37 pull-down bit 0 : No pull-down 1 : Pull-down 1 O 0 4 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 : No pull-down 1 : Pull-down Port P7o, P7i pull-up bit 0 : No pull-up 1 , 0 : No pull-up 1 : Pull-up 0 0 1 Port P44-P47 pull-up bit 0 : No pull-up 1 -
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led 7 segment LDS 5161 AK

Abstract: 7-segment 4 digit LFD 5522 Y :. P H O N E N O .; ( . .I â'" ;.-,. ' -V - ORDER NO. QTY , weeks for delivery. . , â¡ VISA â¡M asterC ard Q American Express Expiration Date Account No , ITY: STA TE: ZIP : CO U NTRY: P H O N E N O .: ORDER NO. ( ) TITLE QTY , created b y In te l customers. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it m ake a commitment
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led 7 segment LDS 5161 AK 7-segment 4 digit LFD 5522 AKO 701 434 82360SL MIP 411 diagrama ako 451 692 K27970 X287751 02780-M X1773790D X52-5-561-1279 X52-73-17-5333

ia181

Abstract: TMP68204 on't care High Y : Yes Low N : No 204-9 TOSHIBA 2.4 I/O Circuits of Pins TMP68204 Pin , that time accesses any of the four areas, no signals are generated for selecting the respective areas , being inadvertently accessed during the IACK cycle. When a vector No. is externally input, the address , CS1toCS3pins No memory space specified CS1 to CS3 output disabled Internal/external DTACKcan be used 0 wait , automatically generated so that internal circuit registers can be accessed with no waits. In DMA single-address
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ia181 diack ST 083 TMP68204F-16
Abstract: where no microcontroller use has been considered before (e.g. timer functions, serial communication -
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PIC16C7X PIC16C72 PIC16C74A PIC16C73 PIC16C76 PIC16C73A

THERMISTORS nsp 037

Abstract: Thyristor TAG 9118 INDEX OF COMPONENTS A Section/Page No. A.C. Adaptor , ' . Sectibn/Page No. .14,157â'" 169,162 _ P18â'"P24 .L14 , Bolts . â' N u tse rts". t Section/Page No. O Octal Plugs , ' . Q â' Q-Maxâ' Cutter; Section/Page No. S - conlinued Seven Segment Indicators Sheet , . COMPONENTS - SILICONIX MULLARD N = NSC S = SIGNETICS i TYPE NO. CODE PRICE
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THERMISTORS nsp 037 Thyristor TAG 9118 a1273 y k transistor ICA 0726 0148 Transformer AM97C11CN transistor SK A1104 200X300X360