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Part : ZL50073GAG2 Supplier : Zarlink Semiconductor Manufacturer : Chip One Exchange Stock : 74 Best Price : - Price Each : -
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ZL50073 Datasheet

Part Manufacturer Description PDF Type
ZL50073 Zarlink Semiconductor 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Input ... Original
ZL50073 Zarlink Semiconductor 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs Original
ZL50073GAC Zarlink Semiconductor 32K-channel digital switch with high jitter tolerance, rate conversion per group of 4 streams (8, 16, 32 or 64 Mbps), and 128 inputs and 128 outputs. Original
ZL50073GAC Zarlink Semiconductor Interface - Telecom, Integrated Circuits (ICs), IC DIGITAL SWITCH 32K CH 484PBGA Original
ZL50073GAG2 Zarlink Semiconductor 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs Original
ZL50073GAG2 Zarlink Semiconductor Interface - Telecom, Integrated Circuits (ICs), IC DIGITAL SWITCH 32K CH 484PBGA Original

ZL50073

Catalog Datasheet MFG & Type PDF Document Tags

ZL50073

Abstract: MHz or 65.536 MHz clock. This clock must be provided for correct operation of the ZL50073. The , automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing options. The active clock edge may , write access to the ZL50073. D14 DS Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. C15 R/W Read/Write Input (5 V , Input) Asynchronous reset input used to initialize the ZL50073. 0 = Reset 1 = Normal See Section
Zarlink Semiconductor
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ZL50073GA

ZL50073

Abstract: ZL50073GAC operation of the ZL50073. The frequency of the CKi0 input is selected by the CK_SEL1-0 inputs. The active , of each clock input is automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing , input used with DS to enable read and write access to the ZL50073. D14 DS Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. , Input) Asynchronous reset input used to initialize the ZL50073. 0 = Reset 1 = Normal See Section
Zarlink Semiconductor
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8095

Abstract: STi256 for the ZL50073. Figure 2 illustrates the construction of a 64 K x 64 K channel switch by putting , switch. Figure 5 shows the implementation of a 256 K x 256 K three-stage matrix using the ZL50073s. The , ZLAN-111 Applications of the ZL50073 Designing Large Switching Matrices Application Note , feature-rich device, ZL50073, will be used as an example. The other 32 K switches can be used similarly. Two , used more often. 2.0 The ZL50073 is a non-blocking large TDM digital switch with 32,768 x 32,768
Zarlink Semiconductor
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8095 STi256 4863

SToD15

Abstract: for correct operation of the ZL50073. The frequency of the CKi0 input is selected by the CK_SEL1 , automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing options. The active clock edge may be , input used with DS to enable read and write access to the ZL50073. Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. Read/Write Input (5 V , Schmitt-Triggered Input) Asynchronous reset input used to initialize the ZL50073. 0 = Reset 1 = Normal See Section
Zarlink Semiconductor
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SToD15
Abstract: for correct operation of the ZL50073. The frequency of the CKi0 input is selected by the CK_SEL1 , automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing options. The active clock edge may be , Tolerant Input) Active low input used with DS to enable read and write access to the ZL50073. Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. , (5 V Tolerant Schmitt-Triggered Input) Asynchronous reset input used to initialize the ZL50073. 0 = Zarlink Semiconductor
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SToD15

Abstract: 4-bit bidirectional shift register for correct operation of the ZL50073. The frequency of the CKi0 input is selected by the CK_SEL1 , automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing options. The active clock edge may be , Tolerant Input) Active low input used with DS to enable read and write access to the ZL50073. Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. , (5 V Tolerant Schmitt-Triggered Input) Asynchronous reset input used to initialize the ZL50073. 0 =
Zarlink Semiconductor
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4-bit bidirectional shift register

STiD12

Abstract: 65.536 MHz clock. This clock must be provided for correct operation of the ZL50073. The frequency of the , each clock input is automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing options , Input) Active low input used with DS to enable read and write access to the ZL50073. Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. , ZL50073. 0 = Reset 1 = Normal See Section 11.0, Power-up and Initialization of the ZL50073 for detailed
Zarlink Semiconductor
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STiD12

STiD12

Abstract: SToD15 operation of the ZL50073. The frequency of the CKi0 input is selected by the CK_SEL1-0 inputs. The active , of each clock input is automatically detected by the ZL50073. Refer to Section 2.0 for TDM timing , used with DS to enable read and write access to the ZL50073. D14 DS Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50073. C15 R , ) Asynchronous reset input used to initialize the ZL50073. 0 = Reset 1 = Normal See Section 11.0, Power-up and
Zarlink Semiconductor
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cd 40188 SToD31 FPI02 40280 40107 40107 Equivalent

ZL30402

Abstract: ZL50010 ZL50070/3/4/5 TDM / TSI SWITCHES VOICE / DATA ZL50073 Simplified Block Diagram , ) rate selection & conversion 484-ball PBGA, 23 x 23 mm ZL50073 32 K x 32 K 128 In/128 Out , VOICE / DATA Applications The ZL50073 TDM switch delivers the density and flexibility required by , cost-effective timing architecture for their application. The diagram below illustrates how Zarlink's ZL50073 , different data rates. The ZL50073 is the industry's first high-density device with integrated G.711 per
Zarlink Semiconductor
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ZL50409 ZL30402 ZL50010 ZL50050 ZL50070 ZL50074 ZLTM50070 MT92210 ZL50110 ZL50058 MT9072
Abstract: Media Gateways, Wireless Base Stations and Class 5 Switches. What do they have in common? 32K TDM/TSI Switches from Zarlink ZL50073-32K Channel TDM/TSI Switch VOICE / DATA WIRELESS , ) 4 Clock Outputs Introducing the ZL50073 family of 32K TDM/TSI Switches Offering two 24K devices and three 32K devices, the ZL50073 family simplifies the design of high-bandwidth voice and data , streams-largest number on a 32K TDM switch · ZL50073/4/5-32K x 32K switches with up to 128 I/O · ZL50070/1-24K Zarlink Semiconductor
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ZL50073--32K ZL50073/4/5--32K ZL50070/1--24K

Ch252

Abstract: CH254 streams and 128 receive streams in the ZL50073. Each transmit STo stream has an associated BER , Programming Sequence 7.0 BERT in the 32 K TDM Switches 7.1 The ZL50073 BERT Programming Sequence , including the ZL50070, ZL50073, ZL50074 and ZL50075. The BERT will be explained on the example of the ZL50073 device, the most feature rich device. A similar test can be easily applied to other 32 K devices , implemented in the ZL50073 TDM switch. Transmit stream 0(SToA0) Ch 0 Ch254 Ch255 Ch 2 Ch 3 Ch 1
Zarlink Semiconductor
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MT90826 MT90866 MT90869 ZL50021 Ch252 CH254 prbs generator 0x030000 bert ZL50031 ZLAN-166 ZL50030/31 MT90869/70/71 ZL50060/61

"digital switch"

Abstract: ZL50018 with High Jitter Tolerance (ZL50073) ZL50063 16 K Channel (32 input and 32 output streams) High , with Per-Group (4 Streams) Rate Conversion (8, 16, 32, 64 Mbps) ZL50073 32 K Channel (128 input
Zarlink Semiconductor
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ZL50018 ZL50019 MT90810 MT8986 MT89L86 MT90863 ZL50030 MT90812 MT9080B

MT89L86

Abstract: MT8986 , 32, 64 Mbps) ZL50073 32 K Channel (128 input and 128 output streams) High Jitter Tolerance , Tolerance (ZL50073) 128 Input Streams Input Group (4 streams) 8, 16, 32 or 64 Mbps Input Delay
Zarlink Semiconductor
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ZL50011 ZL50015 ZL50022 MT8920B MT90840 10ZL059

X32K

Abstract: ZL50060 ZL50061 ZL50062 ZL50063 ZL50064 ZL50070 ZL50073 ZL50074 ZL50075 16 K x 16 K 64 64 16 K x 16 K
Zarlink Semiconductor
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X32K MT90871 ZL50051 ZL50052 ZL50053 MT90870 ZL50057
Abstract: common 32K switches. The 32K switch model was taken from Zarlink Semiconductor's ZL50073 device. Both Zarlink Semiconductor
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ZL50074

Abstract: Motorola P13 - 02.08.00 , 32.768 MHz or 65.536 MHz and the rates are automatically detected by the ZL50073. These clocks must be
Zarlink Semiconductor
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Motorola P13 - 02.08.00 STOD03
Abstract: MHz, 32.768 MHz or 65.536 MHz and the rates are automatically detected by the ZL50073. These clocks Zarlink Semiconductor
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ZL50074GDC