NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: GND Y3 6 6 9 VCC GND 7 7 10 GND Y4 8 8 12 VCC A4 9 9 13 GND Y5 10 10 14 VCC 3.0 V A5 Y6 11 12 11 12 16 18 GND VCC A6 13 13 19 GND -o.ov Vcc 14 14 20 VCC â- VOH BURN-IN CONDITIONS: VCC , (g) MOTOROLA Hex 1-Input Inverter Gate ELECTRICALLY TESTED PER: MIL-M-38510/30004 MIL-M-38510/30004 LOGIC DIAGRAM Vcc A6 Y6 A5 Y5 A4 Y4 nil nil rrn nói r^j y y y p ft ft fr. Ill lil ill LsJ Lü ¿J LzJ A1 Y1 A2 , Subgroup 10 Subgroup 11 Min Max Min Max Min Max ... | OCR Scan |
2 pages, |
54LS05 38510/30004 Y6 11 JM38510/30004 MIL-M-38510/30004 MIL-M-38510/30004 abstract |
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| Abstract: cc z > 5 y^. Q Y8 ]5 Y8 Y7 Vcc Y7 ]» Y6 ]10 Y6 ]11 ìfi ö n |UJ O > O lo C3 , REVISED MARCH 1994 logic diagram clkin â- u 30 O O O H 3J m < m £ W ;3>l W 23 21 11 10 y1 yî 20 19 â„¢ y2 y2 18 17 16 14 y3 y3 y4 y4 13 12 y5 y5 y6 ys y7 y7 y8 y8 , J-Vcc -1-7 V _/ "D CLKIN 73 CLKIN -1-1- VCC-0.9 V -1-1- VCC-1.7 V O Y -UW-^y- VOH E y-ri-V°L O , Y6 Y6 Y7 Y7 Y8 Y8 -ti X tPLH1 X tPLH2 X »PLH3 X *PLH4 X »PLH5 X «PLH6 X tPLH7 X ... | OCR Scan |
5 pages, |
CDC112 SCAS322-DECEMBER 1993-REVISED CDC112 abstract |
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| Abstract: 13 A8 ECL/TTL 1 Y1 2 Y2 3 Y3 4 Y4 9 Y5 10 Y6 11 Y7 12 Y8 This symbol is in , 655303 · DALLAS, TEXAS 75265 9 10 Y5 Y6 11 Y7 12 Y8 SN100KT5541 SN100KT5541 OCTAL , Control Inputs Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 , 4 6.2 2.5 5.1 7.7 2.1 4.3 6.4 1.1 3.7 6.3 UNIT ns ns ns ns ... | Original |
7 pages, |
SN100KT5541 SDZS004A SN100KT5541 abstract |
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| Abstract: 13 A8 ECL/TTL 1 Y1 2 Y2 3 Y3 4 Y4 9 Y5 10 Y6 11 Y7 12 Y8 This symbol is in , 655303 · DALLAS, TEXAS 75265 9 10 Y5 Y6 11 Y7 12 Y8 SN100KT5541 SN100KT5541 OCTAL , Control Inputs Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 , 4 6.2 2.5 5.1 7.7 2.1 4.3 6.4 1.1 3.7 6.3 UNIT ns ns ns ns ... | Original |
7 pages, |
SN100KT5541 SDZS004A SN100KT5541 abstract |
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| Abstract: 13 A8 ECL/TTL 1 Y1 2 Y2 3 Y3 4 Y4 9 Y5 10 Y6 11 Y7 12 Y8 This symbol is in , 655303 · DALLAS, TEXAS 75265 9 10 Y5 Y6 11 Y7 12 Y8 SN100KT5541 SN100KT5541 OCTAL , Control Inputs Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 , 4 6.2 2.5 5.1 7.7 2.1 4.3 6.4 1.1 3.7 6.3 UNIT ns ns ns ns ... | Original |
8 pages, |
SN100KT5541NT SN100KT5541DW SN100KT5541 SDZS004A SN100KT5541 abstract |
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| Abstract: a6169 13 9 12 6 14 7 13 8 Y6 11 15 12 11 Y2 Y3 A3 Y5 A7 5 Y4 A6 16 9 A5 4 A2 Y7 Y4 A4 Y5 A5 GND 10 Y6 A6 A7 SA00202 SA00202 , , 4, 5, 6, 7, 8, 9 EN 19 A0 Â A7 Data inputs 18, 17, 16, 15, 14, 13, 12, 11 & 1 , 6 14 7 13 8 12 9 11 FUNCTION TABLE INPUTS OUTPUTS OE0 H L X Z , ns tPZH tPZL Output enable time to High and Low level 2 1.1 2.1 3.1 4.4 4.8 ... | Original |
6 pages, |
74ABT541PW 74ABT541 74ABT541 abstract |
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| Abstract: 12 Y6 11 Y7 GND 10 GND 10 Functional Diagram OEA OEB 540 D0 Y0 541 Y0 D1 Y1 Y1 D2 Y2 Y2 D3 Y3 Y3 D4 Y4 Y4 D5 Y5 Y5 D6 Y6 Y6 D7 Y7 , OE A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 CD54HC541 CD54HC541, CD54HCT541 CD54HCT541 (CERDIP) CD74HC541 CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 CD74HCT541 (PDIP, SOIC) TOP , 15pF CL = 15pF 5 5 tPHL, tPLH CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 10 9 11 14 24 28 35 12 10 ... | Original |
20 pages, |
CD54/74HC540 CD74HCT540 CD54/74HC541 CD54/74HCT541 SCHS189C CD54/74HC540 abstract |
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| Abstract: 12 Y6 11 Y7 GND 10 GND 10 Functional Diagram OEA OEB 540 D0 Y0 541 Y0 D1 Y1 Y1 D2 Y2 Y2 D3 Y3 Y3 D4 Y4 Y4 D5 Y5 Y5 D6 Y6 Y6 D7 Y7 , OE A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 CD54HC541 CD54HC541, CD54HCT541 CD54HCT541 (CERDIP) CD74HC541 CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 CD74HCT541 (PDIP, SOIC) TOP , 15pF CL = 15pF 5 5 tPHL, tPLH CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 10 9 11 14 24 28 35 12 10 ... | Original |
20 pages, |
CD54/74HC540 CD74HCT540 CD54/74HC541 CD54/74HCT541 SCHS189C CD54/74HC540 abstract |
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| Abstract: 12 Y6 11 Y7 GND 10 GND 10 Functional Diagram OEA OEB 540 D0 Y0 541 Y0 D1 Y1 Y1 D2 Y2 Y2 D3 Y3 Y3 D4 Y4 Y4 D5 Y5 Y5 D6 Y6 Y6 D7 Y7 , OE A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 CD54HC541 CD54HC541, CD54HCT541 CD54HCT541 (CERDIP) CD74HC541 CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 CD74HCT541 (PDIP, SOIC) TOP , 15pF CL = 15pF 5 5 tPHL, tPLH CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 10 9 11 14 24 28 35 12 10 ... | Original |
19 pages, |
CD54/74HC540 CD74HCT540 CD54/74HC541 CD54/74HCT541 SCHS189C CD54/74HC540 abstract |
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| Abstract: & ECL/TTL 1 Y1 2 Y2 3 Y3 4 Y4 9 Y5 10 Y6 11 Y7 12 Y8 This symbol is in , HOUSTON, TEXAS 77251-1443 · 9 10 Y5 Y6 11 Y7 12 Y8 SN100KT5541 SN100KT5541 OCTAL ECLTOTTL , Control Inputs Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 , 1.7 4 6.2 2.5 5.1 7.7 2.1 4.3 6.4 1.1 3.7 6.3 UNIT ns ns ns ... | Original |
9 pages, |
SN100KT5541NT SN100KT5541DW SN100KT5541 SN100KT5541 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| _rn5 fdce_rn13 fdce_dn5 fdce_dn11 fds6 w_addr_lut0 ldc1 fdce_rn4 fdce_rn12 fdce_dn4 fdce_dn10 X0Y6 X1Y6 X2Y6 X3Y6 X4Y6 X5Y6 X6Y6 X7Y6 w_addr_out_lut fds3 fdcn1 fdce_rp7 fdce_rp15 fdce_dp7 fdce_dp11 fds2 _rp4 fdce_rp12 fdce_dp4 fdce_dn8 X0Y4 X1Y4 X2Y4 X3Y4 X4Y4 X5Y4 X6Y4 X7Y4 fds1 fds9 fdce_rn3 fdce_rn11 fd_pint3 fdce_rp3 fdce_rp11 fdce_dp3 fd_pint0 fd_pint2 fdce_rp2 fdce_rp10 fdce_dp2 fdce_rp1 fdce_rp9 www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (Placement.xls) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| Sheet1 Sheet2 Sheet3 LUT FF LUT FF LUT FF LUT FF LUT FF LUT FF LUT FF LUT FF X0Y8 X1Y8 X2Y8 X3Y8 X4Y8 X5Y8 X6Y8 X7Y8 fd_db15 fd_d31 fd_db31 muxn7 fd_db7 fd_d23 fd_db23 muxn6 muxp11 fd_db14 fd_d30 fd_db30 muxn5 fd_db6 fd_d22 fd_db22 muxn4 muxn11 X0Y6 X1Y6 X2Y6 X3Y6 X4Y6 X5Y6 X6Y6 X7Y6 fd_db13 fd_d29 fd_db29 muxn3 fd_db5 fd_d21 fd_db21 muxn2 muxp10 fd_db12 fd_d28 fd_db28 muxn1 fd_db4 df_d20 fd_db20 muxn0 muxn10 X0Y4 X1Y4 X2Y4 X3Y4 X4Y4 X5Y4 X6Y4 X7Y4 fd_db11 fd_d27 fd_db27 muxp7 fd_db3 fd_d19 fd www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (Placement.xls) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| 3, y4 PIN 13,14,15,16; y5, y6, y7, Pin20 PIN 17,18,19,20; y0,y1,y2,y3,y4,y5,y6,y7 ISTYPE 'Com'; y0,y1,y2,y3,y4,y5,y6,y7 ISTYPE 'Invert'; X,K,Z,C,P,U,D = .X & s2 & data ); y5.OE = (enb ); !y6 = (!s0 & s1 & s2 & data ); y6.OE = (enb ); !y7 = (s ,y5,y6,y7]) [0,0,0,1,1]->[0,1,1,1,1,1,1,1]; [1,0,0,1,1]->[1,0,1,1,1,1,1,1]; [0,1,0,1 APEEL(tm) V3.30 Tue Nov 11 11:54:35 APEEL FILE: PEEL18CV8 PEEL18CV8 PEEL18CV8 PEEL18CV8 4-bit counter with 2 input mux Designer www.datasheetarchive.com/download/54803669-39594ZC/test102.zip (DMUX1T8.AB1) |
Atmel | 19/01/1998 | 463.64 Kb | ZIP | test102.zip |
| .10 Module_Port LA9 X= 17.60,Y= 6.10 Module_Port LA10 X= 17.60,Y= 6.10 Module_Port LA11 X= 17.60,Y .50,Y= 5.60 Input U9,PD2 X= 11.80,Y= 6.10 Input U8,NC X= 15.50,Y= 6.10 Input U9,NC X= 11.80,Y= 6.20 Input U8,NC X= 15.50,Y= 6.20 Input U9,NC X= 11.80,Y= 6.30 Input U8,NC X= 15.50,Y= 6.30 Input U9,NC X= 11.80,Y= 6.50 Input X= 10.30,Y= 6.20 Input P8,K X= 11.20,Y= 6.20 Input P8,K X= 14.70,Y= 6 www.datasheetarchive.com/download/16621423-847737ZC/rf11sch-v1.zip (ref.NC) |
STMicroelectronics | 16/12/1998 | 267.11 Kb | ZIP | rf11sch-v1.zip |
| \9$:$/&9$W&-&Q#YF1"1=E]/7=CGE89 CGE89 "'48 #" M% >IZZ.KMM C 6 M"0)OE: > M?4" %@M^=;&@@18+(FBQH(6"S www.datasheetarchive.com/download/37542492-960430ZC/4kefixsn.uue |
Xilinx | 05/09/1996 | 1804.08 Kb | UUE | 4kefixsn.uue |
| ) ; xlat ( ) to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11 ,y2,y3,y4,y5,y6,y7,y8,y9) to (15,14,13,12, 1, 2, 3, 4, 5, 6, 7, 9,10,11) ; } part 54l72 /Demultiplexer" ; newattr "$ttlout" = "TP" ; pin ( , y14 Decimal Decoder" ; newattr "$ttlout" = "TP" ; pin ( ) ; net "vss" : (8) ; net "vcc" : (16) ; xlat ( ) to (15 www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |
| . INST "The.0.SandT/inttwoenasync" RLOC = "X1Y6" ; INST "The.0.SandT/intsyncin" RLOC = "X0Y /intdatmuxtwonot[2]" RLOC = "X4Y7" ; INST "The.0.Rx/intdatmuxtwonot[1]" RLOC = "X4Y6" ; INST "The.0.Rx/intdatmuxtwonot[0]" RLOC = "X4Y6" ; INST "The.0.Rx/intdatmuxtwo[3]" RLOC = "X4Y5" ; INST "The.0.Rx /intdatmuxtre[0]" RLOC = "X4Y0" ; INST "The.0.Rx/intdatmuxonenot[3]" RLOC = "X5Y6" ; INST "The.0.Rx/intdatmuxonenot[2]" RLOC = "X5Y6" ; INST "The.0.Rx/intdatmuxonenot[1]" RLOC = "X5Y4" ; INST "The.0.Rx www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (DdrReceiver.ncf) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| T/intltchsyncneg" RLOC = "X1Y6" ; INST "The.0.SandT/Phase71" RLOC = "X0Y4" ; INST "The.0.SandT/Phase02 T/NegPhaseRegEna" RLOC = "X0Y6" ; INST "The.0.SandT/DatEnaOut" RLOC = "X1Y3" ; INST "The.0.Sand ]" RLOC = "X4Y7" ; INST "The.0.Mux/intdataint[30]" RLOC = "X4Y6" ; INST "The.0.Mux/intdataint[29 ]" RLOC = "X4Y7" ; INST "The.0.Mux/intdataint[22]" RLOC = "X4Y6" ; INST "The.0.Mux/intdataint[21 ]" RLOC = "X3Y7" ; INST "The.0.Mux/intdatain[30]" RLOC = "X3Y6" ; INST "The.0.Mux/intdatain[29 www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (DdrTransmitter.ncf) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| T/intltchsyncneg" RLOC = "X4Y6" ; INST "The.0.SandT/Phase71" RLOC = "X5Y4" ; INST "The.0.SandT/Phase02 T/NegPhaseRegEna" RLOC = "X5Y6" ; INST "The.0.SandT/DatEnaOut" RLOC = "X4Y3" ; INST "The.0.Sand ]" RLOC = "X1Y7" ; INST "The.0.Mux/intdataint[30]" RLOC = "X1Y6" ; INST "The.0.Mux/intdataint[29 ]" RLOC = "X1Y7" ; INST "The.0.Mux/intdataint[22]" RLOC = "X1Y6" ; INST "The.0.Mux/intdataint[21 ]" RLOC = "X2Y7" ; INST "The.0.Mux/intdatain[30]" RLOC = "X2Y6" ; INST "The.0.Mux/intdatain[29 www.datasheetarchive.com/download/35631323-996047ZC/xapp764.zip (DdrTransmitter.ncf) |
Xilinx | 27/05/2004 | 9655.66 Kb | ZIP | xapp764.zip |
| PIN,A6,1-1,5,23,I PIN,Y6,1-1,5,22,O ) (SYM,5 DATA,2,U5 DATA,3,TBUF PIN,*000001,1-1,5,23,T ,1-1,5,Y5 SIG,A6,1-1,5,A6 > SIG,A7,1-1,5,A7 SIG,Y7,1-1,5,Y7 SIG,G1B,1-1,5,G1B SIG,G2B,1 PINLIST,2 (DRAWING,ORCAD.PIN,1-1 (SYM,1 DATA,2,U1 DATA,3,OR2 PIN,*000001,1-1,5,21,O PIN,G1B,1-1,5,23,1 PIN,G2B,1-1,5,23,2 ) (SYM,2 DATA,2,U2 DATA,3,TBUF PIN,*000001,1-1,5,23,T PIN,A8,1-1,5,23,I PIN,Y8,1-1,5,22,O ) (SYM,3 DATA,2,U3 DATA,3,TBUF PIN,*000001,1-1,5,23,T www.datasheetarchive.com/download/43031979-958119ZC/or4sdt3.zip (HX541.PIN) |
Xilinx | 05/09/1996 | 499.51 Kb | ZIP | or4sdt3.zip |