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Part : XENB1181 Supplier : Schneider Electric Manufacturer : Newark element14 Stock : - Best Price : $46.01 Price Each : $49.96
Part : XENB1191 Supplier : Schneider Electric Manufacturer : Newark element14 Stock : - Best Price : $60.56 Price Each : $69.76
Part : XENB1491 Supplier : Schneider Electric Manufacturer : Newark element14 Stock : - Best Price : $60.56 Price Each : $69.76
Part : XENB1181 Supplier : Schneider Electric Manufacturer : Farnell element14 Stock : - Best Price : £40.44 Price Each : £43.91
Part : XENB1181 Supplier : Schneider Electric Manufacturer : Sager Stock : - Best Price : $39.10 Price Each : $43.29
Part : XENB1191 Supplier : Schneider Electric Manufacturer : Sager Stock : - Best Price : $52.68 Price Each : $58.32
Part : XENB1491 Supplier : Schneider Electric Manufacturer : Sager Stock : - Best Price : $52.68 Price Each : $58.32
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XENB

Catalog Datasheet MFG & Type PDF Document Tags

XG02

Abstract: xb22 57 XENB 98 FRP Timing Generator Block ­2­ CXD3508ATQ VSS XB11 XB01 VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 OE1 , output - 57 XENB O ENB pulse output (inverse) - 58 VCK O VCK pulse output , 100 0.2 ENB, XENB V IOH1 = ­0.50mA VDD ­ 0.2 R01, R11, R21, R31, R02, R12, R22, R32, XR01 , ­ GND (100 ­ 10%) 80 tREP ENB pulse output fall time Conditions ENB, XENB tFEP
Sony
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ACX704AKM XG02 xb22 diagram sony lcd tv xg32 DOT320 sony 32" TV lcd power supply E00947 CXD3519TQ 100PIN TQFP-100P-L021 P-TQFP100-14

XG02

Abstract: XB12 ENB 57 XENB 98 FRP Timing Generator Block ­2­ CXD3508ATQ Pin Configuration XHCK2 XHCK1 XHST2 XHST1 XVCK XENB XOE2 XOE1 HCK2 HCK1 XVST HST2 HST1 XB22 XB12 , XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 I/O O O O O O O O O O O O O O O O , , B1, B2, B3, Hsync/DENB, Vsync, MCK, PCI CLR TEST1, TEST2, SLIN, TESTV, FA, TESTP ENB, XENB IOH1 = , VDD (0 ­ 90%) VDD ­ GND (100 ­ 10%) 30 ns 30 60 ns 60 80 ns 80 ENB, XENB tFEP HCK1, HCK2
Sony
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XB12 B1137 g-31

diagram sony lcd tv

Abstract: l021 GEN. 58 VCK 59 XVCK 56 ENB 57 XENB 98 FRP Timing Generator Block ­2­ CXD3508BTQ VSS XB11 XB01 VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 , O ENB pulse output - 57 XENB O ENB pulse output (inverse) - 58 VCK O , . Applicable pins ENB, XENB R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12 , output fall time ­ Min. ENB, XENB tFEP HCK1, HCK2, XHCK1, XHCK2, DATA setup time
Sony
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l021 g1134 g21 Transistor E00Z21

ACX706AKM

Abstract: diagram sony lcd tv CLR F9 V Timing Pulse GEN. J4, J3 VCK, XVCK K4, K3 ENB, XENB Timing Generator Block VDD2 , HCK1 XENB ENB XG11 XR01 B01 G01 B0 B1 B2 B3 XVST VSS1 XB01 , VST pulse inversion output - K4 ENB O ENB pulse output - K3 XENB O ENB , , B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = ­4.0mA VST, XVST, ENB, XENB, OE1 , 35 VCK, XVCK, VST, XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO GND ­ VDD (0 ­ 90
Sony
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CXD3513GG ACX706AKN ACX706AKM ACX706AK TFBGA128 ACX706AKM/AKN E01407B1Z 128PIN
Abstract: , XENB Timing Generator Block VDD2 (5.0V) B2, D2, D7 VSS1 (GND) F10 TESTO B4, D3, F4 , B31 G0 G1 G2 G3 XHCK1 HCK1 XENB ENB XG11 XR01 B01 G01 B0 B1 , '" K3 XENB O ENB pulse inversion output â'" J4 VCK O VCK pulse output â , , XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = â'"4.0mA VST, XVST, ENB, XENB, OE1, XOE1, OE2 , â'" GND (100 â'" 10%) â'" â'" 35 VCK, XVCK, VST, XVST, ENB, XENB, OE1, OE2, XOE1 Sony
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TFBGA-128P-061 P-TFBGA128-11

xb22

Abstract: xg32 57 XENB 98 FRP Timing Generator Block ­2­ CXD3508TQ VSS XB11 XB01 VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 OE1 , pulse output - 57 XENB O ENB pulse output (inverse) - 58 VCK O VCK pulse , 0V CLR 0.9 µA 3.0 µA VI = VDD 10 IOL1 = 0.75mA 100 0.2 ENB, XENB V , tREP ENB pulse output fall time Conditions ENB, XENB tFEP HCK1, HCK2, XHCK1, XHCK2
Sony
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TQFP-100P-L111 XG11 sony lcd tv power supply circuit diagram sync to HSYNC and VSYNC converter E00228-PS CXD2475TQ P-TQFP100-14X14-0 42ALLOY

xg32

Abstract: xb22 ENB 57 XENB 98 FRP Timing Generator Block ­2­ CXD3508TQ Pin Configuration XHCK2 XHCK1 XHST2 XHST1 XVCK XOE1 XOE2 HCK2 HCK1 XENB HST2 HST1 XVST XB22 XB12 , XG01 XB31 XB21 VDD VSS XB11 XB01 VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 , , B1, B2, B3, Hsync/DENB, Vsync, MCK, PCI CLR TEST1, TEST2, SLIN, TESTV, FA, TESTP ENB, XENB IOH1 = , VDD (0 ­ 90%) VDD ­ GND (100 ­ 10%) 30 ns 30 60 ns 60 80 ns 80 ENB, XENB tFEP HCK1, HCK2
Sony
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diagram power supply sony 32 in LCD TV circuits
Abstract: K4, K3 ENB, XENB Timing Generator Block VDD2 (5.0V) B2, D2, D7 VSS1 (GND) F10 TESTO B4 , XG01 VDD1 XR31 B31 G0 G1 G2 G3 XHCK1 HCK1 XENB ENB XG11 XR01 , '" K4 ENB O ENB pulse output â'" K3 XENB O ENB pulse inversion output â , , B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = â'"4.0mA VST, XVST, ENB, XENB , , VST, XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO GND â'" VDD (0 â'" 90%) â'" â Sony
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E01407-PS

xb22

Abstract: XB12 58 VCK 59 XVCK 56 ENB 57 XENB 98 V Timing Pulse GEN. HCK2 54 V , O VST pulse output (inverse) - ENB 56 O ENB pulse output - XENB 57 O , ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 OE1 , , XENB © Sunplus Technology Co., Ltd. Proprietary & Confidential |IIL2| 10 - 100 |IIH2 , , B02, B12, B22, XB02, XB12, XB22, XB31 GND-VDD ENB pulse output rise time ENB, XENB (0
Sunplus Technology
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SPLC3508A SPLC2475A XR02

SIGNAL PATH designer

Abstract: IDT74FCT16260 , xCLAV, xENB Clock Pin, Cell Available Pin, Enable Pin 4067 tbl 02 Table 2 Comparison of DPI and , throttle the data into the UTOPIA device based on the state of Transmit xENB and Transmit xCLAV. Transmit xENB must be able to halt transmission of data within one clock cycle of going inactive, although the , throttle the data into the DPI device based on the state of Transmit xENB and Transmit xCLAV. Transmit xENB has to halt transmission of data within 1 clock cycle after it goes inactive, while the
Integrated Device Technology
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IDT77V400 SIGNAL PATH designer IDT74FCT16260 AB-171

HSYNC, VSYNC input output

Abstract: xb22 Timing Pulse GEN. J4, J3 VCK, XVCK K4, K3 ENB, XENB Timing Generator Block VDD2 (5.0V) B2 , HCK2 XVCK VCK XG01 VDD1 XR31 B31 G0 G1 G2 G3 XHCK1 HCK1 XENB , output - K4 ENB O ENB pulse output - K3 XENB O ENB pulse inversion output , , XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = ­4.0mA VST, XVST, ENB, XENB, OE1, XOE1, OE2, XOE2, TESTO , , XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO GND ­ VDD (0 ­ 90%) - - 50 VDD ­
Sony
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CXD3521GG HSYNC, VSYNC input output ACX*AKM sony lcd tv circuits diagrams ACX704AKM/BKM E01408-PS

lcd Inverter Delta

Abstract: 18HV V -1.0 to +17 V STH, XSTH, CKH1, CKH2 STV, XSTV, CKV1, CKV2, ENB, XENB, PCG, XPCG , VVSS VSS for V drive 8 XENB Inverted signal of ENB 9 ENB 10 VVDD 11 CSV , .STH 19.XSTH 18.HVSS 17.CSH 16.G 15.R 14.B 13.PCD 12.NC 11.CSV 10.VVDD 9.ENB 8.XENB 7.VVSS 6
SANYO Electric
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ALP234FCX LV4139W lcd Inverter Delta 18HV ENN6764 LV4131W LV4133W

lcd Inverter Delta

Abstract: IC 8 PIN 2267 to +14 V -1.0 to +14 V STH, XSTH, CKH1, CKH2 STV, XSTV, CKV1, CKV2, ENB, XENB , Enable signal 10 XENB 11 PCD 12 B Video signal (B) 13 R Video signal (R , .CKH2 20.STH 19.XSTH 18.CSH 17.PCG 16.XPCG 15.VSS 14.G 13.R 12.B 11.PCD 10.XENB 9.ENB 8.CSV 7
SANYO Electric
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ALR122FNX LV4135W LV4137W IC 8 PIN 2267 LV4137 ENN6773

LV4137W

Abstract: LV4135W , CKV2, ENB, XENB, PCG, XPCG -1.0 to +14 V -1.0 to +14 V VG, VR, VB, VPCD , 10 XENB 11 PCD 12 B Video signal (B) 13 R Video signal (R) 14 G , .B 11.PCD 10.XENB 9.ENB 8.CSV 7.XSTV 6.STV 5.VVDD 4.CKV2 3.CKV1 2.COM 1.NC No.6753-4/8
SANYO Electric
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ALP121AAX XENB ENN6753

ACX706AKM

Abstract: xg32 CLR F9 V Timing Pulse GEN. J4, J3 VCK, XVCK K4, K3 ENB, XENB Timing Generator Block VDD2 , HCK1 XENB ENB XG11 XR01 B01 G01 B0 B1 B2 B3 XVST VSS1 XB01 , VST pulse inversion output - K4 ENB O ENB pulse output - K3 XENB O ENB , , B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = ­4.0mA VST, XVST, ENB, XENB, OE1 , 35 VCK, XVCK, VST, XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO GND ­ VDD (0 ­ 90
Sony
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E01407A17

1431T transistor

Abstract: TRANSISTOR 1431T DATA , ENB,XENB -1.0 to +10 V G, R, B, DSD -1.0 to +8 V Symbol Ratings Unit , 5 6 7 8 9 10 11 12 13 14 15 16 17 COM CKV1 CKV2 STV XSTV VVDD ENB XENB CSV , ) COM SC LV4141W ALP248 DSD LV4149W CKH1/CKH2, STH/XSTH CKV1/CKV2, STV/XSTV, ENB/XENB , ,VB) COM SC LC15007 ALP248 DSD CKH1/CKH2, STH/XSTH CKV1/CKV2, STV/XSTV, ENB/XENB DSG
SANYO Energy
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ALP248CGX 1431T transistor TRANSISTOR 1431T DATA 1431T 1431T 5 transistor 2sc1213 datasheet 1431T E031118

LV4133W

Abstract: transistors 13001 to +17 V -1.0 to +17 V STH, XSTH, CKH1, CKH2 STV, XSTV, CKV1, CKV2, ENB, XENB , control signal (H : Normal scan, L : Reverse scan) 9 ENB Enable signal 10 XENB 11 PCD , .HVDD 22.CKH1 21.CKH2 20.STH 19.XSTH 18.CSH 17.PCG 16.XPCG 15.VSS 14.G 13.R 12.B 11.PCD 10.XENB
SANYO Electric
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ALP233FXX transistors 13001 13001 datasheet transistor 13001 ENN6763

67551

Abstract: LV4137 , CKH2 STV, XSTV, CKV1, CKV2, ENB, XENB, PCG, XPCG -1.0 to +14 V -1.0 to +14 V , Enable signal 10 XENB 11 PCD 12 B Video signal (B) 13 R Video signal (R , .G 13.R 12.B 11.PCD 10.XENB 9.ENB 8.CSV 7.XSTV 6.STV 5.VVDD 4.CKV2 3.CKV1 2.COM 1.NC No
SANYO Electric
Original
ALP121AXX 67551 13001 13001 s ENN6755

SIGNAL PATH designer

Abstract: IDT74FCT16260 xSOC Start of cell Signal Pin xCLK Clock Pin xCLK, xCLAV, xENB Clock Pin, Cell Available , Transmit xENB and Transmit xCLAV. Transmit xENB must be able to halt transmission of data within one , into the DPI device based on the state of Transmit xENB and Transmit xCLAV. Transmit xENB has to halt
Integrated Device Technology
Original

g22 touch

Abstract: lcd color sony Vertical Driver with Level Shifters VVDD, VVSS1, VVSS2 VST, XVST, ENB, XENB, VCK, XVCK TEST1, TEST2 , , XOE1, OE2, XOE2, TEST4, TEST5 · V driver pulse input pin voltage VST, XVST, VCK, XVCK, ENB, XENB , Data input 34 ENB Pulse input 69 XG02 Data input 35 XENB Pulse input 70 , conversion circuit × 2 VVSS1 (7) ENB, XENB VVDD VVDD 850 EBN 850 XEBN VVSS1 Level , trenb 80 ns ENB, XENB ENB pulse fall time tfenb 80 ns HCK duty Dhck 48
Sony
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g22 touch lcd color sony xg22 sony qvga 2.8 acx R2M 45 R2M diode BHSR-02VS-1
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