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XDRA2-PICEICM232-2 Advantech 2 PORT ISOLATED SERIAL - Bulk (Alt: XDRA2-PICEICM232-2) from $462.4051 (Dec 2016) Avnet Buy
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XDRI459AIZEQQ1 Texas Instruments N/A 20 (Nov 2016) Rochester Electronics Buy
XDRI459BIZEQQ1 Texas Instruments N/A 110 (Nov 2016) Rochester Electronics Buy
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XDRV3201QPAPRQ1 Texas Instruments Analog / Linear ICs (S&D, non Std., MPP) Part 2 - Tape and Reel (Alt: XDRV3201QPAPRQ1) (Oct 2016) Avnet Buy

XDR 150 datasheet

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: . 150 Table 5-7. XDR Memory Serial Interface Signals: Channel 1 , Document Name Rambus BE-XIO Specification (DD2.0) - Addendum to DL-0153 DL-0153 XDR IO Cell Datasheet (DL , . Referencing Signal Names from the Datasheet , . 2.2.2 Initialization of MIC, XDR I/O Cells, and XDR DRAM , . 2.2.2.5 Step 4: XDR DRAM Initialization ... Original
datasheet

222 pages,
1368.87 Kb

EDX5116ACSE DRAM 2164 DL-0172 d870 DL-0161 DL-153 DL-130 D880 cell broadband DL-0171 2006 international 9400 wiring diagram Rambus XDR toshiba f630 d880 transistor DL-0159 DL-0178 t d880 transistor d880 TEXT
datasheet frame
Abstract: -0153 XDR IO Cell Datasheet (DL-187 DL-187) 1. This document contains Rambus proprietary information. Contact , . Referencing Signal Names from the Datasheet , . 2.2.2 Initialization of MIC, XDR I/O Cells, and XDR DRAM , . 2.2.2.5 Step 4: XDR DRAM Initialization . 2.2.2.6 Step 5.1: XDR DRAM Load ... Original
datasheet

222 pages,
1355.66 Kb

DL-0172 90 nm CMOS YellowStone LOG rX2 1326 DL-0161 cell broadband sony x35 d880 transistor Rambus XDR DL-0178 D880 2006 international 9400 wiring diagram DL-0171 yc 2604 replacement transistor D880 toshiba 2685 XDR Rambus sony bx 1387 TEXT
datasheet frame
Abstract: clock for the XDR Clock Generator (CDCD5704 CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply ... Texas Instruments
Original
datasheet

9 pages,
198.93 Kb

DDP2230 CDCDLP223 SCAS836 TEXT
datasheet frame
Abstract: VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k ... Texas Instruments
Original
datasheet

9 pages,
319.56 Kb

JESD22 dlp dmd chip CDCDLP223 300MHZ 20MHZ 100MHZ ddp2230 SCAS836 TEXT
datasheet frame
Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 ICS9214 Advance Information Rambus 800 MHz XDR Clock , support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock , solution. Figure 1 shows the major components of the ICS9214 ICS9214 XDR Clock Generator. These include the a PLL , multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other , -Pin 4.4mm TSSOP 0809-04/12/04 XDR is a trademark of Rambus ADVANCE INFORMATION documents contain ... Integrated Circuit Systems
Original
datasheet

15 pages,
202.13 Kb

ICS9214 TEXT
datasheet frame
Abstract: VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k ... Texas Instruments
Original
datasheet

9 pages,
321.26 Kb

JESD22 CRYSTAL 20 mhZ CDCDLP223 300MHZ 20MHZ 100MHZ ddp2230 SCAS836 TEXT
datasheet frame
Abstract: VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k ... Texas Instruments
Original
datasheet

9 pages,
333.51 Kb

JESD22 dlp dmd chip Crystal oscillator 20 MHz CDCDLP223 300MHZ 20MHZ 100MHZ chip dmd ti dlp ddp2230 SCAS836 TEXT
datasheet frame
Abstract: clock for the XDR Clock Generator (CDCD5704 CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply ... Texas Instruments
Original
datasheet

9 pages,
200.47 Kb

DDP2230 CDCDLP223 SCAS836 TEXT
datasheet frame
Abstract: clock for the XDR Clock Generator (CDCD5704 CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply ... Texas Instruments
Original
datasheet

10 pages,
529.04 Kb

CDCDLP223 SCAS836 TEXT
datasheet frame
Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 ICS9214 Rambus General Description XDR Clock , frequency multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is , clock TM signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock , interface solution. Figure 1 shows the major components of the ICS9214 ICS9214 XDR Clock Generator. These include , +0.5 V 0°C to +70°C ­65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may ... Integrated Device Technology
Original
datasheet

18 pages,
302.24 Kb

F 9214 ICS9214 TEXT
datasheet frame

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