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HSP50214BVI Intersil Corporation Programmable Downconverter; MQFP120; Temp Range: See Datasheet visit Intersil Buy
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CP82C50A-5 Intersil Corporation CMOS Asynchronous Communications Element; PDIP40, PLCC44; Temp Range: See Datasheet visit Intersil Buy
CP82C50A-5Z Intersil Corporation CMOS Asynchronous Communications Element; PDIP40, PLCC44; Temp Range: See Datasheet visit Intersil Buy

XDR 150 datasheet

Catalog Datasheet MFG & Type PDF Document Tags

Cell Broadband Engine CMOS SOI 65 nm Hardware Initialization Guide

Abstract: Cell Broadband Engine Hardware Initialization Guide . 150 Table 5-7. XDR Memory Serial Interface Signals: Channel 1 , Document Name Rambus BE-XIO Specification (DD2.0) - Addendum to DL-0153 XDR IO Cell Datasheet (DL , . Referencing Signal Names from the Datasheet , . 2.2.2 Initialization of MIC, XDR I/O Cells, and XDR DRAM , . 2.2.2.5 Step 4: XDR DRAM Initialization
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DL-0178 Cell Broadband Engine CMOS SOI 65 nm Hardware Initialization Guide Cell Broadband Engine Hardware Initialization Guide transistor d880 t d880 DL-0159 2007--P

Sony Semiconductor Replacement Handbook 1991

Abstract: sony bx 1387 -0153 XDR IO Cell Datasheet (DL-187) 1. This document contains Rambus proprietary information. Contact , . Referencing Signal Names from the Datasheet , . 2.2.2 Initialization of MIC, XDR I/O Cells, and XDR DRAM , . 2.2.2.5 Step 4: XDR DRAM Initialization . 2.2.2.6 Step 5.1: XDR DRAM Load
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Sony Semiconductor Replacement Handbook 1991 sony bx 1387 XDR Rambus toshiba 2685 yc 2604 replacement DL-0171

ddp2230

Abstract: dlp dmd chip VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k
Texas Instruments
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CDCDLP223 JESD22 ddp2230 dlp dmd chip 100MHZ 20MHZ 300MHZ SCAS836 TSSOP20 A114-C MIL-STD-883

DDP2230

Abstract: clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply
Texas Instruments
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Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 Advance Information Rambus 800 MHz XDR Clock , support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock , solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include the a PLL , multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other , -Pin 4.4mm TSSOP 0809-04/12/04 XDR is a trademark of Rambus ADVANCE INFORMATION documents contain Integrated Circuit Systems
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MO-153

ddp2230

Abstract: 100MHZ VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k
Texas Instruments
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CRYSTAL 20 mhZ

ddp2230

Abstract: chip dmd ti dlp VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k
Texas Instruments
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chip dmd ti dlp Crystal oscillator 20 MHz

DDP2230

Abstract: clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply
Texas Instruments
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Abstract: clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply Texas Instruments
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ISO/TS16949

F 9214

Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 Rambus General Description XDR Clock , frequency multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is , clock TM signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock , interface solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include , +0.5 V 0°C to +70°C ­65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may
Integrated Device Technology
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F 9214 9214DGLF PGG28 9214DGLFT

ICS9214

Abstract: SMBA1 Integrated Circuit Systems, Inc. TM TM ICS9214 Advance Information Rambus 800 MHz XDR Clock , support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock , solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include the a PLL , multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other , ODCLK_T3 ODCLK_C3 SMBDAT SMB_A0 SMB_A1 28-Pin 4.4mm TSSOP 0809-08/26/04 XDR is a trademark of
Integrated Circuit Systems
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SMBA1

ddp2230

Abstract: 100MHZ VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k
Texas Instruments
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ddp2230

Abstract: Crystal oscillator 20 MHz clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply
Texas Instruments
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F 9214

Abstract: 0809E Integrated Circuit Systems, Inc. TM TM ICS9214 Rambus General Description XDR Clock , frequency multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is , clock TM signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock , interface solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include , +0.5 V 0°C to +70°C ­65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may
Integrated Device Technology
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0809E
Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 Advance Information Rambus 800 MHz XDR Clock , support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock , solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include the a PLL , multipliers of: 3, 4, 5, 6, 8, 9/ 2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to , ODCLK_T3 ODCLK_C3 SMBDAT SMB_A0 SMB_A1 28-Pin 4.4mm TSSOP 0809-06/20/03 XDR is a trademark of Integrated Circuit Systems
Original
Abstract: Integrated Circuit Systems, Inc. TM TM ICS9214 Advance Information Rambus 800 MHz XDR Clock , support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock , solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include the a PLL , multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other , ODCLK_T3 ODCLK_C3 SMBDAT SMB_A0 SMB_A1 28-Pin 4.4mm TSSOP 0809-08/22/03 XDR is a trademark of Integrated Circuit Systems
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DDP2230

Abstract: Crystal oscillator 20 MHz VSS SCLK 10 11 VDD The 100 MHz HCLK output provides the reference clock for the XDR , 200-400 Mhz ±1.0% and ±1.5% SSC 150 KW EN 2-Wire Serial Interface Control Logic SCLK SDATA IREF VDD 150 KW IDO HCLK out VSS VDD TERMINAL FUNCTIONS PIN TYPE XIN , output for XDR clock generator 100 MHz 17 O HCLK Clock output for XDR clock generator 300 , IREF 20 EN 7 I LVTTL Output enable, 20 MHz, 100 MHz and 200­400 MHz outputs, 150 k
Texas Instruments
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SSC150

ddp2230

Abstract: clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply
Texas Instruments
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Abstract: clock for the XDR Clock Generator (CDCD5704). Spread-spectrum clocking with 0.5% down spread, which , 20 Mhz LVTTL XIN 100 Mhz SSC PLL 1 OUT = 100 Mhz ­0.5% SSC HCLK out VDD 150 KW EN SCLK 2 , IREF VDD 150 KW SDATA IDO VDD VSS TERMINAL FUNCTIONS TERMINAL XIN XOUT SDATA SCLK 20 , output, 20 MHz (buffered output from crystal oscillator) Clock output for XDR clock generator Clock output for XDR clock generator Clock output for DMD system Clock output for DMD system 3.3 V Power supply Texas Instruments
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rambus xdr

Abstract: Integrated Circuit Systems, Inc. ICS9214 Rambus XDR Clock Generator General Description The ICS9214 clock generator provides the TM necessary clock signals to support the Rambus XDR memory subsystem , components of the ICS9214 XDR Clock Generator. These include the a PLL, a Bypass Multiplexer and four , , 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other system clocks 2.5V power , ODCLK_C3 VDD2.5 SMBDAT SMB_A0 SMB_A1 28-Pin 4.4m m TSSOP 0809C-11/11/05 XDR is a trademark of
Integrated Circuit Systems
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rambus xdr 0809C--11/11/05
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