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XC95288XL pinout

Catalog Datasheet MFG & Type PDF Document Tags

XC95288XL pinout

Abstract: xc95288xl-10tqg144 0 R XC95288XL High Performance CPLD 0 5 DS055 (v2.0) March 22, 2006 Product , anc e · Low Po we r 94 MHz Description The XC95288XL is a 3.3V CPLD , XC95288XL © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents , XC95288XL High Performance CPLD R 3 JTAG Port 1 JTAG Controller In-System Programming Controller , 54 18 Function Block 16 Macrocells 1 to 18 DS055_02_101300 Figure 2: XC95288XL Architecture
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XC95288XL pinout xc95288xl-10tqg144 XC95288XL-10TQ144C XC95288XL-7TQG144I XC9500XL XAPP111 XAPP784 BG256 BG352 CS280

XC95288XL pinout

Abstract: XC95288XL 0 XC95288XL High Performance CPLD DS055 (v1.7) August 21, 2003 0 5 Features · · , 150 Description 100 The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage , _01_121501 Figure 1: Typical ICC vs. Frequency for XC95288XL © 2003 Xilinx, Inc. All rights reserved. All Xilinx , www.xilinx.com 1-800-255-7778 1 R XC95288XL High Performance CPLD 3 JTAG Port 1 JTAG , Function Block 16 18 Macrocells 1 to 18 DS055_02_101300 Figure 2: XC95288XL Architecture
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XC95288XL-10PQ208I XC95288XL-7PQ208I XC95288XL-7TQ144I XC95288XL-10TQ144I XC95288XL-10-PQ208 marking G18 TQ144 PQ208 XC95288XL-10BG256I XC95288XL-10FG256I FG256
Abstract: 0 XC95288XL High Performance CPLD DS055 (v1.6) May 27, 2003 0 5 Features â'¢ â , we r 94 MHz 150 Description 100 The XC95288XL is a 3.3V CPLD targeted for , Clock Frequency (MHz) DS055_01_121501 Figure 1: Typical ICC vs. Frequency for XC95288XL © 2003 , XC95288XL High Performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller , DS055_02_101300 Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line Xilinx
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XC95288XL-10CS280I

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 0 XC95288XL High Performance CPLD R DS055 (v2.1 April 3, 2007 0 5 Features · · , Xilinx WARNING: Programming temperature range of TA = 0° C to +70° C Description The XC95288XL , . DS055 (v2.1 April 3, 2007 Product Specification www.xilinx.com 1-800-255-7778 1 XC95288XL , Frequency (MHz) DS055_01_121501 Figure 1: Typical ICC vs. Frequency for XC95288XL 2 www.xilinx.com 1-800-255-7778 DS055 (v2.1 April 3, 2007 Product Specification XC95288XL High Performance CPLD R 3
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XC95288XL10TQG144I pinout XC95288XL PQG208 fgg256 XC95288XL-10TQG144C XC95288XL-7CS280C XC95288XL-10FGG256I

XAPP114

Abstract: A5E8 0 XC95288XL High Performance CPLD DS055 (v1.5) June 20, 2002 0 5 Features · · · , XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge , : Typical ICC vs. Frequency for XC95288XL © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks , 1-800-255-7778 1 R XC95288XL High Performance CPLD 3 JTAG Port 1 JTAG Controller , Block 16 18 Macrocells 1 to 18 DS055_02_101300 Figure 2: XC95288XL Architecture Function
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XAPP114 A5E8 w7510 XC95288

T9423

Abstract: w7510 0 XC95288XL High Performance CPLD DS055 (v1.4) March 19, 2001 0 5 Features · · · , ) DS055_01_101300 The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communi- Figure 1: Typical ICC vs. Frequency for XC95288XL © 2001 Xilinx, Inc , .4) March 19, 2001 Product Specification www.xilinx.com 1-800-255-7778 1 R XC95288XL High , DS055_02_101300 Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line
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T9423 k1739 W-7510

XC95288XL-10PQG208I

Abstract: XC95288XL-10TQ144I 0 XC95288XL High Performance CPLD DS055 (v1.8) July 15, 2004 0 5 Features · · · , we r 94 MHz 150 100 Description The XC95288XL is a 3.3V CPLD targeted for , Clock Frequency (MHz) DS055_01_121501 Figure 1: Typical ICC vs. Frequency for XC95288XL © 2003 , XC95288XL High Performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller , DS055_02_101300 Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line
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XC95288XL-10PQG208I XC95288XL-10PQG208C XAPP427 XC952 xc95288xl-7fg256c XC95288XL-10-TQ144 XC95288XL-10CSG280I CSG280

TQG144

Abstract: XC95288XL-10PQG208I 0 XC95288XL High Performance CPLD DS055 (v1.9) September 15, 2004 0 5 Features · , we r 94 MHz 150 100 Description The XC95288XL is a 3.3V CPLD targeted for , Clock Frequency (MHz) DS055_01_121501 Figure 1: Typical ICC vs. Frequency for XC95288XL © 2003 , XC95288XL High Performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller , DS055_02_101300 Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line
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TQG144 xc95288xl10pqg208c 6 pin diode n10 BGG256 marking j9 marking w13

xc9572xl pinout

Abstract: V1001 Virtex-II Pro: Pinout Tables 90 KB (v1.0) 01/31/02 510 KB (v1.0) 01/31/02 240 KB (v1.0) 01/31/02 , Functional Description Virtex-II: DC and Switching Characteristics Virtex-II: Pinout Tables 130 KB (v1 , Extended Memory: Pinout Tables 50 KB (v1.4) 04/02/01 560 KB (v2.0) 11/09/01 160 KB (v2.1_ 02/01/02 , Characteristics 50 KB (v2.2) 11/09/01 575 KB (v2.3) 11/09/01 180 KB (v2.7) 02/01/02 Virtex-E: Pinout , : DC and Switching Characteristics Virtex: Pinout Tables Virtex-E: Module Descriptions 02/01/02
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xc9572xl pinout V1001 CoolRunner XPLA3 CPLD Family xc4000 series fpgas xc95144 pinout XC95288XV Family Q1-02 XC9500 XC4000 XC3000 XC5200 XC2C64

XC9572XL TQG100

Abstract: XC9500XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1,600 3,200 6 , JTAG pins) Package(1) XC9536XL XC9572XL XC95144XL XC95288XL PC44 34 34 - - , in XC95144XL and XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability , changes while maintaining the same pinout. www.xilinx.com DS054 (v2.2) July 25, 2006 Product , Included hot socket reference; revised layout; BGA package change for XC95288XL 04/02/99 1.3 Minor
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XC9572XL TQG100 schematic of TTL XOR Gates XC9572XL TQ100 XC9572XL Series xc95144xl tqg144 PC44

xilinx jtag cable

Abstract: XC4000XL XC95144XL 144 3,200 144 5 3.7 3.5 178 XC95288XL 288 6,400 288 6 4.1 4.3 151 Table 2 , ) XC9536XL 34 36 36 XC9572XL 34 52 72 XC95144XL 81 117 XC95288XL 117 168 38 117 , XC95288XL X5899_01 Figure 10: I/O Block and Output Enable Capability The input buffer is compatible , features that enhance the ability to accept design changes while maintaining the same pinout. The , reference; revised layout; BGA package change for XC95288XL February 3, 1999 (Version 1.2) Xilinx
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xilinx jtag cable XC4000XL X5904

XC95288XL pinout

Abstract: Xilinx jtag cable pcb Schematic XC95288XL 288 6,400 288 6 4.0 3.8 208 Table 1: XC9500XL Device Family XC9536XL Macrocells Usable Gates , 36 - XC9572XL 34 34 34 34 38 38 52 52 72 72 - XC95144XL 81 81 117 117 117 117 - XC95288XL , Global OE 3 Available in XC95144XL and XC95288XL I/O/GTS4 Global OE 4 DS054 , ability to accept design changes while maintaining the same pinout. 12 www.xilinx.com DS054 (v2 , Included hot socket reference; revised layout; BGA package change for XC95288XL Minor typesetting
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Xilinx jtag cable pcb Schematic micron 3*3 resistor

schematic of TTL XOR Gates

Abstract: XC95144 : XC9500XL Device Family XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 , XC95144XL XC95288XL 44-pin PLCC 34 34 - - 44-pin VQFP 34 34 - - 48 , XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability The input buffer is , same pinout. www.xilinx.com 1-800-255-7778 DS054 (v1.6) January 24, 2002 Preliminary Product , 2/3/99 1.2 Included hot socket reference; revised layout; BGA package change for XC95288XL
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XC95144 HW-130 xc9572xl pin

XC9500XL

Abstract: XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates , XC95144XL XC95288XL PC44 34 34 - - PCG44 34 34 VQ44 34 34 - - , XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability The input buffer is , changes while maintaining the same pinout. www.xilinx.com 1-800-255-7778 DS054 (v1.9) November 11 , ; revised layout; BGA package change for XC95288XL 04/02/99 1.3 Minor typesetting corrections
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xc9572xl vqg

Abstract: xc95144xl XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1,600 , User I/O Pins (not including 4 dedicated JTAG pins) XC9536XL XC9572XL XC95144XL XC95288XL , XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability The input buffer is , changes while maintaining the same pinout. www.xilinx.com 1-800-255-7778 DS054 (v1.8) August 2 , ; revised layout; BGA package change for XC95288XL 04/02/99 1.3 Minor typesetting corrections
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xc9572xl vqg xc9572xl -vqg xc9572xl 64pin

XC9572XL TQ100

Abstract: XC9500XL XC95288XL 288 6,400 288 6 4.0 3.8 208 Table 1: XC9500XL Device Family XC9536XL Macrocells Usable Gates , 36 - XC9572XL 34 34 34 34 38 38 52 52 72 72 - XC95144XL 81 81 117 117 117 117 - XC95288XL , Global OE 3 Available in XC95144XL and XC95288XL I/O/GTS4 Global OE 4 DS054 , ability to accept design changes while maintaining the same pinout. 12 www.xilinx.com DS054 (v2 , change for XC95288XL Minor typesetting corrections. Minor typesetting corrections. Added CS280 package
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XC9572XL

Abstract: XC9500 pqg208 XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1,600 3,200 6 , JTAG pins) Package(1) XC9536XL XC9572XL XC95144XL XC95288XL PC44 34 34 - - , in XC95144XL and XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability , changes while maintaining the same pinout. www.xilinx.com DS054 (v2.0) July 15, 2005 Product , ; BGA package change for XC95288XL 04/02/99 1.3 Minor typesetting corrections. 06/07/99
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XC9500 pqg208

Xilinx jtag cable Schematic

Abstract: socket cpld Registers tPD (ns) tSU (ns) tCO (ns) fSYSTEM (MHz) XC9572XL XC95144XL XC95288XL 36 800 36 , XC95144XL 81 117 XC95288XL 117 168 38 117 192 192 5-5 5 R FastFLASHTM XC9500XL , Global OE 2 I/O/GTS3 I/O/GTS4 Global OE 3 Available in XC95144XL and XC95288XL Global OE , same pinout. The XC9500XL architecture provides for superior pin-locking characteristics with a , hot socket reference; revised layout; BGA package change for XC95288XL V1.3 and V1.4 Minor
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Xilinx jtag cable Schematic socket cpld

XC9572XL

Abstract: XC95288XL pinout XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1,600 3,200 6 , XC95288XL PC44 34 34 - - PCG44 34 34 VQ44 34 34 - - VQG44 34 , XC95288XL DS054_10_042101 Figure 10: I/O Block and Output Enable Capability The input buffer is , while maintaining the same pinout. www.xilinx.com 12 R XC9500XL High-Performance CPLD Family , /99 1.2 Included hot socket reference; revised layout; BGA package change for XC95288XL. 04
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VQ44

XC95288XL pinout

Abstract: xc9500 jtag cable 178 XC95288XL 288 6,400 288 7 4.8 4.5 125 © 2001 Xilinx, Inc. All rights reserved. All Xilinx , XC9572XL 34 34 52 72 38 XC95144XL 81 117 117 XC95288XL 117 168 192 192 192 R 3 JTAG Port JTAG , Global OE 3 Available in XC95144XL and XC95288XL I/O/GTS4 Global OE 4 DS054 , ability to accept design changes while maintaining the same pinout. 12 www.xilinx.com 1-800-255-7778 , XC95288XL Minor typesetting corrections. Minor typesetting corrections. Added CS280 package Added DS054 data
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xc9500 jtag cable
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