500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
TPC8407,LQ(S Toshiba America Electronic Components Trans MOSFET N/P-CH 30V 9A/7.4A 8-Pin SOP visit Digikey Buy
TPC8408,LQ(S Toshiba America Electronic Components Trans MOSFET N/P-CH 40V 6.1A/5.3A 8-Pin SOP visit Digikey Buy
XCTUBES-PC84 Xilinx XILINX SPARE 84PC TUBES visit Digikey Buy
HPC-8424SE-R8A1E Advantech Co Ltd 4U STORAGE CHASSIS ATX/EATX visit Digikey Buy

XC2018 PC84

Catalog Datasheet MFG & Type PDF Document Tags

XC2000

Abstract: XC2018 PC84 family has two members, the XC2064 and XC2018. Even the larger XC2018 should fit in the smallest XC5200 , family. Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 , Resources Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84, PQ100, VQ100, Packages , PC84, PQ100, VQ100, PQ160, TQ144, TQ176, PG191, PQ208 PC84, PC84, PQ160, TQ144, TQ176
Xilinx
Original
XC4000 XC3100A XC2000 XC2018 PC84 XILINX XC2000 xc3000 xact XC2000/XC3000

XC2064

Abstract: XC3030 XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A XC3064A , PC84 WC84 PG84 CQ100 PQ100 TQ100 VQ100 CB100 PG120 PP132 PG132 TQ144 PG144 PG156 PQ160
Xilinx
Original
PQ240 XC4005A xc3142a xc5204 XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L

XILINX XC2000

Abstract: XC2018 PC84 members, the XC2064 and XC2018. Even the larger XC2018 should fit in the smallest XC5200 device, the , . Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 XC3090 , Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB flip-flops , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84, PQ100, VQ100, Packages TQ144 , 8 mA Yes Yes Yes 7 XC5210 16,000 1,296 0 192 165,488 1,296 PC84, PQ100, VQ100
Xilinx
Original
xilinx XC3000 Architecture D24E 8*1 multiplexer with inverter xilinx schematic XC3000A XC3100 XC6200

XC2000

Abstract: XC2018 PC84 members, the XC2064 and XC2018. Even the larger XC2018 should fit in the smallest XC5200 device, the , . Table 2: Density Comparison XC2000/ XC3000 XC2064 XC2018 XC3020 XC3030 XC3042 XC3064 XC3090 , Between XC5202, XC5206, XC5210 and XC3195, XC2018 Resource Max Logic Gates Maximum CLB flip-flops , Boundary-scan Internal oscillator Configuration modes PC44, VQ64, PC84, PQ100, VQ100, Packages , PC84, PQ100, VQ100, PQ160, TQ144, TQ176, PG191, PQ208 PC84, PC84, PQ160, TQ144, TQ176
Xilinx
Original
XC2000 FPGAs VQ64 XILINX xc2018

XC2064

Abstract: XC2018 PC84 XC2064 XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A , CHART PC44 x PQ44 WC44 PD48 x VQ64 PC68 x WC68 PG68 x PC84 WC84 PG84 CQ100 PQ100 TQ100
Xilinx
Original
xc5210 PQ160 XC3120A XC3130A XC3164A XC3190A XC3195A CQ164

XC2064

Abstract: XC3030A 68 Ceramic PGA PG68 Plastic PLCC PC84 84 Ceramic PGA PG84 Plastic PQFP PQ100 Plastic TQFP TQ100 , XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L
-
OCR Scan
XC3190 X04008 PP175 Xilinx XC3090 xc3142 xact xc3090 Xilinx XC3090A XC2O10 XC2O10L XC3120 XC3130 XC3142 XC3164

VHDL code for generate sound

Abstract: XC3020A - PQ100 Packages Speed Grades XC2018 PC44, VQ64, PC68, PC84, PG84, TQ100 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84, VQ64, VQ100 -10 XC2064La VQ64, PC68 -10 XC3020a PC68, PC84, PG84, CB100, CQ100, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84, PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a PC84, PG84, CB100, CQ100, PQ100, TQ100, PG132, -50, -70, -100, -125 PP132 XC3064a b PC84, PG132, PP132, PQ160 -50
Xilinx
Original
XACT8000 VHDL code for generate sound XC3020A - PQ100 xilinx xact viewlogic interface user guide foundation field bus XC7336A XC2064A

CB100

Abstract: xilinx XC3000 Architecture . Component Availability Pins Type Code XC2064 XC2018 XC2064L XC2018L XC3020 XC3030 XC3042 XC3064 XC3090 , &8 Ceramic PGA PG68 Plastic PLCC PC84 84 Ceramic PGA PG84 Plastic PQFP PQ100 Plastic TQFP TQ100
-
OCR Scan
Xilinx XC3030A fpga programming XC2000 PG68 XC3000/3100
Abstract: XC2018 XC2064L XC2018L -5 0 -70 -100 BIB ' * c f~ "c PG68 1 (Cl) Cl 100 PLAST. PLCC CERAM. PGA PC84 PG84 TQ100 VQ100 C IM ~â' â' c MB 1 Cl -
OCR Scan
XC2000L XC2000L- XC2064-70PC44C MIL-STD-S83C

netcon

Abstract: XC7354 parameters, see The Programmable Logic Data Book. Device a Packages Speed Grades XC2018 PC44, PC68, PC84, PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84, VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84, PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84, PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84, PG84, PG132, PP132, PQ100
Xilinx
Original
netcon XC7354 XC5204PC84 XC5204-PC84 XC7000 DS-344

ORCAD BOOK

Abstract: OSC52 Grades XC2018 PC44, PC68, PC84, PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84, VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84, PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84, PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84, PG84, PG132, PP132, PQ100, TQ100 -50, -70, -100, -125 XC3064a b PC84, PG132, PP132, PQ160 -50
Xilinx
Original
ORCAD BOOK OSC52 orcad DS-35 VST386 XcxxX WIN32S

OSC52

Abstract: xilinx xc3000 . Device a Packages Speed Grades XC2018 PC44, PC68, PC84, PG84, TQ100, VQ64 -33, -50, -70, -100, -130 XC2064a PC44, PC68, PD48, PG68 -33, -50, -70, -100, -130 XC2018La PC84, VQ64, VQ100 -10 XC2064La PC68, VQ64 -10 XC3020a CB100, CQ100, PC68, PC84, PG84, PQ100 -50, -70, -100, -125 XC3030a PC44, PC68, PC84, PG84, PQ100, TQ100 -50, -70, -100, -125 XC3042a CB100, CQ100, PC84, PG84, PG132, PP132, PQ100, TQ100 -50, -70, -100, -125 XC3064a b PC84, PG132
Xilinx
Original
xilinx xc3000 XC4000A XC4000E XC4025 xact reference guide

XC2018 PC84

Abstract: DS401 families. Device XC2018 XC2064 XC2018L XC2064L XC3020 XC3030 XC3042 XC3064* XC3090* XC3020A , XC3142 XC3164* XC3190* XC3195* XC3120A June 1995 Packages PC44 PC44 PC84 PC68 CB100 PC44 CB100 PQ100 PC84 CB164 PQ208 CB100 PC44 VQ100 CB100 TQ144 PC84 CB164 TQ176 PC84 PC84 PC84 PC84 PC84 CB100 PC44 CB100 TQ100 PC84 CB164 PQ208 PC84 CB100 PC68 PC68 VQ64 VQ64 CQ100 PC68 CQ100 TQ100 PG132 CQ164 Speed Grades PC84 PD48 VQ100 PG84 PG68 TQ100 VQ64
Xilinx
Original
DS401 XC3042 pc84 CORE i3 INTERNAL ARCHITECTURE CORE i3 ARCHITECTURE xc4000 vhdl

XC2018

Abstract: XC2018 PC84 XC2064 5.0 V 600-1,000 64 58 12,038 XC2064L 3.3 V 600-1,000 64 58 12,038 XC2018 5.0 V 1,000-1,500 100 , center of the device. The XC2064 has 64 such blocks arranged in an 8-row by 8-column matrix. The XC2018 , numbers of data frames. For the XC2064, configuration requires 12,038 bits for each device. For the XC2018 , and the XC2018 uses 197. The configuration bit stream begins with preamble bits, a preamble code and , , initialization will require about 160 additional cycles of the internal sampling clock (197 for the XC2018) to
-
OCR Scan
XC3042A pinout xc206470pc44c x5397 XC7236A XC7272A XC7318 XC7336 XC7372 XC73108

XC2064

Abstract: xc2064-70pc44c XC2064 and XC2018 are the world's lowest cost FPGAs, and they remain the most economical solution for , XC2064 XC2064L XC2018 XC2018L ­ I/O functions ­ Digital logic functions ­ Interconnections · , . The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a combinatorial , , configuration requires 12,038 bits for each device. For the XC2018, the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The
Xilinx
Original
Matrix Crystal x5399 XC4002A XC2064-70-pc44c X3461 X6120

kb3940

Abstract: XC2064-70PC44C Field-Programmable: - I/O functions - Digital logic functions - Interconnections Device XC2064 XC2064L XC2018 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a , , configura tion requires 12,038 bits for each device. For the XC2018, the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The , , initialization will require about 160 additional cycles of the internal sampling clock (197 for the XC2018) to
-
OCR Scan
kb3940 XC201B MIL-STD-883C
Abstract: XC2018 XC2018L Vcc 5.0 3.3 5.0 3.3 V V V V Typ. Logic Capacity (gates) 6 0 0 -1 ,0 0 0 600 -1 ,0 0 0 1 , XC2064 has 64 such blocks arranged in an 8-row by 8-column matrix. The XC2018 has 100 logic blocks , cycles of the internal sampling clock (197 for the XC2018) to clear the internal memory before another , XC2018, the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 uses 197. The configuration bit stream begins with preamble bits, a preamble code -
OCR Scan
2064-70P
Abstract: K XC2064/XC2018 Logic Cellâ"¢Array Product Specification FEATURES â'¢ Fully , speed grades. Part Number XC2064 XC2018 Logic Capacity (gates) 1200 1800 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. logic block inputs and the , . Typical global clock buffer power is about 3 mW / MHz for the XC2064 and 4 mW / MHz for the XC2018. With , ,038 bits for each device. For the XC2018, the configuration of each device requires 17,878 bits. The -
OCR Scan
XC2064/XC2018 XC2064/2018

306E-09

Abstract: MQFP-208 : Actual Temperature: Actual Voltage: Assumed Activation Energy: XC2018 Period: Combined Started , : Si Gate CMOS XC2000 Microcircuit Group PLCC-44 & 84 T = 85C, R.H. = 85% 5.0V +/- .25V XC2018 , XC2000 Microcircuit Group PLCC- 84 T = 121C; 2 atm. sat. steam. XC2018 Period: XC2000 July , XC2000 Microcircuit Group PLCC- 84 T = -65C/+150C (Air to Air) XC2018 Period: XC2000 July 1 , : XC1736D, XC2018, XC3020, XC3030, XC3042, XC3190, XC4005E, XC4005, XC4010, XC4010E XC5210, XC7336, &
Xilinx
Original
XC1700D MQFP-208 306E-09 XC4005E PHYSICAL HT 208 145C XC3000/A XC3100/A PQ120 PQFP-100
Abstract: '¢ Performance equivalent to TTL SSI/MSI Device Vcc XC2064 XC2064L XC2018 XC2018L 5.0 3.3 5.0 , -column matrix. The XC2018 has 100 logic blocks arranged in a 10 by 10 matrix. Each logic block has a , the XC2064, configura­ tion requires 12,038 bits for each device. For the XC2018, the configuration of each device requires 17,878 bits. The XC2064 uses 160 configuration data frames and the XC2018 , sampling clock (197 for the XC2018) to clear the internal memory before another configuration may begin -
OCR Scan
Showing first 20 results.