NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: PRELIMINARY 80296SA 80296SA COMMERCIAL CHMOS 16-BIT 16-BIT MICROCONTROLLER s 50 MHz Operation s Chip-select Unit - 6 Chip-select Pins s 6 Mbytes of Linear Address Space - Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select s 512 Bytes of Register RAM s 2 Kbytes of Code/Data RAM s Register-register Architecture s Footprint and Functionally Compatible Upgrade for the 8XC196NP 8XC196NP and 80C196NU 80C196NU s Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier ... | Original |
40 pages, |
AD10 8XC196NP 80C296SA 80C196NU 80296SA A3155 16 bit MCS-96 microcontroller 16-BIT 80296SA abstract |
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| Abstract: ADVANCE INFORMATION 80296SA 80296SA COMMERCIAL CHMOS 16-BIT 16-BIT MICROCONTROLLER s 50 MHz Operation s Chip-select Unit - 6 Chip-select Pins s 6 Mbytes of Linear Address Space - Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select s 512 Bytes of Register RAM s 2 Kbytes of Code/Data RAM s Register-register Architecture - Programmable Wait States (015) for Each Chip Select s Footprint and Functionally Compatible Upgrade for the 8XC196NP 8XC196NP and 80C196NU 80C196NU - Pr ... | Original |
40 pages, |
AD10 8XC196NP 80C296SA 80c296 80C196NU 80296SA A3155 16-BIT 80296SA abstract |
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| Abstract: PRELIMINARY 80296SA 80296SA COMMERCIAL CHMOS 16-BIT 16-BIT MICROCONTROLLER s 50 MHz Operation s 6 Mbytes of Linear Address Space s 512 Bytes of Register RAM s 2 Kbytes of Code/Data RAM s Register-register Architecture s Footprint and Functionally Compatible Upgrade for the 8XC196NP 8XC196NP and 80C196NU 80C196NU s Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier s 32 I/O Port Pins s 19 Interrupt Sources, 14 with Programmable Priorities s 4 External Interrupt Pins and NMI Pin s 2 Flexible 16-bit Time ... | Original |
40 pages, |
16 bit MCS-96 microcontroller 80296SA 16-BIT 8XC196NP 80C196NU 80296SA abstract |
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| Abstract: 83C196EA 83C196EA CHMOS 16-Bit Microcontroller Datasheet - Automotive Advance Information Product Features s s s s s s s s s s s s s s s s 40 MHz operation Optional clock doubler 2 Mbytes of linear address space 1 Kbyte of register RAM 3 Kbytes of code RAM 8 Kbytes of ROM Register-to-register architecture Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits 2 peripheral interrupt handlers (PIH) provide direct hardware ... | Original |
40 pages, |
AD11 AD10 83C196EA 83C196EA abstract |
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| Abstract: 0000h X001h 000Xh 0000h 0101h 0000h 8000h 0000h 8808h 8808h 8808h 8808h ... | Original |
28 pages, |
VBH48A SR14 SR13 SR12 PC99 LM4550 LM4549AVH LM4549A LM4549A abstract |
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| Abstract: 0 D0 4349h 4E53h 0000h 0000h 0000h BB80h BB80h 0000h X001h 000Xh ... | Original |
28 pages, |
VBH48A SR14 SR13 SR12 PC99 LM4550 LM4549AVH LM4549A LM4549A abstract |
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| Abstract: 4E53h 0000h 0000h 0000h BB80h BB80h 0000h X001h 000Xh 0000h 0101h 0000h ... | Original |
27 pages, |
VBH48A SR15 SR14 SR13 PC99 LM4550 LM4546BVH LM4546B LM4546B abstract |
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| Abstract: ADVANCE INFORMATION 80C196EA/83C196EA 80C196EA/83C196EA CHMOS 16-BIT 16-BIT MICROCONTROLLER Automotive s 40 MHz operation s Optional clock doubler s Serial debug unit provides read and write access to code RAM with no CPU overhead s 2 Mbytes of linear address space s Chip-select unit (CSU) s 1 Kbyte of register RAM s 3 chip-select pins s 3 Kbytes of code RAM s Dynamic demultiplexed/multiplexed address/data bus for each chip-select s 8 Kbytes of ROM s Register-to-register architecture ... | Original |
46 pages, |
AD10 80C196EA/83C196EA 16-BIT 80C196EA/83C196EA abstract |
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| Abstract: 83C196EA 83C196EA CHMOS 16-BIT 16-BIT MICROCONTROLLER Automotive s 32 MHz operation s Optional clock doubler s Serial debug unit provides read and write access to code RAM with no CPU overhead s 2 Mbytes of linear address space s Chip-select unit (CSU) s 1 Kbyte of register RAM s 3 chip-select pins s 3 Kbytes of code RAM s Dynamic demultiplexed/multiplexed address/data bus for each chip-select s 8 Kbytes of ROM s Register-to-register architecture s Programmable wait states ( ... | Original |
38 pages, |
AD10 83C196EA 16-BIT 83C196EA abstract |
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| Abstract: ADVANCE INFORMATION 83C196EA 83C196EA CHMOS 16-BIT 16-BIT MICROCONTROLLER Automotive s 40 MHz operation s Optional clock doubler s Serial debug unit provides read and write access to code RAM with no CPU overhead s 2 Mbytes of linear address space s Chip-select unit (CSU) s 1 Kbyte of register RAM s 3 chip-select pins s 3 Kbytes of code RAM s Dynamic demultiplexed/multiplexed address/data bus for each chip-select s 8 Kbytes of ROM s Register-to-register architecture s Prog ... | Original |
46 pages, |
AD10 83C196EA 16-BIT 83C196EA abstract |
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| Abstract: WAFER, HOUSING & TERMINAL PITCH: 4.00x4.00mm 4.00 mm WAFER - MCx 001 RIGHT ANGLE TYPE - Pa SPECIFICATIONS VOLTAGE RATING: 600V AC/DC CURRENT RATING: 1A AC/DC WITHSTAND VOLTAGE: 1800V AC/MINUTE INSULATOR RESISTANCE: 1000M 1000M OHM MIN. TEMPERATURE RANGE: -25º C ~ +85º C CONTACT RESISTANCE: 20m OHM MAX. MATERIALS BASE: NYLON 6T, UL 94V-0 CONTACT: BRASS, TIN PLATED SOLDER TABS: BRASS, TIN PLATED MC x WAFER SERIES 001 SERIES NO. Pa XX T X PCB TYPE CONT ... | Original |
3 pages, |
1000M 1000M abstract |
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| Abstract: fast mode. This is because the DAC has received the value X001H (X = don't care) which interprets to ... | Original |
11 pages, |
XDS510 TMS320C3X TMS320C31 TLV5619 SPRU163 XDS510 cable TLV5639 SLAU071 SLAU071 abstract |
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| Abstract: ad1286 Min Serial Port Clock period (BRR x002H) (BRR = x001H) (Note 1) TXLXL Units Max , register value for transmissions is x001H. TXLXL TXD TXHQV TXLXH RXD (Out) 0 1 2 ... | Original |
34 pages, |
MARK AD9 AD11 AD10 8XL196NP 83L196NP 80L196NP 16-BIT 8XL196NP abstract |
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| Abstract: ad1286 (SP_BAUD x002H) (SP_BAUD = x001H) (Note 1) Units Max 6TXTAL1 4TXTAL1 ns ns TQVXH , transmit is x001H. TXLXL TXD TXHQV TXLXH RXD (Out) 0 1 2 Valid 4 3 TDVXH ... | Original |
33 pages, |
P648 MARK AD9 a3080 8XC196NP 83C196NP 80C196NP 272459 16-BIT 8XC196NP abstract |
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| Abstract: x001H) (Note 1) Output data setup to clock high Output data hold after clock high Next output data valid , transmissions is x001H. TXLXL TXD TXLXH TXHQV TXHQX 2 3 4 5 6 TQVXH TXHQZ 7 RXD (Out) 0 ... | Original |
34 pages, |
A3256 8XL196NP 16-BIT 80L196NP 83L196NP 8XL196NP abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| (BRR = x001H) (Note2)" Port Clock Period Falling Edge to Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",480,"Serial Port Clock Period (BRR clock." NOTE2,"The minimum baud-rate register value for transmit is x001H." NOTE3,"The minimum www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| (BRR = x001H) (Note2)" Port Clock Period Falling Edge to Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",240,"Serial Port Clock Period (BRR clock." NOTE2,"The minimum baud-rate register value for transmit is x001H." NOTE3,"The minimum www.datasheetarchive.com/download/37837815-173476ZC/196.zip (2.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| = x001H) (Note2)" Port Clock Period Falling Edge to Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",120,"Serial Port Clock Period (BRR ." NOTE2,"The minimum baud-rate register value for transmit is x001H." NOTE3,"The minimum baud www.datasheetarchive.com/download/37837815-173476ZC/196.zip (4.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(T*4),]",160,"Serial Port Clock Period (BRR = x001H) (Note Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",240,"Serial Port Clock Period (BRR => x002H) (Note3 minimum baud-rate register value for transmit is x001H." NOTE3,"The minimum baud-rate register value www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(tOSC*4),]",160,"Serial Port Clock Period (BRR = x001H to Rising Edge (BRR = x001H)" tSPCP2,"[max(tOSC*6),]",240,"Serial Port Clock Period (BRR => x002H guarantee recognition at next clock." NOTE2,"The minimum baud-rate register value for transmit is x001H www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TLK) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(T*4),]",80,"Serial Port Clock Period (BRR = x001H) (Note2 Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",120,"Serial Port Clock Period (BRR => x002H) (Note3)" t transmit is x001H." NOTE3,"The minimum baud-rate register value for receive is x002H." NOTE4,"This www.datasheetarchive.com/download/37837815-173476ZC/196.zip (2.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| = x001H) (Note2)" Port Clock Period Falling Edge to Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",60,"Serial Port Clock Period (BRR => x next clock." NOTE2,"The minimum baud-rate register value for transmit is x001H." NOTE3,"The www.datasheetarchive.com/download/37837815-173476ZC/196.zip (4.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(T*4),]",40,"Serial Port Clock Period (BRR = x001H) (Note2 Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",60,"Serial Port Clock Period (BRR => x002H) (Note3)" t transmit is x001H." NOTE3,"The minimum baud-rate register value for receive is x002H." NOTE4,"This www.datasheetarchive.com/download/37837815-173476ZC/196.zip (4.TLK) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(T*4),]",100,"Serial Port Clock Period (BRR = x001H) (Note Rising Edge (BRR = x001H)" tSPCP2,"[max(T*6),]",150,"Serial Port Clock Period (BRR => x002H) (Note3 clock." NOTE2,"The minimum baud-rate register value for transmit is x001H." NOTE3,"The minimum www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| PORT, SHIFT REGISTER MODE" tSPCP1,"[max(tOSC*4),]",100,"Serial Port Clock Period (BRR = x001H to Rising Edge (BRR = x001H)" tSPCP2,"[max(tOSC*6),]",150,"Serial Port Clock Period (BRR => x002H is x001H." NOTE3,"The minimum baud-rate register value for receive is x002H." NOTE4,"This www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TLK) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |