NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| Virtex-4 | Xilinx, Inc. | DC and Switching Characteristics |
44 pages, |
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| VIRTEX-4 | Xilinx, Inc. | Tri-Mode Embedded Ethernet MAC Wrapper v4.4 |
9 pages, |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Virtex-4 FX12 Mini-Module The Memec Virtex-4 FX12 Mini-Module Development Kit provides a low , PowerPC Processor Based on the Virtex-4 FX12 FPGA 10/100/1000 Ethernet Port DDR and Flash Memory 76 , General Purpose Development The Memec Virtex-4 FX12 Mini-Module is the ultimate programmable system. , Architects, FPGA designers, and board designers will find the flexibility of Virtex-4 FX12 Mini-Module , solutions, while the configurable I/O settings offer versatile interface options. The Virtex-4 FX12 ... | Original |
2 pages, |
DS-KIT-FX12MM1-BASE DS-KIT-FX12MM1-BASE-EURO vhdl code for rs232 interface lcd module verilog xilinx vhdl rs232 code xilinx USB cable LCD module in VHDL virtex memec Virtex-4 DS-KIT-FX12MM1 networking SOCKET CONNECTION DIAGRAM virtex-4 fx12 RS232 RS232 abstract |
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| Abstract: Avnet Product Brief Xilinx® Virtex-4TM LX Evaluation Kit Features: FPGA - Xilinx XC4VLX25-FF668 XC4VLX25-FF668 or XC4VLX60-FF668 XC4VLX60-FF668 Virtex-4 FPGA I/O Peripherals - 128x64 OSRAM graphical display - AvBus , - Micron 32 MB DDR SDRAM - 8 MB FLASH - Xilinx platform FLASH Communication Xilinx Virtex-4 LX Evaluation Kit - RS-232 RS-232 serial port The Xilinx Virtex-4 LX Evaluation Kit provides a , platform to develop and test designs targeted to the revolutionary Xilinx Virtex-4 Platform FPGA family. ... | Original |
2 pages, |
,national semiconductor Linear ADS-XLX-V4LX-EVL25 CY7C68013 xilinx jtag cable DP83847 LM2704 LP2995M PT5401A ethernet xilinx vhdl vhdl code for lcd display VHDL code of lcd display Xilinx lcd display controller design XC4VLX60-FF668 XC4VLX25-FF668 XC4VLX60-FF668 XC4VLX25-FF668 abstract |
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| Abstract: Virtex-4 FX LC Development Kit The perfect solution for FPGA and system designers who need a low cost, flexible prototype platform. The Memec Virtex-4 FX LC Development Kit is the ideal solution for investigating the embedded PowerPCTM and tri-mode Ethernet MAC included in the Xilinx Virtex-4 , from Xilinx. The FX LC kit bundles a full- Features featured, expandable Virtex-4 FX based system , The Virtex-4 FX LC board is based on the 4VFX12 4VFX12 RS-232 RS-232 Interface FPGA, with a PowerPC 405 core ... | Original |
2 pages, |
4VFX12 LC SYSTEM BOARD mg027 P160 p160 cpu Xilinx Ethernet development DS-KIT-4VFX12LC-EDK-EURO xilinx vhdl rs232 code virtex-4 lc ds-kit-4vfx12lc The Virtex-4 LC system board virtex memec Virtex-4 4VFX12 abstract |
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| Abstract: 0 Virtex-4 GT11 Transceiver Wizard v1.5 DS138 DS138 August 15, 2007 0 Product Specification , serial interface with your custom function. Core Specifics Supported Device Family1 Virtex-4 FX , Instantiation Template · Creates customized HDL wrappers to configure Virtex-4 RocketIO GT11 transceivers Verilog and VHDL Verilog or VHDL Wrapper Additional Items · Users can configure Virtex-4 GT11 , for custom protocols UG076 UG076: Documentation Virtex-4 RocketIO Multi-Gigabit Transceiver User ... | Original |
3 pages, |
wizard GT11 ROCKETIO DS112 Virtex-4 verilog code for fibre channel GPON block diagram UCF virtex4 UCF virtex-4 UG076 virtex ucf file 6 DS138 DS138 abstract |
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| Abstract: Virtex-4 Development Boards & Kits Part Number Product Name Short Description Vendor ADPe-XRC-4 Virtex-4 FX PCI Express Card Virtex-4 FX100/FX140 FX100/FX140 based 8 lane PCI Express card with 1GByte SDRAM and 8MB SRAM. Wide range of I/O modules. Alpha Data ADM-XRC-4FX Virtex-4 PMC/PMC-X Card Virtex-4 FX100/FX140 FX100/FX140 based PMC/PMC-X card with 1GByte SDRAM. Wide range of I/O modules and adapters. Alpha Data ADM-XRC-4LS Virtex-4 LX and SX PMC Board Virtex-4 PMC board with LX160 LX160, 24MB ZBT ... | Original |
3 pages, |
HW-AFX-SP3-1500-DB virtex 5 sx50t LX-300 AES-S6EV-LX16-G ADS-XLX-V4LX-EVL25-G AES-XLX-V5LXT-PCIE50-G MXS3FK-PQ208-001-IM VIRTEX-5 DDR2 controller AES-XLX-V5SXT-PCIE50-G Virtex-5 LX50T virtex 5 fpga based image processing SPARTAN-3 XC3S400 PQ208 AES-XLX-V4FX-PCIE100-G AES-XLX-V5LX-EVL50-G AES-XLX-V5LX-EVL110-G AES-XLX-V5LX-EVL50-G abstract |
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| Abstract: Virtex-4 FPGA RocketIO GT11 Transceiver Wizard v1.6 DS138 DS138 May 16, 2008 Product Specification , ) Virtex-4 FX Provided with Core Documentation Product Specification Getting Started Guide Design , Requirements Features · Creates customized HDL wrappers to configure Virtex-4 FPGA RocketIO GT11 transceivers · Users can configure Virtex-4 FGPA GT11 transceivers to conform to industry standard protocols , Xilinx, Inc. at http://www.xilinx.com/support 1. For more information on the Virtex-4 devices, see ... | Original |
4 pages, |
Virtex-4 datasheet GT11 DS112 UG076 UG246 virtex 4 date code virtex ucf file 6 GPON block diagram fgpa ROCKETIO UCF virtex-4 DS138 DS138 abstract |
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| Abstract: White Paper Stratix II vs. Virtex-4 Performance Comparison Altera® Stratix® II devices use a , performance advantage for Stratix II devices (-3 speed grade, fastest) versus Virtex-4 devices (-12 speed , -3 (fastest) Synplify Pro version 8.0 Quartus II software version 5.0 Xilinx Virtex-4 -12 , Virtex-4, proving them to be the fastest FPGAs in the 90-nm process node. The Stratix II devices' , advantage. See Figure 1. September 2006, ver. 2.0 WP-S2052505-2 WP-S2052505-2.0 1 Stratix II vs. Virtex-4 ... | Original |
12 pages, |
barrel shifter with flip flop barrel shifter 16-bit adder code using xilinx code datasheet abstract |
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| Abstract: , Virtex-II ProTM and Virtex-4 FPGAs and CoolRunnerTM-II CPLDs. The PicoBlaze solution delivers: The , performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-4 TM FPGA and , ,Virtex-II/Pro and Virtex-4 PicoBlaze Performance and Features Comparison (KCPSM3). Feature PicoBlaze for Spartan-3/E, Virtex-II/Pro and Virtex-4 PicoBlaze for Virtex-E and Spartan-II/E , MIPS (Virtex-II Pro) 100 MIPS (Virtex-4 LX, SX) 102 MIPS (Virtex-4 FX) 37 MIPS (Spartan-IIE) 21 ... | Original |
2 pages, |
xilinx XC3S200 vhdl code for alu 18f pic controller datasheet 8 bit alu instruction in vhdl 18f pic controller xilinx vhdl code vhdl code PN code generator vhdl code for 4 bit ram spartan kcpsm3 vhdl code for 8 bit ram vhdl code for 8 bit alu vhdl code mips code datasheet abstract |
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| Abstract: R Radiation-Tolerant Virtex-4 QPro-V Family Overview DS653 DS653 (v1.2) December 16, 2008 , Virtex-4 QPro-V FPGAs provide unprecedented integration with Advanced Silicon Modular Block (ASMBLTM , solution and tri-mode Ethernet MACs all in a single device. Radiation-Tolerant Virtex-4 QPro-V FPGAs are a , · FX  optimized for signal processing Radiation-Tolerant Virtex-4 QPro-V FPGAs are based on commercial Virtex-4 technology, providing enhancements to the popular Virtex and Virtex-II families - ... | Original |
7 pages, |
PPC405 SRL16 UG070 UG073 powerpc 405 XC4VLX200 dsp radiation tolerant CF1509 CF1140 Radiation Tolerant DSP IBM powerpc 405 virtex 2 CF1144 "radiation tolerant" ethernet phy XQR4VFX140 DS653 DS653 abstract |
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| Abstract: handled more efficiently in hardware. The Virtex-II Pro and Virtex-4 FX FPGAs meet these requirements , embedded PowerPC processor in the Virtex-II Pro and Virtex-4 FX FPGAs. This minimal footprint embedded , on the PowerPC 405 processor core in the Virtex-II Pro and Virtex-4 FX FPGAs. With exciting new , software while leveraging the embedded PowerPC core in the Virtex-II Pro and Virtex-4 FX FPGAs, using the , frequency (up to 400 MHz in Virtex-II Pro and 450 MHz in Virtex-4 FX FPGA) which far exceeds any soft core ... | Original |
2 pages, |
XAPP672 XAPP575 PPC405 Virtex4 uart datasheet abstract |
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| Abstract: White Paper Stratix II vs. Virtex-4 Density Comparison Introduction Altera® Stratix® II , of this new architecture as compared to the Xilinx Virtex-4 product family. This measurement is based on Xilinx's -12 speed grade Virtex-4 devices versus Altera's production -3 speed grade Stratix II , Stratix II devices compared to Virtex-4 devices. The primary difference between the capacity and performance benchmarks is that the maximum performance for both Stratix II and Virtex-4 devices is ... | Original |
19 pages, |
XC4VLX160 XC4VLX100 Virtex-4 XC4VLX60 datasheet virtex 4 vs spartan 3e 32 bit carry select adder code Virtex-4 datasheet full adder bcd circuit diagram of half adder vhdl code for crossbar switch bcd subtractor VIRTEX-4 vhdl for 8-bit BCD adder datasheet abstract |
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| Abstract: ` 0 R Virtex-4 Family Overview DS112 DS112 (v3.1) August 30, 2010 0 0 Product , logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise , all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC , basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E , compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch ... | Original |
9 pages, |
PPC405 SFG363 virtex 4 virtex 4 date code virtex 5 ddr data path Virtex-4 datasheet Virtex-4 SF363 XC4VLX100 XC4VLX15 XC4VSX35 XC4VLX80 XC4VLX60 XC4VLX40 XC4VLX25 datasheet abstract |
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| Abstract: ` 0 R Virtex-4 Family Overview DS112 DS112 (v3.0) September 28, 2007 0 0 Product , logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise , all complex applications. The wide array of Virtex-4 hard-IP core blocks includes the PowerPCTM , basic Virtex-4 building blocks are enhancements of those found in the popular Virtex, Virtex-E , compatible. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process using 300-mm (12-inch ... | Original |
9 pages, |
XC4VLX80 DSP48 FF1513 FFG676 PPC405 sf363 VIRTEX-4 Virtex-4 SF363 XC4VLX100 XC4VLX15 XC4VLX160 XC4VLX200 XC4VLX25 XC4VLX40 XC4VLX60 datasheet abstract |
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| Abstract: Virtex-4 User Guide 0 R Virtex-4 Family Overview DS112 DS112 (v1.1) September 10, 2004 0 , architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families (platforms , source-synchronous interface blocks. The basic Virtex-4 building blocks are an enhancement of those found in the , , allowing upward compatibility of existing designs. Virtex-4 devices are produced on a state-of-the-art , features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative ... | Original |
10 pages, |
Virtex Analog to Digital Converter Virtex-4 SF363 Virtex-4 XC4VLX60 XC4VLX100 XC4VLX15 xc4vsx55 XC4VLX160 XC4VLX200 XC4VLX80 XC4VLX60 XC4VLX25 XC4VLX40 Virtex 4 XC4VFX60 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| virtex4 DEVFAMTIME 0 DEVICE xc4vlx25 DEVICETIME 1090110286 DEVPKG ff668 DEVPKGTIME 1083708897 _main_top.ucf [Normal] p_MapEffortLevel=xstvlg, virtex4, Implementation.t_placeAndRouteDes, 1095009140, High p_SimUseCustom_behav=xstvlg, virtex4, Test Fixture.t_MSimulateBehavioralVerilogModel, 1080171063, True p_xstCoresSearchDir=xstvlg, virtex4, Schematic.t_synthesize, 1093798707, core_fifos xilxBitgStart_Clk=xstvlg, virtex4, Implementation.t_bitFile, 1058806214, JTAG Clock xilxMapCoverMode=xstvlg, virtex4, Implementation www.datasheetarchive.com/download/49538481-996041ZC/xapp710.zip (V4_RL2_rev1_0.npl) |
Xilinx | 13/09/2004 | 102.73 Kb | ZIP | xapp710.zip |
| _0 DEVFAM virtex4 DEVFAMTIME 0 DEVICE xc4vlx25 DEVICETIME 0 DEVPKG ff668 DEVPKGTIME 0 DEVSPEED -10 ] p_ModelSimSimRunTime_tb=xstvlg, virtex4, Test Fixture.t_MSimulateBehavioralVerilogModel, 1090460538, 10000ns p_SimUseCustom_behav=xstvlg, virtex4, Test Fixture.t_MSimulateBehavioralVerilogModel, 1080171063, True xilxBitgStart_Clk=xstvlg, virtex4, Verilog.t_bitFile, 1093363077, JTAG Clock xilxMapTrimUnconnSig=xstvlg, virtex4, Verilog.t_placeAndRouteDes, 1089236520, False xilxNgdbldUnexpBlks=xstvlg, virtex4, Verilog www.datasheetarchive.com/download/99847513-996038ZC/xapp703.zip (V4_QDR2_rev1_0.npl) |
Xilinx | 10/09/2004 | 91.46 Kb | ZIP | xapp703.zip |
| networking around the most exciting new programmable technology in the world: the Virtex-4™ solution from . At Programmable World 2004, Xilinx and its partners will showcase the new Virtex-4™ solution in performance acceleration that Virtex-4 solutions will bring to your video and digital communications showcase the new Virtex-4™ solution in each of four digital Â"domainsÂ" Â- DSP, processor, connectivity, and reductions, power improvements, and performance acceleration that Virtex-4 solutions will bring to your www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_50/xc_pw04-50.htm |
Xilinx | 19/07/2004 | 16.82 Kb | HTM | xc_pw04-50.htm |
| Format = BusFormatParenNotRipped SET SimulationOutputProducts = Verilog SET XilinxFamily = Virtex4 SET Verification = None SELECT Synchronous_FIFO Virtex4 Xilinx,_Inc. 5.0 CSET data_width = 36 CSET read www.datasheetarchive.com/download/49538481-996041ZC/xapp710.zip (rld_rdfifo.xco) |
Xilinx | 13/09/2004 | 102.73 Kb | ZIP | xapp710.zip |
| Format = BusFormatParenNotRipped SET SimulationOutputProducts = Verilog SET XilinxFamily = Virtex4 SET Verification = None SELECT Asynchronous_FIFO Virtex4 Xilinx,_Inc. 6.0 CSET read_error_sense = active_high CSET read www.datasheetarchive.com/download/49538481-996041ZC/xapp710.zip (rld_wdfifo.xco) |
Xilinx | 13/09/2004 | 102.73 Kb | ZIP | xapp710.zip |
| ) in CLBs # SET BusFormat = BusFormatAngleBracketNotRipped SET XilinxFamily = Virtex4 SET Output Netlist ASYSymbol VHDLSim VerilogSim SELECT Distributed_Memory Virtex4 Xilinx,_Inc. 7.1 CSET single www.datasheetarchive.com/download/66975450-996095ZC/ug073_c05.zip (distmem1.xco) |
Xilinx | 07/09/2004 | 76.92 Kb | ZIP | ug073_c05.zip |
| BusFormat = BusFormatAngleBracketNotRipped SET XilinxFamily = Virtex4 SET OutputOption = Output Netlist ASYSymbol VHDLSim VerilogSim SELECT Distributed_Memory Virtex4 Xilinx,_Inc. 7.1 CSET single www.datasheetarchive.com/download/66975450-996095ZC/ug073_c05.zip (distmem2.xco) |
Xilinx | 07/09/2004 | 76.92 Kb | ZIP | ug073_c05.zip |
| BusFormat = BusFormatAngleBracketNotRipped SET XilinxFamily = Virtex4 SET OutputOption = Output Netlist ASYSymbol VHDLSim VerilogSim SELECT Distributed_Memory Virtex4 Xilinx,_Inc. 7.1 CSET single www.datasheetarchive.com/download/66975450-996095ZC/ug073_c05.zip (distmem3.xco) |
Xilinx | 07/09/2004 | 76.92 Kb | ZIP | ug073_c05.zip |
| ) in CLBs # SET BusFormat = BusFormatAngleBracketNotRipped SET XilinxFamily = Virtex4 SET Output Netlist ASYSymbol VHDLSim VerilogSim SELECT Distributed_Memory Virtex4 Xilinx,_Inc. 7.1 CSET single www.datasheetarchive.com/download/66975450-996095ZC/ug073_c05.zip (distmem4.xco) |
Xilinx | 07/09/2004 | 76.92 Kb | ZIP | ug073_c05.zip |
| demonstrate the Virtex-4 QDR II SRAM interface on a memory evaluation board. - top.v - test Resources" section of the Virtex-4 Users' Guide for more details on IDELAYCTRL usage. When integrating the Virtex-4 and QDR II memory device. This will demonstrate the designs ability to automatically adjust to www.datasheetarchive.com/download/99847513-996038ZC/xapp703.zip (readme.txt) |
Xilinx | 10/09/2004 | 91.46 Kb | ZIP | xapp703.zip |