NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Preliminary P521-48 P521-48 Low Phase Noise PECL VCXO (27MHz to 65MHz) FEATURES OSCOFF 15 , /02/04 Page 1 Preliminary P521-48 P521-48 Low Phase Noise PECL VCXO (27MHz to 65MHz) PAD ASSIGNMENT , Rev 3/02/04 Page 2 P521-48 P521-48 Preliminary Low Phase Noise PECL VCXO (27MHz to 65MHz , Preliminary P521-48 P521-48 Low Phase Noise PECL VCXO (27MHz to 65MHz) 4. General Electrical Specifications , Low Phase Noise PECL VCXO (27MHz to 65MHz) 7. PECL Electrical Characteristics PARAMETERS SYMBOL ... | Original |
6 pages, |
865 IC marking P521 vcxo P521-48 P521-48DC pecl logic voltage levels marking P521 IC P521 p521 VCXO 27MHZ p521 file P521-48 abstract |
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| Abstract: Preliminary P521-49 P521-49 Low Phase Noise LVDS VCXO (27MHz to 65MHz) FEATURES OSCOFF 15 , /02/04 Page 1 Preliminary P521-49 P521-49 Low Phase Noise LVDS VCXO (27MHz to 65MHz) PAD ASSIGNMENT , Rev 3/02/04 Page 2 P521-49 P521-49 Preliminary Low Phase Noise LVDS VCXO (27MHz to 65MHz , Preliminary P521-49 P521-49 Low Phase Noise LVDS VCXO (27MHz to 65MHz) 4. General Electrical Specifications , Low Phase Noise LVDS VCXO (27MHz to 65MHz) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL ... | Original |
6 pages, |
P521-49DC P521-49 VCXO 27MHZ P521 P521-49 abstract |
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| Abstract: Preliminary PLL502-26 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES · · · · · Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable , board space and cost. OUTPUT RANGE OUTPUT FREQUENCY RANGE OUTPUT TYPE VCXO Audio 27MHz , from other VDD. OUT_27MHz 14 O 27MHz VCXO output clock. GND_27MHz 15 P GND , ) 492-0991 Rev 09/26/03 Page 2 PLL502-26 PLL502-26 Preliminary High Pull-Range VCXO (27MHz) with ... | Original |
5 pages, |
VCXO 27MHZ Varicap PLL502-26SC-R PLL502-26SC PLL502-26 P502-26SC CRYSTAL 27MHZ 27mhz PLL502-26 abstract |
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| Abstract: PLL502-26 PLL502-26 High Pull-Range VCXO (27MHz) with integrated Audio PLL FEATURES · · · · · Low phase noise 27MHz VCXO (-135 dBc at 10kHz offset). Integrated variable capacitors. Wide pull range (+ , RANGE OUTPUT FREQUENCY RANGE VCXO Audio 27MHz 8.192MHz 12.288MHz OUTPUT TYPE CMOS , ) 492-0991 www.phaselink.com Rev 09/17/04 Page 1 PLL502-26 PLL502-26 High Pull-Range VCXO (27MHz) with integrated , should be decoupled separately from other VDD. OUT_27MHz 14 O 27MHz VCXO output clock. ... | Original |
5 pages, |
osc XTAL PLL502-26SC-R PLL502-26SC PLL502-26 P502-26SC OSC 27MHZ CRYSTAL RESONATOR 27mhz control 27mhz 27MHZ crystal CRYSTAL 27MHZ VCXO 27MHZ PLL502-26 abstract |
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| Abstract: 6 5 4 VCXO_27MHZ VCXO_27MHZ 9 SM_VCXO C86 47uF 3.3VA U2 3.3VA B B , CLK_REFSEL R31 20.0K VCXO_FR HREF_B VREF_B 6 1 29 VCXO_27MHZ 8 VCXO_27MHZ HREF_A , HD_CLKP HD_CLKN 20 19 HD_CLKP HD_CLKN R43 100 VC_FREERUN VCXO SD_CLKP SD_CLKN 24 ... | Original |
9 pages, |
VDD25-2 hsmc altera HDR2X1 SASF546-P26-X1 LTI-SASF546-P26-X1 datasheet abstract |
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| Abstract: device. BLOCK DIAGRAM VCXO Clock Recovery Channel Data Input Descrambler Channel , TBD IP FORMAT n Verilog HDL n GDS II TYPICAL SATELLITE IRD BLOCK DIAGRAM VCXO (27MHz) QPSK Demod Tuner I2 C Peripheral Interface DRAM DRAM Transport Decoder ... | Original |
2 pages, |
set top box dvb qpsk demod PID ic CRC32 block diagram of audio decoder basic microprocessor block diagram DVB T transport stream processor datasheet abstract |
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| Abstract: Preliminary PLL501-22 PLL501-22 27MHz Multiple Output VCXO with Audio Clock FEATURES · · 2 VCXO , pulled 27MHz signal of the VCXO. The wide pull-range makes it ideal for STB and MPEG Video , VCXO 27MHz 27MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/04 Page 1 Preliminary PLL501-22 PLL501-22 27MHz Multiple Output VCXO with Audio Clock , Ground. 27MHz 12 O S0 13 I VDD 14 P 27MHz VCXO output. Digital control ... | Original |
5 pages, |
VCXO 27MHZ PLL501-22 27mhz control 11.2896 CRYSTAL 27MHZ 27mhz PLL501-22 abstract |
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| Abstract: [] Fig.57 27MHz BUFFER Temperature Skew (BUF_OUT2 Phase Delay) Reference data (VCXO:27MHz output - , 200 100 -25 0 25 50 75 100 TemperatureT [] Fig.62 27MHz VCXO , VoltageVc [V] Fig.64 27MHz VCXO Control voltage Frequency data Reference data (BU2365FV BU2365FV consumption , /16 50 75 100 Fig.63 27MHz VCXO Temperature Central frequency fc 100 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 25 TemperatureT [] Reference data (VCXO : 27MHz output ... | Original |
17 pages, |
27MHz vco oscillator 18.432mhz 4 MHz crystal 3pin BU2365FV connector 15pin vco 27MHz SSOP-B24 NX5032GA Nihon Dempa Kogyo Nihon Dempa Kogyo Co., Ltd. VCXO 27MHZ exs00a BU2365FV abstract |
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| Abstract: MPEG-2 encoding Decoder clock Cypress VCXO 27MHz xx ppm Presentation Frequency PLL PLL , voltagecontrolled crystal oscillator (VCXO) functionality as it relates to the DTV system. This article addresses , diagram. The required clock outputs for the system are provided by the CY22388 CY22388 4-PLL VCXO clock generator. , encode the data, a VCXO is used in combination with the ASIC to match the output frequency to the reference source. An in-depth discussion of the use of a VCXO is presented in the section Using a VCXO in ... | Original |
19 pages, |
xport ethernet 54-054 CY22388 CY22389 CY24488 CY25100 PAL video RF MODULATION CARD TDA8004 TUNER ANALOG SAT TV 27MHz rf transmitter dtv schematic diagram receiver 8psk schematic diagram schematic multiplexer satellite modem schematic diagram lcd tv tuner box ANC0003 ANC0003 ANC0003 abstract |
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| Abstract: X32B NTSC/PAL Encoder TV Monitor PLLs C oprocessors DEMOD FEC 27MHz VCXO TCI Input 1 , generate all the internal clocks from a single 27MHz external 1 Hitachi, Ltd. MAP-CA2000 MAP-CA2000 Data , 27MHz that can be used to generate periodic interrupts. 1.3 INTERRUPTS AND EXCEPTIONS The ... | Original |
42 pages, |
TV Tuner phillips 21 PAL to ITU-R BT.601/656 Decoder ITU-R BT.656 to jpeg IEC958 ac3 decoder toslink MAP-CA2000TM MAP-CA2000 MAP-CA2000TM abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| _n, // 270MHz VCO neg clk input vcxo_27M_in, // 27MHz VCXO clock input used as ref osc only // (not VCXO) // SDI Port sdi_rxd_p, // SDI serial input bit stream sdi_rxd_n, // SDI serial " ; /////////////////////////////////////////////////////////////// // SDI 27MHz VCXO IBUF_LVDCI_25 VCXO27M (.I(vcxo_27M_in), .O(vcxo_27M); // synthesis attribute LOC of buffers for signals controlling the 27Mhz // VCXO //OBUF_LVDCI_33 VCXO27M_LPFEN (.O(vcxo_27M_sel), .I : // //- //Description of module: // // This module instances modules that through control of a VCO / VCXO will preform www.datasheetarchive.com/download/56962836-995945ZC/xapp250.zip (top_xapp250.v) |
Xilinx | 11/10/2003 | 13.1 Kb | ZIP | xapp250.zip |
| 14" ; NET "clk_74_17M_p" LOC = "B14" ; # # 74.1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo_up" LOC = "M6" ; # # 270MHz VCO loop filter control outputs # NET "sdi_vco_down" LOC = "M4" ; NET "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2" ; # # ICS660 ICS660 ICS660 ICS660 PLL control outputs # NET "ics660_s www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (sdv_multi_sdi_tx.ucf) |
Xilinx | 15/03/2004 | 67.57 Kb | ZIP | xapp683.zip |
| "clk_54M_p" LOC = "D14" ; # # 74.1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo_up" LOC = "M6" ; # # 270MHz VCO loop filter control outputs # NET "sdi_vco_down" LOC = "M4" ; NET "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2" ; # # ICS660 ICS660 ICS660 ICS660 PLL control outputs # NET "ics660_s" LOC = "A2 www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (sdv_sdsdi_rio_tx.ucf) |
Xilinx | 15/03/2004 | 67.57 Kb | ZIP | xapp683.zip |
| 14" ; NET "clk_74_17M_p" LOC = "B14" ; # # 74.1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo_up" LOC = "M6" ; # # 270MHz VCO loop filter control outputs # NET "sdi_vco_down" LOC = "M4" ; NET "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2" ; # # ICS660 ICS660 ICS660 ICS660 PLL control outputs # NET "ics660_s www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (sdv_multi_sdi_tx.ucf) |
Xilinx | 15/03/2004 | 67.57 Kb | ZIP | xapp683.zip |
| "clk_54M_p" LOC = "D14" ; # # 74.1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo_up" LOC = "M6" ; # # 270MHz VCO loop filter control outputs # NET "sdi_vco_down" LOC = "M4" ; NET "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2" ; # # ICS660 ICS660 ICS660 ICS660 PLL control outputs # NET "ics660_s" LOC = "A2 www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (sdv_sdsdi_rio_tx.ucf) |
Xilinx | 15/03/2004 | 67.57 Kb | ZIP | xapp683.zip |
| "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2 .1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo www.datasheetarchive.com/download/72452944-996024ZC/xapp680.zip (sdv_hdsdi_tx.ucf) |
Xilinx | 07/01/2004 | 92.02 Kb | ZIP | xapp680.zip |
| "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2 .1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo www.datasheetarchive.com/download/72452944-996024ZC/xapp680.zip (sdv_hdsdi_tx.ucf) |
Xilinx | 07/01/2004 | 92.02 Kb | ZIP | xapp680.zip |
| "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2 .1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (sdv_hdsdi_rx.ucf) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7" ; NET "vcxo_27M_up" LOC = "M2 .1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (sdv_hdsdi_rx.ucf) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| "ics660_clk_in" LOC = "G14" ; # # 74.1758MHz VCXO loop filter control outputs # NET "hdsdi_vcxo_down" LOC = "M5" ; NET "hdsdi_vcxo_up" LOC = "M6" ; # # 270MHz VCO loop filter control outputs # NET "sdi_vco_down" LOC = "M4" ; NET "sdi_vco_up" LOC = "M3" ; # # 27MHz VCXO loop filter control and control voltage select outputs # NET "vcxo_27M_down" LOC = "M1" ; NET "vcxo_27M_sel" LOC = "N7 processor only needs to run at 27 MHz since # it only runs in SD mode. # TIMESPEC "TS_RX_DEC_IN" = FROM www.datasheetarchive.com/download/58948463-996028ZC/xapp684.zip (sdv_multi_sdi_rx.ucf) |
Xilinx | 22/09/2004 | 2253.89 Kb | ZIP | xapp684.zip |