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LTM4609MPV#PBF Linear Technology LTM4609 - 36VIN, 34VOUT High Efficiency Buck-Boost DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 141; Temperature Range: -55°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTM8042IV-1#PBF Linear Technology LTM8042/LTM8042-1 - µModule (Power Module) Boost LED Driver and Current Source; Package: LGA; Pins: 77; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC4099EUDC#TRPBF Linear Technology LTC4099 - I<sup>2</sup>C Controlled USB Power Manager/Charger with Overvoltage Protection; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
REF01EH Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, MBCY8, METAL CAN, TO-5, 8 PIN, Voltage Reference visit Linear Technology - Now Part of Analog Devices
REF02CJ8 Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 5 V, CDIP8, 0.300 INCH, CERAMIC, DIP-8, Voltage Reference visit Linear Technology - Now Part of Analog Devices
LTC3620EDC#TRPBF Linear Technology LTC3620 - Ultralow Power 15mA Synchronous Step-Down Switching Regulator; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

Toggle flip flop IC

Catalog Datasheet MFG & Type PDF Document Tags

siemens master drive circuit diagram

Abstract: SR flip flop IC J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip , Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , , fanout=2) 150 MHz maximum toggle frequency Performance optimization with standard and high drive , Buffer Total Quantity 62 15 6 22 36 8 14 6 48 40 324 581 © Siem ens Components, Inc., A S IC Products
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toggle type flip flop ic

Abstract: Toggle flip flop IC flip -flop s w ith true and com plem ent outputs, designed fo r use in high-perform ance ECL system s , The resultant clo ck signal co n tro llin g the flip -flop is the logical OR operation of these tw o , ) and M aster R eset (MR) inputs. Each flip -flop also has its own D irect Set (S D n ) and D irect C , «o» S Y N ER G Y T RI P L E D H J P - F L û viüUb.i 3 i S E M IC O N D U C T O R F EA TU R E S Max. toggle frequency of 800MHz Differential outputs I ee min. of -8 0 m A Industry
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Abstract: , P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip -flop . The , pulses (see the Output State Diagram). INPUTS Clock (Pin 2) The internal flip -flo p s toggle and , The flip -flo p s shown in the circuit diagram s are T oggle-E nable flip -flop s. A T o g g le CLOCK LOAD Enable flip -flo p is a com bination of a D flip -flo p and a T flip -flop . When loading data , the flip -flop . The logic level at the Pn input is then clocked to the Q output of the flip -flo p -
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MC1034

Abstract: maxim 5678 J K flip flop in applications such as single-rail operation Since a true master slave design > s , ill override the clock, setting both the master and the slave portions of the flip flop A low fevel c , master and stave portions of the flip-flop are internally offset to give a "raceiess" flip flop (i.e , independent of the rise and fall times of the clock waveforms This single-phase T yp e D flip flop m ay be , ing the state o f the flip -flo p and sim p lifie s system application. W hen the c loc k is low , the
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Toggle flip flop IC

Abstract: flip flop 945 «IK Flip Flop The M C10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave , CLK L L H H X QN+1 L L H H X Z = Low to High Transition 1 K o o J 8 7 Flip Flop vcc , activated with a logic HIGH. · 300ps Propagation Delay · 3.5 G H z Toggle Frequency · High Bandwidth Output , :PHL : S H RR Characteristic Maximum Toggle Frequency3 Propagation Delay Setup Time Hold Time Reset
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Toggle flip flop IC flip flop 945 flip flop j k MC10EP35/D MC10EP35
Abstract: toggle flip flop (starts out low) 1 0 Borrow - high true 1 1 24-bit Comparitor/Counter match - high , triggered. Bit-2: Compare Toggle Flip Flop. Toggles every time the 24-bit counter equals the 24-bit Preset , -5 Bit-4 Pin 16 Function 0 0 Carry - low true 0 1 Carry toggle flip flop (starts out low) 1 0 , Control Register as follows: Bit-5 Bit-4 Pin Function 0 0 Carry - low true 0 1 Carry toggle flip , Register. They are insepa­ rably linked together. The toggle flip flops are triggered by the trailing -
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LS7166

PO74G112A

Abstract: T flip flop pin configuration PO74G112A www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET , NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Maximum Ratings , www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise , DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz , J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Packaging Mechanical
Potato Semiconductor
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T flip flop pin configuration JK flip flop IC diagram 750MH 5000-VH A114-A 200-VM A115-A PO74G112ASU

toggle type flip flop ic

Abstract: crc-16 implementation 10G024 10G024K Quad D Flip Flop with XOR Inputs 1.9 GHz Clock Rate 10G PicoLogicTM Family_ FEATURES , quad D-type flip flop with XOR gate or 2:1 MUX data inputs (D0A-D3A, D0B-D3B). When the DA and DB , , and is latched into the flip flop by the rising edge of either the Individual clock inputs (CLK0-CLK3 , each flip flop asynchronously to a low level. All device outputs can be disabled (brought low), without interfering with the current.state of the flip flop, via the output enable (OUTEN) control. This permits
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toggle type flip flop ic crc-16 implementation QQ00405 10G061 90GHS 050P3

RS flip flop IC

Abstract: JK flip flop IC accordance with the function table given. Use of SD and Rd permits direct R-S flip flop operation. When SD , simultaneously become high, the condition of Q and Q canncrt be predetermined. When used as a J-K flip flop, Sq , D-type flip flop. 2-66 This Material MITSUBISHI HIGH SPEED CMOS M74HC109P DUAL J-K FLIP-FLOP WITH , operation supply current under no-load conditions, (per flip flop) The power dissipated during operation , 74LS109. The M74HC109 contains two edge-triggered J-K flip flops, each circuit with Independent clock
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4000B RS flip flop IC JK flip flop IC RS flip flop cmos RS flip flop

Toggle flip flop IC

Abstract: 100el30 a triple m a ste r-sla ve D flip flop with differential outputs. The M C 100EL30 is pin and , provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. MC100LVEL30 MC100EL30 1 · 1200MHz M inim um Toggle Frequency · 2 0 , P LA S TIC S O IC P ACKA G E CASE 7 5 1 D -0 4 Logic Diagram and Pinout: 20-Lead SOIC (Top View , tpHL Characteristic Maximum Toggle Frequency Propagation Delay to Output Setup Time Hold Time Set/Reset
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100LVEL30 1200MH DL140

JK flip flop IC

Abstract: RS flip flop IC are inhibited. A jo in t (JK) input is provided fo r all flip -flop s in this fam ily. The com mon , provided on all flip -flop s except the 9020, which because of a logic trade-off has only clear inputs. The , . This operation is represented sym bolically by AND gates in the logic symbol for each flip -flop . , CHARACTERISTICS (Ta = 25°C, Vcc = 5.0 V, C l = Ci = 15 pF of all flip -flop s unless otherwise noted) SYMBOL Clock , aterial 5-4 9XXX Series FUNCTIONAL DESCRIPTION - The T T L 9000 series has fo u r flip -flo p s
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9022DC ic 9022 JK flipflop 9001 9022 9000DC 9020DC 9000FC 9001FC 9020FC
Abstract: aster-slave D-type flip -flop s w ith d iffe re n tia l outputs, designed for use in new, high-perform ance , operation before use as clocking control for the flip -flop s. Data is clocked into the flip-flops on the , . 1100MHz toggle frequency Extended 100E Vee range of -4.2V to -5.46V Differential outputs Asynchronous , transition u = LOW-to-HIGH transition D C E L E C T R I C A L C H A R A C T E R I S T IC S V e e = V e e , 65 - 5 5-71 S E M IC O N D U C TO R SYNERGY. SY10E151 SY100E151 s V ee = V ee -
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SY10/100E151 1100MH MC10E/100E151 J28-1 SY10E151JC SY10E151JCTR

ic CD40106

Abstract: cd40106 application notes FIGURE 3 Output status determines dynamic dissipation in this 3-state-output flip flop The IC , many outputs are toggling For example a 74HC374 octal 3state flip flop clocked at 1 MHz dissipates much , its inputs are tied High or Low during clocking Figure 3 shows that when the flip flop's outputs , outputs can toggle at a different rate from that of the IC's clock or input Thus for an individual IC and , the load toggle rate to the IC's toggle frequency CLE e (CL)(fL f) (7) Display drivers CPD is
National Semiconductor
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MM54HC AN-376 ic CD40106 cd40106 application notes ten segment display 74HC 74HCT IC family spec 74HC14 oscillator application diagram

function of latch ic 74373

Abstract: full adder using ic 74138 LDF J-K flip flop with reset _ J-K flip flop w ith set/reset Toggle flip flow with enable/reset Toggle flip flop with enable/set/reset Toggle flip flop with reset 2-input N A N D driver gate 2-input A , /reset and L S S D D-type latch Toggle flip flop with reset Toggle flip flop with set/reset 8 8 8 8 8 , 1-54 Flip flop 1-55 1-56 1-57 1-58 1-59 Others 1-60 1-61 1-62 Internai tri-state driver 1-63 1-64 1-65 , tristate bus driver-2 Internal tristate bus driver-3 Bus hold-1 D-type flip flop with reset and L S S D
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MSM70000 function of latch ic 74373 full adder using ic 74138 pins and their function in ic 74163 encoder IC 74147 74541 buffer 74373 cmos dual s-r latch MSM71000/72000/73000/74000 MSIW71000 MSM74000

74hc00 oscillator circuit

Abstract: cd40106 application notes . Figure 3 shows that when the flip flop's outputs are enabled and the data inputs are changing, virtually , Flip flops: The same as for latches. The device's inputs are configured to toggle, and any preset or , . AN008128-3 FIGURE 3. Output status determines dynamic dissipation in this 3-state-output flip flop. The , , these outputs can toggle at a different rate from that of the IC's clock or input. Thus, for an , load multiplied by the ratio of the load toggle rate to the IC's toggle frequency: CLE = (CL)(fL/f).
Fairchild Semiconductor
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74hc00 oscillator circuit CRYSTAL 20 MHZ with 74hc14 CD40106 CD40106 Family specifications CD40106 PIN OUT IC 74C14 MM54HC/74HC 54HC/74HC

100LVEL29

Abstract: 100el29 et and R eset The MC100LVEL29 is a dual m a ste r-sla ve flip flop. The device features fully , will go to a defined state, however the state will be random based on how the flip flop pow ers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note th a t the Set and Reset inputs cannot both be HIGH simultaneously. · 1100MHz F lip -F lo p Toggle Frequency · 2 0 -le a d SOIC , 751D -0 4 TR U TH TABLE Logic Diagram and Pinout: 20-Lead SO IC (Top View) RO Vcc QO QO SO S1 Vcc
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100LVEL29 100el29 Ox25C MC100EL29 100EL29

T flip flop IC

Abstract: JK flip flop IC HCTS109T Data Sheet July 1999 File Number Radiation Hardened Dual JK Flip Flop Features Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to , Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition , CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures , H H H L Toggle H H L H No Change H H H H H H X X
Intersil
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T flip flop IC transistor smd K2 T flip flop ic number smd transistor k2 T flip flop CMOS IC 5962R9576901TEC MIL-PRF-38535 HCTS109 TA14440A ISO9000

toggle type flip flop ic

Abstract: Radiation Hardened Dual JK Flip Flop H arris' Satellite Applications FlowTM (SAF) devices are fully tested , maintaining a high level of reliability. The Harris HCTS109T is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the clock (CP1 or CP2). , C O 02 1 C AUTION: These devices are sensitive to electrostatic discharge; follow proper IC , s L H L H H H H H R H L L H H H H H CP X X X Q H L Ht L Toggle No Change Q L H Ht H
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1-800-4-HARR

Toggle flip flop IC

Abstract: T flip flop IC HCTS109T TM Data Sheet July 1999 FN4624.1 Radiation Hardened Dual JK Flip Flop Features Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to , Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the , CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures , H H H L Toggle H H L H No Change H H H H H H X X
Intersil
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k2 smd transistor CDFP4-F16 T flip flop IC CMOS 13KA 5962R9576901TXC
Abstract: HCTS109T D ata S h eet Ju ly 1999 F ile N u m b er Radiation Hardened Dual JK Flip Flop Features Harrisâ'™ Satellite Applications Flowâ"¢ (SAF) devices are fully tested and guaranteed to , reliability. The Harris HCTS109T is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop , ¡ Q2 C AUTIO N : These devices are sensitive to electrostatic discharge; follow proper IC Handling , H H H L Toggle H H L H No Change H H H H H H X X -
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1-800-4-HARRIS
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