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BCV26_L99Z Fairchild Semiconductor Corporation PNP Darlington Transistor ri Buy
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TTL 74ls76

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Abstract: and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , are unpredictable if SD and RD go HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be , temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 7476 74LS76 UNIT Min Typ2 , waveforms, VM = 1,3V for 74S; VM = 1,5V for all other TTL families. The shaded areas indicate when the input ... OCR Scan
datasheet

6 pages,
139.61 Kb

J-K Flip-Flop 7476 TTL 7476 i c 74ls76 74ls76 PIN CONFIGURATION 7476 Jk 7476 LS 7476 7476 pin configuration ci 74ls76 TTL 74ls76 7476 J-K Flip-Flop 7476 ttl 7476 PIN DIAGRAM input and output 74LS76 7476 74LS76 pin diagram of ttl 7476 74LS76 jk flip flop 7476 74LS76 pin diagram of 7476 74LS76 7476 PIN DIAGRAM 74LS76 ci 7476 74LS76 74LS76 74LS76 TEXT
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Abstract: HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , are unpredictable if 3 D and R d go HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be , Min Typ2 3.4 0.2 0.4 Max Min 2.7 74LS76 UNIT Typ2 3.4 0.35 0.25 -1 .5 1.0 0.1 0.3 0.4 40 80 80 20 60 , l Vm For all waveforms, V m = 1.3V for 74S; VM = 1.5V for ail other TTL families. The shaded ... OCR Scan
datasheet

6 pages,
251.41 Kb

7476 7476 PIN DIAGRAM 7476 signetics 7476 ttl TTL 7476 7476 signetics TTL 7476 pin configuration 7476 logic diagram 7476 J-K Flip-Flop Jk 74ls76 pin out 7476 FUNCTION TABLE 7476 PIN DIAGRAM input and output 74LS76 PIN CONFIGURATION 7476 pin diagram of 7476 TEXT
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Abstract: HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , . 2. The 74LS76 is edge triggered. Data must be stable one set-up time prior to the negative edge of , temperature range unless otherwise noted.) 7476 C M a. ? 74LS76 UNIT Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 , waveforms, V m - 1.3V for 74S; Vm = 1.5V for all other TTL families. The shaded areas indicate when the ... OCR Scan
datasheet

6 pages,
145.77 Kb

Diagram of 7476 Pin Configuration of 7476 Jk 74ls76 pin out 7476 ttl 74LS76 logic diagram TTL 7476 Flip-Flop 7476 TTL 74ls76 7476 7476 J-K Flip-Flop J-K Flip-Flop 7476 74LS76 7476 PIN DIAGRAM input and output LS 7476 7476 pin configuration pin diagram of ttl 7476 7476 FUNCTION TABLE 7476 PIN DIAGRAM pin diagram of 7476 PIN CONFIGURATION 7476 TEXT
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Abstract: and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , LOW, but the output states are unpredictable if SD and BD go HIGH simultaneously. 2. The 74LS76 is , CONDITIONS1 7476 74LS76 UNIT Min Typ2 Max Min Typ2 Max HIGH-level 0H output voltage Vcc - MIN , TTL families The shaded areas Indicate when the input is permitted to change for predictable output ... OCR Scan
datasheet

6 pages,
146.88 Kb

ALL 74LS76 7476 master slave 74LS 7476 pin configuration Jk 7476 74LS76 ttl LS76 TTL 7476 J-K Flip-Flop 7476 74LS76 pin diagram of ttl 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 pin diagram of 7476 TTL 74ls76 7476 PIN DIAGRAM input and output 7476 ttl 7476 7476 PIN DIAGRAM jk flip flop 7476 TEXT
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Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 , /7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 14 — J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 — K Q Pins are , €” KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL , /74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 54LS/74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8 ... OCR Scan
datasheet

3 pages,
69.13 Kb

74LS114 74ls74 74LS76 logic diagram CI 74109 74ls76 D147 74LS76 FAIRCHILD 7473 latch 74LS109 7475 D latch 74ls107 ci 74LS74 fairchild 9024 TTL 74ls76 CI 74107 CI 74LS76 7474 D latch ci 7476 CI 7473 CI 7474 TEXT
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Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 — J SD 0 _6 14 0 4 — CP 12 CP 3-0 K Co Q »1 13 —0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd , /7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 14 — J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 — K Q Pins are ... OCR Scan
datasheet

1 pages,
24.26 Kb

TTL 74109 74S109 7476 master slave ttl 7474 14 PIN CD-D60 Fairchild 9020 Fairchild 902 7474 16 PIN 74LS109 TTL 74ls76 74ls74 74LS73 74LS107 ttl 74ls109 7476 ttl 74ls76 7474 14 PIN TTL 74ls74 TEXT
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Abstract: SANYO SEMICONDUCTOR CORP 12E »"J 7clci70?b OOOabbñ S LC74HG76M LC74HG76M 3035A CMOS High-Speed Standard Logic LC74HC LC74HC Series ©2186 Features Dual J-K Flip-Flop with Set and Reset The LC74HC76M LC74HC76M consists of 2 identical J-K type flip-flops. Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL (74LS76) with the low power dissipation and high noise margin of standard , /74LS /74LS TTL logic family. Absolute Maximum Ratings/Ta=25±2°C, Vss=OV Maximum Supply Voltage Maximum ... OCR Scan
datasheet

1 pages,
101.36 Kb

LC74HC76M LC74HC76 j-k flip flop 74ls76 74LS76 dual flip-flop 74ls series logic family 74ls76 74LS76 pinout TTL 74ls76 Jk 74ls76 pin out LC74HG76M TEXT
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Abstract: d604l Pin 7 13-50 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE NO , 54LS/74LS109 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 ... OCR Scan
datasheet

3 pages,
64.92 Kb

74279 74LS107 74ls112 pin diagram 74LS76 logic diagram ci 7475 ci 9024 Fairchild 902 7475 data latch 74LS109 fairchild 9314 74LS113 74LS112 CI 74196 74LS114 54H/74H78 d147 54H/74H78 74LS78 54H/74H78 7475 D latch 54H/74H78 RS latch 54H/74H78 d146 54H/74H78 54H/74H78 54H/74H78 TEXT
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Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 — J SD 0 _6 14 0 4 — CP 12 , /7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 14 — J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 — K Q Pins are , €” KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL ... OCR Scan
datasheet

2 pages,
66.76 Kb

7472 PIN DIAGRAM 7476 ttl 74LS73 JK Fairchild 9020 74LS74 TTL 7473 dual JK 74LS109 7476 PIN DIAGRAM 74LS73 dual JK 7474 16 PIN jk 7474 pin diagram 7474 7474 PIN DIAGRAM Jk 7476 ttl 7474 14 PIN TTL 7474 7476 JK CI 7473 74ls74 TTL 74ls74 TEXT
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Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D145 9370, 9374 DIGITAL -TTL 0146 9314, 93L14 93L14 D147 54/74279, 54LS/74LS279 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 15 14 1 3 2 4 14 6 5 7 11 mijum Vcc E Do So Di Si D2 S2 D3 S3 MR Qo Ql 02 O3 TT 15 13 12 10 , Pin 16 GND = Pin 8 13-62 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item , 5 Dual JK 54LS/74LS109 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 ... OCR Scan
datasheet

3 pages,
69.93 Kb

D145 74ls76 CI 74196 74L51 9374 74LS114 D146 74279 74LS279 74LS75 74109 pin diagram 7475 74LS78 fairchild 9314 rs latch 93L14 54LS/74LS279 TTL 7475 93L14 54LS/74LS279 74L576 93L14 54LS/74LS279 74LS109 93L14 54LS/74LS279 D147 93L14 54LS/74LS279 ci 7475 93L14 54LS/74LS279 93L14 93L14 54LS/74LS279 54LS/74LS279 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
Latch $ENDCMP # $CMP 74LS76 D Dual JK FlipFlop, Set & Reset K TTL JK JKFF $ENDCMP # $CMP 74LS77 74LS77 7400 D Quad nand2 K TTL nand2 $ENDCMP # $CMP 7402 D Quad Nor2 K TTL Nor2 $ENDCMP # $CMP K HCMOS SR 3State $ENDCMP # $CMP 74HC74 74HC74 D Dual D FlipFlop, Set & Reset K TTL DFF F 74xx nand2 K TTL nand2 $ENDCMP # $CMP 74LS01 74LS01 D Quad nand2 open collect. K TTL nand2 opencol $ENDCMP # $CMP 74LS02 74LS02 D Quad Nor2 K TTL Nor2 $ENDCMP # $CMP 74LS03 74LS03 D Quad Nand2 open collect K TTL Nand2
/datasheets/files/kaleidoscope/cad/kicad - kicad/library/74xx.dcm
Kaleidoscope 10/10/2004 11.88 Kb DCM 74xx.dcm
No abstract text available
/download/48664731-299145ZC/bae65022linux.tgz
Kaleidoscope 22/08/2005 11421.08 Kb TGZ bae65022linux.tgz