NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Nil2 0 27a 5156 LC74HC76 LC74HC76 D u a I J - K F l i P «FI o P With R e gfjá ìnIn D Set WMfz.a-'X Na2027 •LC74HC76 LC74HC76Ü J- 7 'J -y D-yT" I UXTÜV, LS • TTL (74LS76) •ÁfiíSREISa-sST»*. // • T TL ©4*4*5 4 LS/74LS LS/74LS n*J*> 9 V 5. T é = 2 5 ±2V, V sS=0V un « t VcCflftx V • S V VlNmax -0» - 5 V VOUTmai -JO^-^VCC+O-5 V I OUT ±25 mA ¡h*W« I CC/ I Gn// ±50 mA J It // ±20 mA Pómàf^/ 300 mW ttttMHfiK Tit.// -65^+150 x: •í-t-isjí^m Tjl/ t=10*ac 300 •c WWW/ Vss=0v // un 11 /Vcc .vi' .-,'• ... | OCR Scan |
4 pages, |
LC74HC76 13P1 74ls76 sanyo LS 2027 ATJ 2027 C LS 2027 74LS76 IC TTL 74ls76 IC 74LS76 74LS76 LC74HC76 abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 , 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE , 54LS/74LS109 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 ... | OCR Scan |
2 pages, |
74ls76 74196 ttl 74ls109 TTL 74109 ttl 74107 pin diagram of 7473 7473 latch 74LS76 FAIRCHILD 74LS109 74ls74 74ls107 ci 74LS74 fairchild 9024 CI 74107 datasheet abstract |
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| Abstract: inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a negative , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , go HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be stable one set-up time prior , unless otherwise noted.) PARAMETER TEST CONDITIONS1 7476 74LS76 UNIT Min Typ2 Max Min Typ2 , |-- TPHL -IV- V fZ For all waveforms, VM = 1,3V for 74S; VM = 1,5V for all other TTL families. The ... | OCR Scan |
6 pages, |
TTL 7476 Flip-Flop 7476 74ls76 j_k 74ls76 Jk 7476 i c 74ls76 ci 74ls76 7476 J-K Flip-Flop 7476 pin configuration PIN CONFIGURATION 7476 7476 TTL 74ls76 7476 PIN DIAGRAM input and output 7476 ttl 74LS76 74LS76 abstract |
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| Abstract: inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a negative , Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 , HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be stable one set-up time prior to the , unless otherwise noted.) PARAMETER TEST CONDITIONS1 7476 74LS76 UNIT Min Typ2 Max Min Typ2 , for all other TTL families The shaded areas Indicate when the input is permitted to change for ... | OCR Scan |
6 pages, |
LS76 N7476N N74LS76N pin diagram for jk flip flop 7476 TTL 7476 Jk 7476 7476 pin configuration 74LS76 ttl 74LS76 J-K Flip-Flop 7476 PIN CONFIGURATION 7476 7476 J-K Flip-Flop pin diagram of ttl 7476 74LS76 abstract |
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| Abstract: SANYO SEMICONDUCTOR CORP 12E »"J 7clci70?b OOOabbñ S LC74HG76M LC74HG76M 3035A CMOS High-Speed Standard Logic LC74HC LC74HC Series ©2186 Features Dual J-K Flip-Flop with Set and Reset The LC74HC76M LC74HC76M consists of 2 identical J-K type flip-flops. Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL (74LS76) with the low power dissipation and high noise margin of standard CMOS , TTL logic family. Absolute Maximum Ratings/Ta=25±2°C, Vss=OV Maximum Supply Voltage Maximum Input ... | OCR Scan |
1 pages, |
LC74HC76M LC74HC76 j-k flip flop 74ls76 74ls series logic family 74LS76 pinout 74ls76 Jk 74ls76 pin out TTL 74ls76 LC74HG76M LC74HC 74LS76 LC74HG76M abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 - J SD 0 _6 14 0 4 - CP 12 CP 3-0 K Co Q »1 13 -0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 ... | OCR Scan |
1 pages, |
74S109 ttl 7474 14 PIN Fairchild 9020 Fairchild 902 CD-D60 74LS109 74LS73 74LS107 74ls74 TTL 74ls76 7476 ttl 7474 14 PIN 74ls76 ttl 74ls109 datasheet abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 - J SD 0 _6 14 0 4 - CP 12 CP 3-0 K , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 2 7 , 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS Item Function DEVICE NO. Inputs ... | OCR Scan |
2 pages, |
74H74 Jk 74ls76 ttl 74ls109 pin diagram 7474 TTL 74107 flip flop jk pin diagram of 7473 7473 dual JK 7476 ttl 74LS74 TTL 7476 PIN DIAGRAM jk 7474 TTL 7474 74LS73 dual JK datasheet abstract |
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| Abstract: 13- CP CP 2- K Cd 0 0-6 12 K Co 0 Vcc = Pin 14 GND = Pin 7 13-50 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE NO. Inputs Clock Edge « m ci ai ci , ,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 54LS/74LS107 J,K "L - X 60 12 ... | OCR Scan |
2 pages, |
74196 TTL 74279 74LS107 74LS112 74ls112 pin diagram 74LS114 CI 74196 ci 7475 d147 Fairchild 902 fairchild 9314 7475 data latch 7475 D latch d146 54H/74H78 54H/74H78 abstract |
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| Abstract: Pin 8 13-53 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE , 54LS/74LS109 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 ... | OCR Scan |
2 pages, |
Fairchild 902 D146 ci 7475 74ls76 74LS109 74LS78 7475 data latch 74LS107 rs latch 54LS/74LS541 54LS/74LS78 54LS/74LS541 abstract |
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| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D145 9370, 9374 DIGITAL -TTL 0146 9314, 93L14 93L14 D147 54/74279, 54LS/74LS279 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 15 14 1 3 2 4 14 6 5 7 11 mijum Vcc E Do So Di Si D2 S2 D3 S3 MR Qo Ql 02 O3 TT 15 13 12 10 , Pin 8 13-62 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE , 54LS/74LS109 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 ... | OCR Scan |
2 pages, |
74ls76 74LS107 D148 D149 D150 D151 Fairchild 902 fairchild 9314 74L51 7475 FAIRCHILD 93L08 74LS279 74109 D146 pin diagram 7475 93L14 54LS/74LS279 93L14 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Latch $ENDCMP # $CMP 74LS76 D Dual JK FlipFlop, Set & Reset K TTL JK JKFF $ENDCMP # $CMP 74LS77 74LS77 74LS77 74LS77 EESchema-DOCLIB Version 2.0 Date: 10/10/2004-17:10:44 # $CMP 7400 D Quad nand2 K TTL nand2 $ENDCMP # $CMP 7402 D Quad Nor2 K TTL Nor2 $ENDCMP # $CMP 74HC00 74HC00 74HC00 74HC00 D Quad nand2 K HCMOS nand2 74HC74 74HC74 74HC74 74HC74 D Dual D FlipFlop, Set & Reset K TTL DFF F 74xx/74hc_hct74.pdf $ENDCMP # $CMP 74HCT00 74HCT00 74HCT00 74HCT00 D HCT04 HCT04 HCT04 HCT04 D Hex Inverseur K HCTMOS not inv $ENDCMP # $CMP 74LS00 74LS00 74LS00 74LS00 D Quad nand2 K TTL nand2 $ENDCMP www.datasheetarchive.com/files/kaleidoscope/cad/kicad - kicad/library/74xx.dcm |
Kaleidoscope | 10/10/2004 | 11.88 Kb | DCM | 74xx.dcm |
| , SN74ALS235 SN74ALS235 SN74ALS235 SN74ALS235, SN74BCT2952 SN74BCT2952 SN74BCT2952 SN74BCT2952, SN74LS76A, SN10KHT5540 SN10KHT5540 SN10KHT5540 SN10KHT5540, SN74ALS519 SN74ALS519 SN74ALS519 SN74ALS519, SN74BCT29833 SN74BCT29833 SN74BCT29833 SN74BCT29833) Obsolete Notification of SFAB Platinum Thickness Change for TTL Products Wafer Fab Process Change www.datasheetarchive.com/files/texas-instruments/sc/docs/asl/pcns.htm |
Texas Instruments | 12/02/1997 | 23.08 Kb | HTM | pcns.htm |
| _delay=9n) .model pldwn d_pulldown .ends * * * * Flip-Flop *SYM=T7476 T7476 T7476 T7476 *74LS76A DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR * .subckt 74LS76A clk * * * * * *SRC=74LS00 74LS00 74LS00 74LS00;74LS00 74LS00 74LS00 74LS00;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS00 74LS00 74LS00 74LS00 QUADRUPLE 2-INPUT POSITIVE ;74LS01 74LS01 74LS01 74LS01;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS01 74LS01 74LS01 74LS01 QUADRUPLE 2-INPUT POSITIVE-NAND GATES *WITH ;74LS02 74LS02 74LS02 74LS02;TTL;74LSxx;2 input NOR gate *SYM=NOR2 *74LS02 74LS02 74LS02 74LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/74ls.lib |
Spice Models | 18/04/2010 | 63.91 Kb | LIB | 74ls.lib |
| - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2 * -74ALS00- -74ALS00- -74ALS00- -74ALS00- * Quadruple 2-Input Positive NAND Gate * Motorola Schottky TTL Data Book,1983 * * * - 74F00 74F00 74F00 74F00 - * Quad 2-Input Nand Gate * * NS FAST Advanced Schottky TTL Data Book, 1988 * jds * * * - 74H00 74H00 74H00 74H00 - * Quad 2-Input Nand Gates * * The TTL Data Book, Vol. 2, 1985, TI Pages 3-3 to 3 * - 74LS00 74LS00 74LS00 74LS00 - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/dig000.lib |
Spice Models | 18/04/2010 | 473.91 Kb | LIB | dig000.lib |
| Sheet1 Sheet2 Sheet3 rxpw_1 Part # Model/Subckt Name Part Type SubType Description IGEN IGEN !Generators !Pulse Symmetric Current VGEN VGEN !Generators !Pulse Symmetric Voltage PSUPPLY PSUPPLY !Generators Power Power Supply PWRSPLY PWRSPLY !Generators Power Current Limited PWRSPLY2 PWRSPLY2 !Generators Power Sigmoid Current Limited AM AM !Generators Signal DCLK DClock !Generators Signal Digital oscillator DSOURCE Dsource !Generators Signal Digital source ExponentialI ExponentialI !Genera www.datasheetarchive.com/download/31304461-777572ZC/icap4rxpwrliblist.zip (ICAP4RxPwrlibList.xls) |
Spice Models | 29/07/2012 | 215.73 Kb | ZIP | icap4rxpwrliblist.zip |
| Sheet1 Sheet2 Sheet3 rxrf_1 Part # Model/Subckt Name Part Type SubType Description IGEN IGEN !Generators !Pulse Symmetric Current VGEN VGEN !Generators !Pulse Symmetric Voltage PSUPPLY PSUPPLY !Generators Power Power Supply PWRSPLY PWRSPLY !Generators Power Current Limited PWRSPLY2 PWRSPLY2 !Generators Power Sigmoid Current Limited AM AM !Generators Signal DCLK DClock !Generators Signal Digital oscillator DSOURCE Dsource !Generators Signal Digital source Exponential Exponential !Generato www.datasheetarchive.com/download/23131848-777573ZC/icap4rxrfliblist.zip (ICAP4RxRFlibList.xls) |
Spice Models | 29/07/2012 | 211.35 Kb | ZIP | icap4rxrfliblist.zip |
| Sheet1 Sheet2 Sheet3 rx_1 Part # Model/Subckt Name Part Type SubType Description IGEN IGEN !Generators !Pulse Symmetric Current VGEN VGEN !Generators !Pulse Symmetric Voltage PSUPPLY PSUPPLY !Generators Power Power Supply PWRSPLY PWRSPLY !Generators Power Current Limited PWRSPLY2 PWRSPLY2 !Generators Power Sigmoid Current Limited AM AM !Generators Signal DCLK DClock !Generators Signal Digital oscillator DSOURCE Dsource !Generators Signal Digital source ExponentialI ExponentialI !Generato www.datasheetarchive.com/download/46754491-777571ZC/icap4rxliblist.zip (ICAP4RxlibList.xls) |
Spice Models | 29/07/2012 | 198.91 Kb | ZIP | icap4rxliblist.zip |
| ) or ( 6, 7, 4,10, 11, 9, 8) ; swap ( ( 2, 3,13,16, 1,15,14), ( 6, 7, 4,10,11, 9, 8) ) ; } part 74ls76 : default so16,dil16 { newattr "$comment" = "Dual J-K Flip-Flop, Preset + Clear" ; newattr */ /* */ /* */ /* This library provides definitions of */ /* */ /* - Bipolar TTL Low Power Schottky / Series 74 manufacturer prefix or package type suffix) */ /* correspond to the entire TTL package or one of several www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |
| + tpdqhlmx=15ns + ) *$ *- * 74LS76A Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS76A CLK PREBAR LS00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 74LS01 74LS01 74LS01 74LS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book -Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74ls.lib |
Spice Models | 29/07/2012 | 571.07 Kb | LIB | 74ls.lib |
| + tpdqhlmx=15ns + ) *$ *- * 74LS76A Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS76A CLK PREBAR :26:32 $ * * *$ *- * 74LS00 74LS00 74LS00 74LS00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 74LS01 74LS01 74LS01 74LS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book -Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names www.datasheetarchive.com/files/spicemodels/misc/74ls.lib |
Spice Models | 19/12/2001 | 571.09 Kb | LIB | 74ls.lib |