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TTL+74ls76

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Abstract: and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , are unpredictable if SD and RD go HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be , temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 7476 74LS76 UNIT Min Typ2 -
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ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 76ls76- N7476N N74LS76N 1N916 1N3064
Abstract: HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , are unpredictable if 3 D and R d go HIGH simultaneously. 2. The 74LS76 is edge triggered. Data must be , Min Typ2 3.4 0.2 0.4 Max Min 2.7 74LS76 UNIT Typ2 3.4 0.35 0.25 -1 .5 1.0 0.1 0.3 0.4 40 80 80 20 60 -
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PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 logic diagram
Abstract: HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , . 2. The 74LS76 is edge triggered. Data must be stable one set-up time prior to the negative edge of , temperature range unless otherwise noted.) 7476 C M a. ? 74LS76 UNIT Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 -
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7476 pin configuration LS 7476 J-K Flip-Flop 7476 7476 74LS76 logic diagram TTL 74ls76
Abstract: and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , LOW, but the output states are unpredictable if SD and BD go HIGH simultaneously. 2. The 74LS76 is , CONDITIONS1 7476 74LS76 UNIT Min Typ2 Max Min Typ2 Max HIGH-level 0H output voltage Vcc - MIN -
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7476 ttl TTL 7476 LS76 74LS76 ttl Jk 7476 74LS
Abstract: /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , /74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 -
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CI 7474 CI 7473 7474 D latch CI 74LS76 CI 74107 fairchild 9024 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54H/74H73
Abstract: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation is loaded into the master while the Clock is HIGH and trans ferred to the slave on the HIGH-to-LOW , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , . d. The 74LS76 is edge triggered. Data m ust be stable one setup tim e p rio r to the negative edge o -
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logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC 54LS/74LS76 N74H76N N74H76F N74LS76F S5476F S54H76F
Abstract: /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are -
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TTL 74ls74 7474 14 PIN ttl 74ls109 74LS107 74LS73 74ls74 54LS/74LS73 54H/74H103
Abstract: SANYO SEMICONDUCTOR CORP 12E »"J 7clci70?b OOOabbñ S LC74HG76M 3035A CMOS High-Speed Standard Logic LC74HC Series ©2186 Features Dual J-K Flip-Flop with Set and Reset The LC74HC76M consists of 2 identical J-K type flip-flops. Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL (74LS76) with the low power dissipation and high noise margin of standard CMOS ICs. Has buffered outputs, improving the output transition characteristics. All inputs are -
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LC74HC76 74LS76 pinout 74ls series logic family 74LS76 dual flip-flop j-k flip flop 74ls76 54LS/74LS 5146KI
Abstract: 54/7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK information is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , the output states are unpredictabfe if Sd and Rd go HIGH simultaneously. d. The 74LS76 is edge -
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74Ls76 truth table Flip-Flop 7476 74ls76 pin configuration TT 7476 N7476F S54LS76F S5476W S54H76W S54LS76W 54H/74H
Abstract: 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 -
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d146 RS latch 7475 D latch 74LS78 d147 74LS114 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113
Abstract: HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , . The 74LS76 is edge triggered. Data must be stable one set-up time prior to the negative edge of the , range unless otherwise noted.) 7476 74LS76 UNiT Min Typ2 3.4 0.2 0.4 Max Min 2.7 Typ2 3.4 0.35 0.25 -1 -
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flip-flop 74ls76 Diagram of 7476
Abstract: /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are -
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7476 JK TTL 7474 ttl 7474 14 PIN 7474 PIN DIAGRAM pin diagram 7474 jk 7474 74H71 54H/74H101 54H/74H72 54H/74H102 54LS/74LS113
Abstract: 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 -
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ci 7475 74LS109 74L576 TTL 7475 fairchild 9314 pin diagram 7475 93L14 54LS/74LS279 54LS/74LS75 93L08 54LS/74LS77 54S/74S175
Abstract: 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 -
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74LS92 CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 54/7490A 54LS/74LS90 S4/74293 54LS/74LS293 S4/7493A
Abstract: D60 4L,6B,9B 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X -
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7475 data latch Fairchild 902 1L20 CI 74109 TTL 74109 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373
Abstract: LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s (with S e t and Reset) Description D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits, each w ith independent clock-C P, J, K, and directcoupled set and reset input terminals. P -2 · · · · · Features Negative-edge trigger Independent input and ou tp u t term inals for each flip-flop D irect-coupled set and reset Q and Q outputs Wide operating tem perature range (Ta = - 2 0 to + 75 -
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logic ic 74LS76 pin diagram IC 74LS76
Abstract: ro - Item Dual JK 54LS/74LS78 c_ Dual JK Dual JK Dual JK Dual JK 54LS/74LS76 , 0 -8 UJ z D58 54/7476, 54H/74H76, 54LS/74LS76 3- K , Q Cd Cd C O UJ 2 J l -
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ic 74109 7476 Connection diagram IC 74196 74109 dual JK 54 dual JK fairchild IC 74LS76 pin diagram 54LS/74LS197 54LS/74LS196
Abstract: 74LS51 74LS51A 74LS51B 74LS54 74LS55 74LS64 74LS73 74LS73A 74LS74 74LS74A 74LS75 74LS76 74LS76A 74LS77 -
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74LS82 74LS176 74LS94 74LS286 74ls150 74LS177
Abstract:  Nil2 0 27a 5156 LC74HC76 D u a I J - K F l i P «FI o P With R e gfjá ìnIn D Set WMfz.a-'X Na2027 â'¢LC74HC76à J- 7 'J -y D-yT" I UXTÃV, LS â'¢ TTL (74LS76) â'¢ÃfiíSREISa-sST»*. // â'¢ T TL ©4*4*5 4 LS/74LS n*J*> 9 V 5. T é = 2 5 ±2V, V sS=0V un « t VcCflftx V â'¢ S V VlNmax -0» - 5 V VOUTmai -JO^-^VCC+O-5 V I OUT ±25 mA ¡h*W« I CC/ I Gn// ±50 mA J It // ±20 mA Pómàf^/ 300 mW ttttMHfiK Tit.// -65^+150 x: â'¢Ã­-t-isjí^m Tjl/ t=10*ac -
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74LS76 IC LS 2027 sanyo LS 2027 ATJ 2027 C 13P1 AJJM DIP16 S156TSIWI/8295TSR 2027-1M 15PFV
Abstract: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151 -
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74LS152 74LS183 74LS248 74LS258 74LS275 74LS356 74ls series 74LS396 7447 74LS153 74LS155 74LS157 74LS158 74LS160A
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