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Part Manufacturer Description Datasheet BUY
SN7410N-00 Texas Instruments TTL/H/L SERIES, TRIPLE 3-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN7410J-00 Texas Instruments TTL/H/L SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 visit Texas Instruments
SN7410J Texas Instruments TTL/H/L SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 visit Texas Instruments
SN74107J-00 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 visit Texas Instruments
SN7410N-10 Texas Instruments IC TTL/H/L SERIES, TRIPLE 3-INPUT NAND GATE, PDIP14, Gate visit Texas Instruments
SN74107N-10 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 visit Texas Instruments

TTL 7410

Catalog Datasheet MFG & Type PDF Document Tags

TTL 7410

Abstract: Optoway GBB-7410 * GBB-7410 1310 nm TX / 1550 nm RX , 5V / 1250 Mbps 1-Fiber Single-Mode WDM Gigabit Interface , ) * FEATURES DESCRIPTION l l l l The GBB-7410 series single-mode optical transceivers meet the , interface is used. TTL RX-LOS output simplifies interface to external circuitry. A 20-pin SCA-2 host , SCA-2 Host Connector Single +5 V Power Supply Differential PECL Inputs and Outputs TTL RX-LOS
OPTOWAY Technology
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TTL 7410

Abstract: 7410 PCX-7410 FIXED PULSED/CW LASER DIODE · · · · 10A Pulsed/QCW and 5A CW Maximum Output Current >18V , Interfaces Store and Recall up to 5 System Configurations · · The PCX-7410 is a high power CW and pulsed , rear panel, low impedance ribbon cable, designed to preserve the fidelity of high-speed, large The PCX-7410 , /QCW and CW (DC) outputs. It can serve as interlocked, so that the PCX-7410 is disabled when the , 1A to 10A. Furthermore, the output may be biased to any CW current from The PCX-7410 features
IXYS
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Abstract: PCX-7410 FIXED PULSED/CW LASER DIODE â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ 10A Pulsed/QCW and 5A CW , high-speed, large The PCX-7410 offers the unique capability of providing amplitude current pulses. The output connector is both pulsed/QCW and CW (DC) outputs. It can serve as interlocked, so that the PCX-7410 , from The PCX-7410 features advanced circuitry to protect 100mA to 5A, then pulsed above this bias , -7410â'™s output is to 10A maximum. electronically shorted to ground, ensuring that no curThe PCX-7410 can IXYS
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TTL 7411

Abstract: TTL 7410 Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Triple Three-Input NAND ('10), AND ('11 , (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA 74LS11 9ns 2.6mA 74S11 5ns , 7410, 7411, LS10, LS11, S10, S11 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperatures unless , Specification Gates 7410, 7411, LS10, LS11, S10, S11 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 7410, 11 74LS10, 11
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TTL 7411 TTL 7410 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 74LS10 pin configuration LS 7411 N7410N N74LS10N N74S10N N7411N N74LS11N N74S11N

TTL 7411

Abstract: PIN CONFIGURATION 7410 Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates I Triple Three-Input NAND ('10), AND ('11) Gates Product Specification Logic Products TYPE 7410 74LS10 74S10 7411 74LS11 74S11 TYPICAL , Product Specification Gates 7410, 7411, LS10, LS11, S10, S11 ABSOLUTE MAXIMUM RATINGS PARAMETER , 5 -3 1 Signetics Logic Products Product Specification Gates 7410, 7411, LS10, LS11, S10 , otherwise noted.) 7410, 11 TEST CONDITIONS1 Min 0H Vcc = MIN, V,L = MAX, V|H = MIN, Iqh - MAX Vcc = MIN
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TTL LS 7411 74LS11 function table 74 LS 00 Logic Gates TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10 7410 pin configuration N74LS10D N74S10D N74LS11D N74S11D LS0343DS LS03640S

TTL 7410

Abstract: ua 7411 Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Triple Three-Input NAND (10), AND ('11 , (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA 74LS11 9ns 2.6mA 74S11 5ns , Specification Gates 7410, 7411, LS10, LS11, S10, SU ABSOLUTE MAXIMUM RATINGS (Over operating free-air , Specification Gates 7410, 7411, LS10, LS11, S10, S11 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 7410, 11 74LS10, 11
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ua 7411 7411 pin configuration 74ls TTL 7410 11 input 74LS11 pin configuration 74ls TTL family LS00640S 1N916 1N3064

LM 7410

Abstract: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input , TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA , 853-0508 81501 Product Specification Signetics Logic Products Gates 7410, 7411, LS10, LS11, S10 , Gates 7410, 7411, LS10, LS11, S10, S11 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) 7410, 11 PARAMETER 0H HIGH-level
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LM 7410
Abstract: TECHNICÃ"RP/ GREENRAY 37F n AARi.qpq nnnnsui ? -r- s û ù s ' - ' CRYSTAL OSCILLATORS HF to VHF CRYSTAL OSCILLATORS 60 MHz to 100 MHz TTL Model ±.005% SPECIFICATIONS: Input , +70°C Sealed metal case for shielding Output: to drive , MODEL ZY-7410 or ZY-496 MODEL: ZY-7410 Input current: 100 ma. maximum Size: 1.4" X .8" ± .35" (L-W-H) To order: Specify Model ZY-7410 and exact output frequency desired. SPECIFICATIONS -
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ZY-7403 ZY-7410 Y-367 Y-367L

7404 ttl inverter

Abstract: 7402 TTL Digital Integrated Circuits TTL Gates NKT provides a range of standard TTL gates, normally supplied in plastic dual-in-line packages. They are fully compatible with similarly coded '7400 series' devices. DIC 7400 QUAD 2 input NAND DIC 7401 QUAD 2 input NAND (open collector 5.5V rating) DIC 7402 , 7405 Hex Inverter (open collector 5.5V rating) DIC 7410 TRIPLE 3 input NAND DIC 7420 DUAL 4 input , ,_, ^J tâ'"n] 5â'"^ a6 k]Z6 a5 s]a4 DIC 7404, 7405 DIC 7410 DIC 7420,7440 14 LEAD TO 116
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7404 ttl inverter 7402 TTL 7404 7404 hex inverter TTL 7420 TTL 7430

TTL 7410

Abstract: DM74ALS574A , ion-implanted Schottky TTL process n Functionally equivalent with LS374 n Improved AC performance over LS374 , /14 PrintTime=15:09:22 7410 ds006110 Rev. No. 1 cmserv Proof 1 1 Function Table , 7410 ds006110 Rev. No. 1 2 cmserv Proof 2 Absolute Maximum Ratings Supply Voltage , 28 mA -30 Outputs Disabled 3 PrintDate=1997/08/14 PrintTime=15:09:24 7410 ds006110 Rev , PrintDate=1997/08/14 PrintTime=15:09:25 7410 ds006110 Rev. No. 1 4 cmserv Proof 4 Logic
National Semiconductor
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DM74ALS574A DM74ALS574AN DM74ALS574ASJ DM74ALS574AWM M20D ALS574A

TTL 7410

Abstract: 74LS11 function table Signetics I 7410, 7411, LS10, LS11 S10, S11 Gates Triple Three-Input NAND ('10), AND ('11) Gates Product Specification Logic Products TYPE 7410 74LS10 74S1Û 7411 74LS11 74S11 TYPICAL , Gates 7410, 7411, LS10, LS11, S10, S11 ABSOLUTE MAXIMUM RATINGS PARAMETER Vcc V|N l|N Supply , Gates 7410, 7411, LS10, LS11, S10, S11 DC ELECTRICAL CHARACTERISTICS PARAMETER v 0H y 0L . ,K , recommended operating free-air temperature range unless otherwise noted.) 7410, 11 TEST CONDITIONS1 Min
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7411 signetics LS03430S IS03640S

74573

Abstract: 74574 Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together. The following tables are available . TTL Device Summary CMOS Device , device is suitable for your purposes. 1 of 12 E&OE. TTL Device Summary Please click on a , 7404 7405 7406 7407 7408 7410 7411 7414 7420 7421 7427 7430 7432 7447 7448 7473 7474
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74573 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432

9n10

Abstract: ttl 7410 FAIRCHILD TTL/SSI . 9N10/5410, 7410 TRIPLE 3-INPUT NAND GATE LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) FifïïifTillïïiramrn Lj[2j[3jLJl¿JLJU Positive logic: Y = ABC FLATPAK (TOP VIEW) Vcc O- SCHEMATIC DIAGRAM (EACH GATE) Component values shown are typical. RECOMMENDED OPERATING CONDITIONS PARAMETER 9N10XM/5410XM 9N10XC/7410XC UNITS MIN. TYP. MAX. MIN. TYP. MAX. Supply Voltage Vcc 4.5 5.0 , = MAX. 5 -18 -55 mA 9N10/7410 'CCH Supply Current HIGH 3.0 6.0 mA VCC = MAX., V|N = 0V 6
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9n10 9N10 7410 NAND Gate 3-Input 7410 9N10/7410PC ScansUX999 9N10/7410

7404 TTL CMOS

Abstract: TTL 74h04 iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S , . a> Q. » Q c o ï 2
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7404 TTL CMOS TTL 74h04 TTL 7400 fairchild TTL 7404 fairchild 9016 CI 74LS00 TTL 7404 fairchild 54H/74H04 54S/74S04 54LS/74LS04 9S05A 54H/74H05 54S/74S05

TTL 7410

Abstract: TTL 7401 iii LÃ QND LJ Id Lil W Ã LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S , Ended 16 3.0 -5.2 510 4 E105 4L,6B 2 54S/ 74S140 Dual 2-NAND Any TTL TTL Volt Single Ended 40 4.0 +5.0 88 2 D5 3I, 6A,9A 3 54LS/ 74LS240 Octal Inverting Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 175 8 D73 9Z 4 54LS/ 74LS241 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D74 9Z 5 54LS/ 74LS244 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D77 9Z 6 54LS/ 74LS540
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TTL 7401 74LS00 TTL IC TTL 74LS00 TTL 74LS04 7404 TTL 74H04 54L8/74LS05 54LS/74LS14 54H/74H00 54S/74S00 54LS/74LS00 54H/74H01

GSP2E-7401

Abstract: sirf grf2i -bit wide in the GSP2e-7400 series and is 32-bit wide in the GSP2e-7410 series. The processor supports 8 , -bit bus in the 7400 series requires 2 access cycles for 32-bit data while the 32-bit bus in the 7410 , Schematic for GSP2e-7410/7411 Interface to 32-bit Memory , requires two access cycles, while in the 7410 series only one access cycle. To interface the 740X series , to 8 bit wide memory (D[0.7]): connect A0 of memory to MUB[0] of 7410 A1 of memory to MUB[1] of
SiRF Technology
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APNT0012 GSP2E-7401 sirf grf2i GSP2E GSP2e-7400 GSP2E7410 7400 series pin connection 16-BIT

ITT 7400

Abstract: 74h01 FAIRCHILD DIGITAL TTL SSI FUNCTIONS c o_ 5 5= c o o c 3 u. NAND Gates 1 2 3 4 5 ' 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Hex Inverters Hex Inverts (OC) Hex Inverter (15 V) Hex Inverter (30 V) Hex Schm itt Trigger Quad 2-Input Quad 2-Input (OC) Quad 2-Input (OC) Quad 2-Input (12 V , /74LS26 7426 54LS/74LS37 54/7437 74LS38 - 74LS132 54/7438 54/7439 54/74132 54LS/74LS10 54/7410 - 54 , li J l£ l L il GND 111 liJ liJ 111 111 111 111 GND D4 9003, 54/7410, 54H/74H10, 54S/74S10
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ITT 7400 74h01 TTL 7414 fairchild 7404 74h00 74LS40 OC/48 54LS/74LS05 54H/74H20 54H/74H22 54H/74H40 54H/74H30

IC 7404 7406

Abstract: 74LS00 7400 74S00 iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S , Là QND 13-42 FAIRCHILD DIGITAL TTL SSI FUNCTIONS « E O Q) _ o -c ° S »S « >.35 8i 2 E , 54/7410 54H/74H10 54S/74S10 D4 3I,6A,9A 15 Triple 3-lnput (OC) â'" â'" 54/7412 â'" â'" D4 3I,6A,9A
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IC 7404 7406 74LS00 7400 74S00 ic 7404 74LS04 Hex Inverter Gates ic 74132 Fairchild 9002 54S/74S03 54LS/74LS03 54LS/74LS26 54S/74S132 54S/74S20 54LS/74LS20

7400 fan-out

Abstract: 7402 nor Logic Integrateci Circuits, MIC 7400 Series TTL Gates in order of gates per package Type Positive logic Gates per Inputs per Typ. Typ. Max. definition package gate propagation dissipation fan-out delay per package per gate ns mW MIC 7430 NAND 1 8 13 10 10 MIC 7453 AND-OR-INVERT1 1 2-2-2-2 13 22 10 MIC 7454 AND-OR-INVERT 1 2-2-2-2 13 22 10 MIC 7420 NAND 2 4 13 20 10 MIC 7440 NAND , 7460 AND 2 4 5 8 42 MIC 7410 NAND 3 3 13 30 10 MIC 7400 NAND 4 2 13 40 10 MIC 7401 NAND 4 2 35 40 10
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7400 fan-out 7402 nor 7491 8-bit 7490 Decade Counter TTL 7400 TTL 7400 propagation delay

TTL 7404

Abstract: 7404 TTL iii LÃ QND LJ Id Lil W Ã LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S , Ended 16 3.0 -5.2 510 4 E105 4L,6B 2 54S/ 74S140 Dual 2-NAND Any TTL TTL Volt Single Ended 40 4.0 +5.0 88 2 D5 3I, 6A,9A 3 54LS/ 74LS240 Octal Inverting Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 175 8 D73 9Z 4 54LS/ 74LS241 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D74 9Z 5 54LS/ 74LS244 Octal Bus Dvr Any TTL TTL Volt Single Ended 40 12 +5.0 180 8 D77 9Z 6 54LS/ 74LS540
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TTL 7404 nand ttl 7400 TTL 741 CI 74LS04 74IS244 7400 ecl nand 74S22 54LS/74LS22 54S/74S40 54LS/74LS40 54S/74S140 90CI9
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