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Part : TMP821DR Supplier : Texas Instruments Manufacturer : Avnet Stock : 12,500 Best Price : $0.2769 Price Each : $0.3169
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Part : TMP82C51AM-2 Supplier : Toshiba Manufacturer : Chip1Stop Stock : 439 Best Price : $25.60 Price Each : $34.9000
Part : TMP82C51AP-2 Supplier : Toshiba Manufacturer : Chip1Stop Stock : 1,913 Best Price : $25.60 Price Each : $34.9000
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TMP82 Datasheet

Part Manufacturer Description PDF Type
TMP821DR Texas Instruments PMIC - Motor, Bridge Drivers, Integrated Circuits (ICs), IC MOTOR CONTROLLER PAR 8SOIC Original
TMP821DR Texas Instruments TMP821 - Two-Phase Half-Wave Motor Predriver 8-SOIC Original
TMP821DR Texas Instruments Two-Phase Half-Wave Motor Predriver 8-SOIC Original
TMP821DRG4 Texas Instruments PMIC - Motor, Bridge Drivers, Integrated Circuits (ICs), IC MOTOR CONTROLLER PAR 8SOIC Original
TMP821DRG4 Texas Instruments TMP821 - Two-Phase Half-Wave Motor Predriver 8-SOIC Original
TMP821DRG4 Texas Instruments Two-Phase Half-Wave Motor Predriver 8-SOIC Original
TMP8243P Toshiba Input / Output Expander Scan
TMP8243PI Toshiba Input / Output Expander Scan
TMP8253 Toshiba PROGRAMMABLE INTERVAL TIMER Scan
TMP8253P-5 Toshiba PROGRAMMABLE INTERVAL TIMER Scan
TMP8255A Toshiba PROGRAMMABLE PERIPHERAL INTERFACE Scan
TMP8255AP-5 Toshiba PROGRAMMABLE PERIPHERAL INTERFACE Scan
TMP8259 Toshiba Programmable Interrupt Controller Scan
TMP8259AP Toshiba PROGRAMMABLE INTERRUPT CONTROLLER Scan
TMP8279 Toshiba Programmable Keyboard / Display Interface Scan
TMP8279P-5 Toshiba Programmable Keyboard / Display Interface Scan
TMP82C255A Toshiba CMOS PROGRAMMABLE PERIPHERAL INTERFACE Scan
TMP82C255A Toshiba IC,PERIPHERAL INTERFACE,CMOS,QFL,80PIN,PLASTIC Scan
TMP82C255AF-10 Toshiba CMOS PROGRAMMABLE PERIPHERAL INTERFACE Scan
TMP82C255AF-2 Toshiba CMOS PROGRAMMABLE PERIPHERAL INTERFACE Scan
Showing first 20 results.

TMP82

Catalog Datasheet MFG & Type PDF Document Tags

P8243

Abstract: TMP8048P Respective Manufacturer INTEGRATED CIRCUIT TOSHIBA technical data TMP8243P/TMP8243PI All communication , presence of data. Additional TMP8243P'S may be added to the 4-bit bus and chip selected using additional , technical data TMP8243P/TMP8243PI Sink Capability The THP824 31' can sink 5 mA , which can be divided in any way among the remaining 9 I/O lines of the TMP8243P. Example: This examples , /TMP8243 PI TMP8243P ABSOLUTE MAXIMUM RATINGS Symbol 1 ten Rating vCc VCC Supply Voltage with Respect
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OCR Scan
P8243 TMP8048P P8243 intel TMP8049P toshiba TMP8049P Intel 8243 TLCS-84 TMP8048P/TMP8049P P/TMP8243 P20-J3 P20-23 TMF6243P/THPI243PI

P8243

Abstract: TMP8048P Electronic-Library Service CopyRight 2003 INTEGRATED CIRCUIT TOSHIBA technical data TMP8243P/TMP8243PI All , indicates the presence of data. Additional TMP8243P'S may be added to the 4-bit bus and chip selected using , TOSHIBA technical data TMP8243P/TMP8243PI Sink Capability The THP824 31' can sink 5 mA , current capability which can be divided in any way among the remaining 9 I/O lines of the TMP8243P. , technical data TMP8243 P/TMP8243 PI TMP8243P ABSOLUTE MAXIMUM RATINGS Symbol 1 ten Rating vCc VCC
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OCR Scan
8035P p8243p 8243P CI P 8243 N THH10 TMP8049
Abstract: TOSHIBA INTEGRATED CIRCUIT TMP8259AP TECHNICAL DATA TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic N-Channel Silicon Gate MOS TMP82 59 AP PROGRAMMABLE INTERRUPT CONTROLLER GENERAL DESCRIPTION The TMP8259AP is a programmable interrupt controller. It handles up to eight , /ÏN CAS2 â'" 487 â'" - INTEGRATED CIRCUIT TOSHIBA TECHNICAL DATA TMP8259AP , AO TMP8259AP TECHNICAL DATA Input/Output Input Function AO Address Line. This pin -
OCR Scan
TKP82 8259AP

2E P621

Abstract: 70F3479 TOSHIBA TMP82C55A CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C55A (hereinafter referred to as PPI) is a CMOS , tmp82c55ap-2/ap-10 tmp82c55am-2/am-10 050489 BLOCK DIAGRAM d7~d0 rd wr cs Ao Ai reset bidirectional data , PROGRAMMABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A (hereinafter , . (1) High Speed Version (TRD = 100ns MAX: TMP82C55AP-10/AM-10) (2) Low power consumption 2mA Type
NEC
Original
PD70F3939 PD70F3488 2E P621 70F3479 PMC151 p1240 encoder BV EI 382 1191 V850E/SJ3-H V850E/SK3-H PD70F3474 PD70F3477 PD70F3931 PD70F3934

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A TOSHIBA TMP8255A PROGRAMMABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable input/output interface , , [ 19 PB2 C 20 25 ]PB7 24 ]PB6 23 ]PB5 22 ]PB4 21 ]PB3 26 ]VCC( + 5V) TMP8255AP-5 MPU85 , TMP8255AP-5 UNIT MIN. MAX. tAR Address set-up time for RD fall 0 - ns tRA Address hold time for RD , operation mode Figure 5.1 shows the control words to define operation mode of the TMP8255A. Control Word
DigiKey Electronics Catalog
Original
schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon LN086WP38 LN11WP23 LN11CP23 LN11WP24 LN11WP34 LN11WP38

74ls219

Abstract: billion transformer e 3103 308 30631 . The TMP82C51AP-2/TMP82C51AP-10 is packaged in the 28 pin standard Dual Inline Package. The TMP82C51AM-2/TMP82C51AM-10 is packaged in the 28 pin Sm all O ut Line Package. FEATURES · Synchronous: 5-8 B it , TOSHIBA TMP82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51 AM-2/TMP82C51 AM-10 PROGRAMMABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION The TMP82C51A is the industry standard U niversal Synchronous , Autom atic Break Detect and H andling · Transfer Rate TMP82C51A-2 TMP82C51A-10 DC-104K bps DC-300K bps ·
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OCR Scan
74ls219 billion transformer e 3103 308 30631 Panasonic DM 20201 SILICON pnp transistor LA3350 tdc1007j tca280 S2000 J24616 J26487 K25582 CH-5404 54070Z

TMP82C55AP-2

Abstract: TMP82C55A TOSHIBA PROGRAM M ABLE INTERVAL TIMER TMP8253P-5 1. GENERAL DESCRIPTION TMP8253 T he T M P , .1 TMP8253Tim ing Diagrams MPU85-125 TOSHIBA 7. PROGRAM M ING THE TMP8253 TMP8253 A ll of th e M , [ 8 CLKO [ 9 OUTO C 10 GATEO C 11 GND C 12 MPU85-119 TOSHIBA 4. BLOCK DIAGRAM TMP8253 MPU85-120 TOSHIBA 5. PIN NAMES AND PIN DESCRIPTION TMP8253 · · · · · · · · , Bus Buffer TMP8253 T his is 3-state, bidirectional, 8 b it buffer used for interfacing the TM
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OCR Scan
ssop40 TMP82C55AP TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 TMP82C55AP-10/AM-10 MPU85-133 MPU85-167 MPU85-168

TMP8255AP-5

Abstract: TMP8255AP5 TOSHIBA CMOS PROGRAM M ABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 TMP82C55A 1. GENERAL DESCRIPTION AND FEATURES T h e T M P 82C 55A ( h e r e in a f t e r r e f e r re , ] P B 7 24 ] P B 6 23 ] P B S 22 ] P B 4 21 ] P B 3 TMP82C55A TMP82C55AP-2/AP-10 TMP82C55AM-2/AM , p u t/O u tp u t 3-state 3-state b id ire c tio n a l Do~D 7 8 8 TMP82C55A Pin N am e Fu , DESCRIPTION TMP82C55A T he PPI is a p rogram m able p erip h e ra l in terface device w ith th ree 8 -b
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OCR Scan
TMP8255AP5 MPU85-128 MPU85-129 MPU85-142 MPU85-143 MPU85-144 MPU85-145

TMP82C51

Abstract: TMP82C51AP-2 TOSHIBA PROGRAM M ABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES TMP8255A The TMP8255A (hereinafter referred to as PPI) is a high Speed program m able input/output , 23 ] P B 5 22 i p b 4 21 ]PB3 20 TMP8255AP-5 MPU85-153 TOSHIBA 3. BLOCK DIAGRAM D 7 ~D , Figure 5.1 shows the control words to define operation mode of the TMP8255A. C o n tro l W o rd 1 G , LOGIC D A T A B U S B U F FE R TMP8255A IN T E R N A L 8 -BIT B U S GRO UPA PO RTA PO R T C
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OCR Scan
82C51A TMP82C51AP AM-2/TMP82C51 TMP82C51AP-2/TMP82C51AP-10 TMP82C51AM-2/TMP82C51AM-10 MPU85-26

8253P

Abstract: p8253 TOSHIBA PR O G R A M M A B LE INTERVAL TIM ER TMP82C54P-2 / TMP82C54M-2 TMP82C54 The TMP82C54P-2 TMP82C54M-2 (hereafter called the TMP82C54) is a low power, CMOS general-purpose programmable , TMP82C53P-2 (TMP82C54P-2) Three independent, 16-bit counters Count data read is available. Status read is available. Six programmable Counter modes Binary/decimal count selection High-speed operation TMP82C54P-2/M , (Chip Select input) A low this input enables the TMP82C54. Unless CS is in the enabled state, the read
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OCR Scan
8253P TLCS-85A p8253 P8253A P8253 MPU85-130 MPU85-131 24PIN
Abstract: TO SH IBA MULTIMODE DMA CONTROLLER TMP8237AP/TMP8237AP-5 1. GENERAL DESCRIPTION TMP8237A T , TMP8237A 1 2 40 ] - 39 ] - Ay A6 I 3 [ 4 [ 38 p - As 37 ] - *- a 4 36 ] 35 ] - 34 32 , (16) t TEM PO RARY COUNT REGISTER (16) t Figure 3 .2 Block Diagram o f TMP8237A d req M E M , R N A L D A T A BU S l/O BU FFER ST A T U S (8) TEM PO RARY (8) TMP8237A TO SH IBA 4. PIN NAME & FUNCTION TMP8237A · · vcc + 5V pow er supply VSS G round · CLK (Clock -
OCR Scan
P82C55A P82C55AP-10/AM PU85-147 PU85-148 PU85-149 DIP40-P-600

P8255

Abstract: P8255A TMP8259AP PROGRAM M ABLE INTERRUPT CONTROLLER TMP8259AP 1. GENERAL DESCRIPTION TMP8259AP is a , . TMP8259AP cs c 1 WR RD d6 c 2 28 26 25 24 22 21 PIN CONNECTIONS (TOP VIEW ) VC C INTA IR , tp u t In p u t Chip Sele ct Inp ut. Fu nctio n TMP8259AP Pin N am e CS A lo w on this pin e , TMP8259AP 050489 M PU85-200 TOSHIBA 5.1 ABSOLUTE M A X IM U M RATINGS SYM BO L VCC VIN PD Tsol , TMP8259AP -65"C to + 150'C 0C to 70'C 050489 5.2 DC CHARACTERISTICS Ta = Oto + 70°C, VCC = 5V ± 10
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OCR Scan
P8255 P8255A P8255AP-5 05CW89 MPU85-154 MPU85-169 MPU85-170 MPU85-171

MPU85-9

Abstract: PROGRAMMABLE PERIPHERAL INTERFACE TMP82C255AN-2 / TMP82C265AF-2 TMP82C255AN-10 / TMP82C265AF-10 1. GENERAL , -2 : TMP82C255AN-2, TMP82C265AF-2 A-10 : TMP82C255AN-10, TMP82C265AF-10 Note 2: Following AC specifications of , Version (TRD = 100ns MAX : TMP82C255AN-10/TMP82C265AF-10) Low power consumption 3mA. Typ. 10pA. MAX. (@5V , lG 3 TMP82C255A/TMP82C265A T -5 2 -3 3 -0 3 PIN CONNECTIONS (TOP VIEW) TMP82C255AN-2 , with six 8 -bit I/O ports. The function is almost equivalent to TMP82C55AX2. The TMP82C265A has the
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OCR Scan
MPU85-9 TMP82C54P-2/M-2 MPU85-93 PU85-94 PU85-116 DIP24-P-600 PU85-118

P8237A

Abstract: TMP8237Af DIP (SDIP), G: Ceramic Flat Package (QFP) TLCS-85 Family (CMOS) Type No. Function TMP82C37AO-5 * TMP82C37BQ-8 Programmable D M A Controller TM P82C5IAD-2 Programmable Com m unication Interface TMP82C51A d - 10 Programmable Interval Timer TMP82C54Q-2 TMP82C55AD-2 T M P 8 2 C 5 5 A Q 10 Programmable Peripheral Interface TMP82C59AD-2 Programmable Keyboard Display Interface Remarks 5/TB , - - - TMP82C265AF-2 TMP82C265AF-I0 Programmable Peripheral Interface x 2 3 /3 5
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OCR Scan
P8237A TMP8237Af TMP8237AP/TMP8237AP-5 P8237AP/A TC74HC373P PU85-245 PU85-246
Abstract: TOSHIBA TMP82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51AM-2 / TMP82C51AM-10 PROGRAMMABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION The TMP82C51A is the industry standard Universal Synchronous , TMP82C51AP-2/TMP82C51AP-10 is packaged in the 28 pin standard Dual Inline Package. The TMP82C51AM-2/TMP82C51 , Automatic Break Detect and Handling â'¢ Transfer Rate TMP82C51A-2 TMP82C51A-10 DC-104K bps DC-300K bps â , Protrusion is 0.15mm. MPU85-59 TOSHIBA TMP8251A PROGRAMMABLE COMMUNICATION INTERFACE TMP8251AP 1 -
OCR Scan
PU85-198 PU85-202 PU85-203 MPU85-204 D1P28-P-600

MPU85-347

Abstract: - ns 050489 Note 1: A-2 : TMP82C255AN-2, TMP82C265BF-2 A-10 : TMP82C255AN-10, TMP82C265BF-10 , /TMP82C265B CMOS PRO G RAM M ABLE PERIPHERAL INTERFACE T - 5 2 .- 3 3 - S 3 TMP82C255AN-2 /TMP82C265BF-2 TMP82C255AN-10 /TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C255A , S H IB A 2. TMP82C255A/TMP82C265B PIN CONNECTIONS (TOP V IEW ) TMP82C255AN-2/TMP82C255AN-10 TMP82C265BF-2/TMP82C265BF-10 O l/l Û I !/>
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OCR Scan
MPU85-347 TMP82C255A/TMP82C265A TMP82C255AN-10/TMP82C265AF-10 TMP82C255AN TMP82C265AF MPU85-317 TMP68010

2SKI34

Abstract: westinghouse general purpose 8bit parallel interface TMP82C55AP-5. TC8864F-00 term inals for the operations are H D B
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OCR Scan
2SKI34 westinghouse TA8515 TOSHIBA DIODE CATALOG LSI LOGIC product catalog CTC 313 transistor pin diagram J22587 90-3D

tmp8251ap

Abstract: tmp8251 TOSHIBA INTEGRATED CIRCUIT TMP8259AP TECHNICAL DATA TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic N-Channel Silicon Gate MOS TMP82 59 AP PROGRAMMABLE INTERRUPT CONTROLLER GENERAL DESCRIPTION The TMP8259AP is a programmable interrupt controller. It handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. FEATURES o o o o o Eight Level Priority Controller, Expandable
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OCR Scan
tmp8251 82C51 USART 8251 pin diagram 8251A intel 8251 USART control word format 8251A TMP82C51AM-2/TMP82C51 MPU85-42 P8251A MPU85-74 MPU85-75
Showing first 20 results.