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Sun UltraSparc T2

Catalog Datasheet MFG & Type PDF Document Tags

Sun UltraSparc t2

Abstract: Sun UltraSparc UltraSPARC T2 Reference Design Kit, with everything you need to start designing, go to: sun. com/products , UltraSPARC® T2 Processor with Wind River Platform for Network Equipment, Linux Edition The future , latency · Wind River Platform for Network Equipment, Linux Edition, running on the UltraSPARC® T2 , UltraSPARC T2 processor is a true "system on a chip" > Today's network infrastructure must deliver far , networking processors (NPUs), for networking functions. Now, with the UltraSPARC T2 CMT processor, plus Wind
Sun Microsystems
Original

UltraSPARC ii

Abstract: Sun UltraSparc T1 unidirectional (output only) pins on UltraSPARC-1 connected directly to system. Sun Microsystems, Inc 15 , ^ Business SPA R C Technology M ay 1995 UltraSPARC-1 DATA SHEET In t r o d u c t io n , o n e n t O v e r v i e w In a single chip implementation, the UltraSPARC-1 processor integrates , dynamic branch prediction scheme is implemented in Sun Microsystems, Inc 2 Prelim inary , units in the FPU allows UltraSPARC-1 to issue and execute two float ing-point instructions per cycle
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Z2 150 1AK

Abstract: Sun UltraSparc T2 UltraSPARC-4 module, is present and is used to man age duplicate tags, for efficient data sharing. Sun , . There are five unidirectional (output only) pins on UltraSPARC-! connected directly to system. Sun , Introduction High-Performance 64 Bit RISC Processor The STP1030, UltraSPARC-!, is a high-performance , ) UltraSPARC-! Bus F ig u r e 1. F u n c tio n a l B lo ck D iagram U l t r a S P A R C -I C o m p o n e n t O v e r v i e w In a single chip implementation, the UltraSPARC-! processor integrates the
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Z2 150 1AK Sun UltraSparc T2 UltraSPARC ii AJ17A

Sun UltraSparc T2

Abstract: Sun UltraSparc T1 . Sun Microsystems, Inc 16 Prelim in ary Revision OS - UltraSPARC-4Data Buffer (UDB) STP II W , Prel i m i na r y SPA RC T echrdogy Business STP1080 May 1995 UltraSPARC-1 Data Buffer (U DB) DATA SHEET Introduction The UltraSPARC^ Data Buffer(UDB) consists of two chips that connect UltraSPARC-! and its E-eache to a 144bit data bus. Data Buffer chips move data between the E-eache and , · · · · · Isolates the processor from the system bus Interface to the UltraSPARC-1 Bus Operates at
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Sun UltraSparc T1 sparc v8 spitfire Sun UltraSparc II 1EEE1149

UltraSPARC IIIi

Abstract: UltraSPARC iie ) External ` Cache RAM Memory Interface Unit (MIU) UltraSPARC- I Bu £ Figure 1. F unctional Block , this bus. (3.3V, UPA)"1 Bidirectional radial UltraSPARC-1 Bus signal betw een UltraSPARC-1 and the system. Driven by UltraSPARC-1 to initiate SYSADR transactions to the system. Driven by the sys tem to initiate Coherency, Interrupt or Slave transactions to UltraSPARC-1. Synchronous to the system clock. (3.3 V, UPA) UltraSPARC-1 system address bus arbitration request from up to 3 other UltraSPARC-1 bus
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UltraSPARC IIIi UltraSPARC iie AF5A ultrasparc STP1030A P1030A

instruction set Sun SPARC T3

Abstract: Sun UltraSparc T2 STP1031 Sun Microelectronics July 1997 UltraSPARCâ"¢-!! DATA SHEET Second Generation SPARC , second generation of UltraSPARC pipeline-based products. In addition to using a new process technology , External ' Cache RAM Sun icroelectronics July 1997 This Material Copyrighted By Its Respective , Sun Microelectronics 3 This Material Copyrighted By Its Respective Manufacturer STP1031 , Timing Considerations Section on page 21 for more detail.) Sun icroelectronics July 1997 This
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STP1031LGA instruction set Sun SPARC T3 instruction set Sun SPARC T5 Sun UltraSparc SUN MICROELECTRONICS SPARC v9 architecture BLOCK DIAGRAM 787-P

AE21 ARRAY DIODE

Abstract: AAD20 the primary connection on an UltraSPARC CPU board between the UPA System Bus (including UltraSPARC , master and slave port connection to the high-speed UltraSPARC UPA Interconnect Architecture. The UPA is , busses. · A "Mondo-Vector" Dispatch Unit, or MDU, for delivering Interrupt requests to UltraSparc CPU , U2P in a PCI UltraSPARC system. U2P connects to the System Controller chip and other UPA ports via , UPA is UltraSPARC's packet switched main system bus. In an UltraSPARC system, the UPA can operate up
Sun Microelectronics
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STP2223BGA AE21 ARRAY DIODE AAD20 ac10 stc

diode marking code e26

Abstract: PIN DIAGRAM of IC AD 524 The U2P * chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus (including UltraSPARC Processors and Memory) and a PCI based I/O Subsystem. Its major functions are UPA port , . UPA to PCI Interface Features · Full master and slave port connection to the high-speed UltraSPARC , requests to UltraSparc CPU modules, including support for PCI interrupts from up to six total slots, as , possible configuration of U2P in a PCI UltraSPARC system. U2P connects to the System Controller chip and
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diode marking code e26 PIN DIAGRAM of IC AD 524 M-1298B5

UltraSPARC ii

Abstract: icroelectronics S T P 10 8 1 O c to b e r 1996 UltraSPARC -II Data Buffer (UDB-II) DATA SHEET D e s c r , design Isolates th 9 procQssor from th 9 syslQm bus Interface to the UltraSPARC-11 bus O , hile the other holds d ata going from the U PA to the UltraSPARC. S 6 un M icroelectronics , coherency, by using cache flushes and com pare-and-sw ap. D ata is protected on th e UltraSPARC side u sin g , SUN. Tl has agreed to accept the updated IO specifications. Register to Register Timing
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STP1081 STP1081ABGA
Abstract: UDB-I is a data buffer device used in UltraSPARC-1 system s to connect the CPU and its external SRAM , volt CM OS device. It is an integral part of an UltraSPARC-1 CPU system. In CPU m odule based system s , data delivery to UltraSPARC-1 on a Correctable or Uncorrectable Error. Uncorrectable errors will have , happen. If an ECC error is detected, bad parity is generated for outgoing data to UltraSPARC-1 a n d /o , until UltraSPARC-1 pulls them out. UDB has the "rea l" interrupt registers that are visible to software -
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STP1080A STP1080BGA 256-P

ultrasparc

Abstract: UltraSPARC " -!! Data Buffer (UDB-II) DATA SHEET D e s c r ip t io n The UltraSPARC-II Data , . UDB-II Block Diagram July 1997 S un M icroelectronics 253 UltraSPARC"-11 Data Buffer , from the UltraSPARC-II to the UPA, while the other holds data going from the UPA to the UltraSPARC , UltraSPARC"-!! Data Buffer (UDB-II) Companion Device for 250/300 MHz UltraSPARC-!! Systems Error , UltraSPARC'-IJ Data Buffer (UDB-JI) Companion Device for 250/300 MHz UltraSPARC-11 Systems TABLE 1: ECC Status
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SYSDATAJ59 SYSDATAI32 OOOOOOOO60 1V11V SPARC-11 STP1081ABGA-125

UltraSPARC ii

Abstract: Sun UltraSparc T1 HighrPer)ormance, 250 MHz, 64-Bit RISC P rocessor Data S he e t F e b ru a ry 1997 STP1031 Sun , in the same group. UltraSPARC-II is part of a second generation of UltraSPARC pipeline-based products , developers. At the same time, it provides software compatibility with existing UltraSPARC-1 based systems , (BGA) · Power Managem ent · Multiple Clocking Modes - UltraSPARC ! C om patible · Multiple Outstanding , single chip implementation, UltraSPARC- II integrates the following components (see Figure D
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g31 m7 te
Abstract: PCI Interface D e s c r ip t io n The U2P * chip is the prim ary connection on an UltraSPARC CPU board betw een the UPA System Bus (including UltraSPARC Processors and Memory) and a PCI based 1 /O , to the high-speed UltraSPARC UPA Interconnect Architecture. The UPA is a split ad dress/d ata , UltraSparc CPU m odules, including support for PCI interrupts from up to six total slots, as w ell as , U2P in a PCI UltraSPARC system. U2P connects to the System Controller chip and other UPA ports via -
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2223B

PSA B20 0110

Abstract: UltraSPARC ii . Clocks, Reset, etc. Observability. JTAG, etc. Figure 3. Main UltraSPARC-41 Interfaces Cache Coherence , 219 UltraSPARC" -Il Second Generation SPARC v9 64-Bit Microprocessor With VIS · Shared Clean (S , Store hit, atomic hit to Shared Clean line i) A Shared Clean line is victimized by UltraSPARC. I-Cache , other interrupters. July 1997 S un M icroelectronics 223 UltraSPARC""-11 Second , d eliver a 64 byte interrupt packet to the destination (see A S I Registers definition in UltraSPARC
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PSA B20 0110

286 dram schematic

Abstract: dps 298 cp 2 Ecache FEPS RIC SlavIO UDB UltraSPARC-1 U2S XB1 Description STP Part No. STP2024QFP STP5110 N/A N/A STP2002QFP STP2210QFP STP2001QFP STP1 080BGA STP1 030BGA STP2220BGA STP223QSOP Audio Controller UltraSPARC , /O Controller Reset/lnterrupt/Clock Controller Slave System I/O Controller UltraSPARC ! Data Butter , follows: UltraSPARC Modules (STPSliO) The processors are essentially isolated from the rest of the system , ) Coherent Read Request tO tl t2 t3 t4 t5 t6 t7 t8 t9 S un M icroelectronics 58
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286 dram schematic dps 298 cp 2 dps 298 cp FRS 8C - 05 9V DC 85A9 k2 dsc hen ng STP2202BG 128MB

UltraSPARC-III

Abstract: specification refer to PCI Local Bus Specification Revision 2.1, June 1 , 1995. 335 UltraSPARC*-IIi APB , APB. Benefits of UltraSPARC-lli with the Advanced PCI Bridge Used with UltraSPARC-11/', APB , 's ability to accept 5 V secondary bus devices allows 5 V commodity devices to be used with UltraSPARC-11/. , icroelectronics UltraSPARC" -Hi APB Advanced PCI Bridge, 66-MHz-Primary-to-33-MHz-Secondary Data Path , a Retried or Disconnected write). July 1997 Sun M ic ro elec tro n ics 343 U
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UltraSPARC-III 66-MH SME2411 SPARC-11/
Abstract: Controller STP2024QFP CPU Module UltraSPARC Module STP5110 DTAG Dual Tag Synchronous SRAM , Slave System I/O Controller STP2001QFP UDB UltraSPARC-1 Data Buffer STP1080BGA STP1030BGA UltraSPARC-1 High Performance 64-Bit RISC Processor U2S UPA-to-SBus Interface STP2220BGA XB1 , Typical System Configuration) typically interface with the DSC as follows: UltraSPARC M odules (STP5110 , the â'DSC Userâ'™s Manualâ'. These registers are accessed through the EBus. Sun M ic ro e le -
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STP2202ABGA STP2202BGA PINA02Y BOZ24Y BOZ24L BOZ24N
Abstract: branch) can be issued in the same group. UltraSPARC-II is part of a second generation of UltraSPARC , existing UltraSPARC-1 based systems. UltraSPARC-II also im plem ents the SPARC-V9 Prefetch instruction , icroprocessor W ith VIS STP1031 O verview o f UltraSPARC-11 Interface The m ain interfaces to and from , hared Clean line P_R DO_REQ SOAK i) A Shared Clean line is victim ized by UltraSPARC. P , y S_C RAB P_R DO_REQ SOAK UltraSPARC-11 as a Bus Port The UltraSPARC Port Architecture -
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1031LG

cmd1011

Abstract: STP2024QFP Audio Controller UltraSPARC Module Dual Tag Synchronous SRAM 2nd Level High Speed Data and Tag Cache , ) typically interface with the DSC as follows: UltraSPARC Modules (STP5110) The processors are essentially , registers of the DSC. 2 Sun Microsystems, Inc June 1998 DSC Dual Processor System Controller , could replace the U2S and SlavIO, respectively, if the system utilizes PCI buses. June 1998 Sun , 8 Serial Port, Mouse, Floppy Figure 1. Typical System Configuration 4 Sun Microsystems
Sun Microsystems
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cmd1011 sun sparc pinout

SPARC v9 architecture BLOCK DIAGRAM

Abstract: UltraSPARC ii a second generation of UltraSPARC pipeline-based products. In addition to using a new process , Clean line is victimized by UltraSPARC. P_RDS_REQ S_RBU or S_RBS Write miss. or I-Cache , UltraSPARC-II as a Bus Port The UltraSPARC Port Architecture (UPA) defines protocols for a family of tightly , UltraSPARC Port Architecture (UPA). (For more information, refer to the manual entitled UPA Interconnect , ASI Registers definition in UltraSPARC User's Manual). · P_NCRD_REQ (Noncached Read): Used when a
Sun Microelectronics
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Sinak h30 sparc sparc v7 1997AD32
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