500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : 7/0.2 LAP SCRN MED SINGLE ROUND 100 Supplier : ESCABLE Manufacturer : Chip1Stop Stock : 32 Best Price : $17.2000 Price Each : $25.7000
Shipping cost not included. Currency conversions are estimated. 

Single Root I/O Virtualization

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: introduced the Single Root I/O Virtualization Specification (SR-IOV) to address these performance issues by , Single Root I/O Virtualization specification System under test TCP offload engine Universal Pass , environment. The trend towards server virtualization has advanced the market offerings and role for I/O , on consolidated hardware. Virtualization also provides the user a rich set of features such as I/O , and 10G network controllers are well-suited for I/O virtualization and offer real-time flexibility in Broadcom
Original
SR-IOV-WP100-R bcm5709 sr-iov BCM5709 Broadcom 5709 vmxnet netxtreme BCM5709C
Abstract: bus. â'¢ Single root I/O virtualization (SR-IOV) support for faster performance in virtualized , ) technology as well as industry-standard I/O virtualization technologies. SR-IOV enhances I/O performance in , eliminates potential I/O bottlenecks in todayâ'™s powerful multiprocessor, multicore servers. In addition , need excellent I/O performance to service growing numbers of virtual machines (VMs). The ability to , all ports. With support for over 1.2 million I/O transactions per second, QLogic adapters deliver the QLogic
Original
Abstract: 10GbE Network Adapter Single Root I/O Virtualization (SR-IOV) With OneConnect support for SR-IOV , corruption. Virtualized I/O New multi-core servers are enabling much higher virtualization ratios , for network consolidation n Maximizes I/O bandwidth with high-performance 10GbE ports n , vEngineâ"¢ technology n SR-IOV support improves I/O performance with virtual server deployments n , balancing (ALB), teaming support, VMW NetQueue v2 and IEEE 802.3ad, VT-d / IOMMU support I/O Emulex
Original
11102-N 11102-NM 10GBASE-SR 11102-NX 10GBASE-CR 11102-NT
Abstract: overall server performance. These technologies are Virtual Machine Device Queues (VMDq) and Single Root I , per port) Provides an implementation of the PCI-SIG standard for I/O Virtualization. The physical , for network I/O. Simply put, GbE cannot scale up to meet the demands of these new servers. 10GbE is a , any virtualized data center. Data centers are demanding flexible and scalable I/O solutions to meet , platforms. The new Intel platforms drive an unprecedented need for additional I/O support. With the Intel Intel
Original
X520-T2 10GBASE-T e10g42bt NAS 1831 connector RJ45 CAT-6 RJ-45 0810/SWU 318349-004US
Abstract: Single Root I/O Virtualization and , availability. Virtualization also provides the user a rich set of features, I/O sharing, consolidation , architecture. Today's virtualization architecture includes VM with device driver, I/O stack and applications, layered on top of a Virtualization layer that includes device emulation, I/O stack and physical device , to the single threaded nature of hypervisor in processing I/O and duplicate I/O copies in the Broadcom
Original
BCM577xx Virtualization Broadcom shell Dynamic traffic light controller Virtualization-WP100-R windows7
Abstract: ) networking devices to the chipset and processors, which help · PCI-SIG Single Root I/O Virtualization , implementation of the PCI-SIG standard for I/O Virtualization. The physical P configuration of each port is , calable PCI Express* interface provides S dedicated I/O bandwidth for I/O-intensive networking , platform, thereby improving application response times. The I/O technologies on a multi-core platform , to 8. It now also supports multicast and broadcast data on a the I/O overhead in a virtualized Intel
Original
e1g44et E1G44ETBLK E1G42EF intel e1g42et E1G42ETBLK intel 82576 0509/TAR/OCG/PDF/XX 320116-002US
Abstract: . 254 5.29.1 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d , . 66 2.22 General Purpose I/O Signals , . 77 3.2 Output and I/O Signals Planes and States , . 159 General Purpose I/O (D31:F0 , . 311 9.3 I/O Map Intel
Original
Abstract: the Single Root I/O Virtualization and Sharing (SR-IOV) specification. The PCI-SIG Single Root I/O , . Ethernet or SAS link). The virtualization software no longer has to multiplex the I/O requests into a , .23 5.2 I/O Operations and Activities , Physical Function driver and the Linux* Virtual Function driver. 1.1 SR-IOV Overview Current I/O , directly connected to the I/O device so that the main data movement can occur without Hypervisor -
Original
E1000 intel gigabit driver intel igb 82576 E1000 82576 Intel 8275 8275 intel
Abstract: â'" Integrated I/O APIC capability with 24 interrupts â'" Supports Processor System Bus interrupt , . 115 4.2.1.9 I/O Cycles , . 118 4.3.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words . 118 4.3.4 , I/O Unit and Watchdog Timer (SIW) (B0:D31:F0) . 181 4.13.1 , . 182 4.13.3.4 I/O Read and Write Cycles Intel
Original
327879-001US PEC 4179 DIODE LK100
Abstract: â'" Integrated I/O APIC capability with 24 interrupts â'" Supports Processor System Bus interrupt , . 116 4.2.1.9 I/O Cycles , . 119 4.3.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words . 119 4.3.4 , I/O Unit and Watchdog Timer (SIW) (B0:D31:F0) . 182 4.13.1 , . 183 4.13.3.4 I/O Read and Write Cycles Intel
Original
842 317 SO8 327879-002US
Abstract: hard IP also provides added functionality, which helps support emerging features such as Single Root I , pin migration compatibility, refer to the I/O Management chapter in volume 2 of the Quartus II , prevent core and I/O noise from coupling into the transceivers, thereby ensuring optimal signal integrity , lists the transceiver PMA features. Figure 1. Stratix V GT, GX, and GS Device Chip View (1) I/O , Blocks DSP Blocks DSP Blocks DSP Blocks PMA (2) I/O, LVDS, and Memory Interface Altera
Original
SV51001-3 100GBASE-R 5SGXBB HF35-F1152 interlaken 40G/100G 40G/100G/400G
Abstract: functionality, which helps support emerging features such as Single Root I/O Virtualization (SR-IOV) or , verifying the pin migration compatibility, refer to the I/O Management chapter in volume 2 of the Quartus , I/O noise from coupling into the transceivers, thereby ensuring optimal signal integrity. The , PCS I/O, LVDS, and Memory Interface PMA PMA PMA PMA (1) I/O, LVDS, and Memory Interface , from the top. External Memory and GPIO Each Stratix V I/O block has a hard FIFO that improves the Altera
Original
SV51001
Abstract: , which helps support emerging features such as Single Root I/O Virtualization (SR-IOV) or optional , verifying the pin migration compatibility, refer to the I/O Management chapter in volume 2 of the Quartus , figure below. The transceivers are isolated from the rest of the chip to prevent core and I/O noise from , PCS I/O, LVDS, and Memory Interface PCS PCS PCS PMA PMA PMA PMA (1) I/O, LVDS, and , External Memory and GPIO 13 External Memory and GPIO Each Stratix V I/O block has a hard FIFO that Altera
Original
Abstract: ECRC features â'¢ Multiple-function and single root I/O virtualization (SR-IOV) support enabled , with 1.4 Tb/s of I/O bandwidth, 980K logic cell capacity, and 4.7 TMAC/s DSP, while consuming 50% less , Gen3 Memory Interface 800 Mb/s 1,866 Mb/s 1,866 Mb/s 400 500 1,000 I/O Voltage , Flip-Chip Peak DSP Performance(2) Transceivers I/O Pins Notes: 1. 2. Additional memory , ) PCIe (5) GTPs Analog Mixed Signal (AMS) Total I/O Banks(6) Max User I/O(7) (4 Xilinx
Original
XQ7A200T DS185
Abstract: Single Root I/O Virtualization (SR-IOV) or optional protocol extensions. In addition, the Stratix V , Maximum User I/O: (General Purpose, LVDS, Transceiver) (2), (3) 40×40 mm2 NF40 - F1517 40×40 mm2 , I/O 900 900 LVDS (1) 225 225 Logic Elements Registers Fractional PLLs Memory , . They are isolated from the rest of the chip to prevent core and I/O noise from coupling into the , Hardcopy Block Transceiver Channels Per Channel: Standard PCS, 10G PCS, Interlaken PCS I/O, LVDS Altera
Original
QSFP 40G transceiver 40GBASE-R pcie gen3 QSFP optical active cable gearbox CPRI multi rate SV51001-1
Abstract: Root I/O Virtualization (SR-IOV) or optional protocol extensions. In addition, the Stratix V device , Figure 1­1. They are isolated from the rest of the chip to prevent core and I/O noise from coupling into , 1­1. Stratix V GT/GX/GS Device Chip View (Note 1) I/O, LVDS, and Memory Interface Embedded , DSP Blocks DSP Blocks DSP Blocks (2) I/O, LVDS, and Memory Interface Notes to Figure , Memory and General Purpose I/O Stratix V devices offer high I/O bandwidth with up to seven 72-bit DDR3 Altera
Original
5sgxa3 KF40-F1517 eye-q 400 NF40-F1517 gf35 KF35-F1152
Abstract: ECRC features Multiple-function and single root I/O virtualization (SR-IOV) support enabled through , I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power , Serial Bandwidth (Full Duplex) PCIe Interface Memory Interface I/O Pins I/O Voltage Package Options Notes , ) (4) PCIe (5) GTPs XADC Blocks Total I/O Banks(6) Max User I/O(7) XC7A20SL XC7A35SL , Combinations and Maximum I/Os Package(1) Size (mm) Ball Pitch (mm) CPG236 10 x 10 0.5 I/O Device GTP HR (2 Xilinx
Original
XC7VX485T XC7A35SLT Virtex-7 XC7VX485T FPGA XC7VH870T CSG325 XC7A75SLT DS180
Abstract: ECRC features â'¢ Multiple-function and single root I/O virtualization (SR-IOV) support enabled , unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and , Interface Memory Interface I/O Pins I/O Voltage Package Options x4 Gen2 x8 Gen2 x8 Gen3 1 , ) 36Kb Total I/O Banks(6) Max User I/O(7) XC7A35T 33,280 5,200 400 90 100 50 , 0.5 0.8 0.8 1.0 0.8 1.0 1.0 1.0 1.0 1.0 Ball Pitch (mm) I/O Device Xilinx
Original
Abstract: ECRC features â'¢ Multiple-function and single root I/O virtualization (SR-IOV) support enabled , unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and , High-Performance Flip-Chip Highest Performance Flip-Chip Memory Interface I/O Pins I/O Voltage Package , ) 36 Kb Total I/O Banks(6) Max User I/O(7) XC7A15T 16,640 2,600 200 45 50 , 0.5 0.8 0.8 1.0 0.8 1.0 1.0 1.0 1.0 1.0 Ball Pitch (mm) I/O Device Xilinx
Original
Abstract: ECRC features Multiple-function and single root I/O virtualization (SR-IOV) support enabled through , unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and , Speed Peak Serial Bandwidth (Full Duplex) PCIe Interface Memory Interface I/O Pins I/O Voltage Package , ,140 18,540 Clock Mgmt Tiles (CMTs) (4) PCIe (5) GTPs XADC Blocks Total I/O Banks(6) Max User I/O(7) XC7A100T XC7A200T XC7A350T 101,440 215,360 360,000 6 10 12 1 1 1 8 16 Xilinx
Original
XC7K160T XC7K160T- XC7VX690T ffg17 DSP48E1 Artix-7
Showing first 20 results.