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74SSTL16847DGGRE4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 visit Texas Instruments
74SSTL16847DGGRG4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 visit Texas Instruments
SN74SSTL16847DGGR Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 visit Texas Instruments
74SSTL16857DGGRG4 Texas Instruments SSTL SERIES, 14-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48 visit Texas Instruments
74SSTL16837ADGGRE4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 visit Texas Instruments
SN74SSTL16837DGGR Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, SSOP-64 visit Texas Instruments

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SSTL-135

Catalog Datasheet MFG & Type PDF Document Tags

HSUL-12

Abstract: SSTL-12 '" LVPECL Video graphics and clock distribution â'" SSTL-15 DDR3 SDRAM JESD79-3D SSTL-135 , SDRAM â'" Differential SSTL-15 DDR3 SDRAM JESD79-3D Differential SSTL-135 DDR3L SDRAM , -15 VCCPD 1.5 2.5 0.75 SSTL-135 VCCPD 1.35 2.5 0.675 SSTL-125 VCCPD 1.25 , Differential SSTL-15 VCCPD 1.5 2.5 â'" Differential SSTL-135 VCCPD 1.35 2.5 â , as SSTL-12, SSTL-15, SSTL-125, SSTL-135, and HSUL-12. High-Speed Differential I/O with DPA Support
Altera
Original
SSTL12 SV51006
Abstract: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/DDR4 Switch Features Description ÃÃ bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 14 This 14-bit DDR3/DDR4 switch is designed for 1.35V/ 1.5V/ 1.8V supply voltage, POD_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for DDR3 or DDR4 memory bus with speed up to 5Gbps. It supports DDR3 800 , ÃÃ DDR3/DDR4 Memory Bus System ÃÃ POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 ÃÃ Pericom Semiconductor
Original
2133M CBTW28DD14 PD-2103 MO-220 PD-2102
Abstract: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/DDR4 Switch Features Description ÃÃ bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 14 This 14-bit DDR3/DDR4 switch is designed for 1.35V/ 1.5V/ 1.8V supply voltage, POD_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for DDR3 or DDR4 memory bus with speed up to 5Gbps. It supports DDR3 800 , ÃÃ DDR3/DDR4 Memory Bus System ÃÃ POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 ÃÃ Pericom Semiconductor
Original
PI2DDR3212ZLE PI2DDR3212NCE
Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSTL15_R, SSTL135_R , _15_DCI, SSTL135_DCI, DIFF_SSTL18_II_DCI, DIFF_SSTL_15_DCI, DIFF_ SSTL135_DCI . . . . . . . . . . . . . . . . . . . . , , SSTL15_T_DCI, SSTL135_T_DCI, DIFF_SSTL18_II_T_DCI, DIFF_SSTL15_T_DCI, DIFF_ SSTL135_T_DCI . . . . . . . . . . , , SSTL135, DIFF_SSTL18_II, DIFF_SSTL15, DIFF_SSTL135 . . . . . . . . 49 52 54 55 57 58 58 58 58 , , DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI75 SSTL18, SSTL15, SSTL135, SSTL12 . . . . . . . . . . . . . . . . . . . . . Xilinx
Original
UG471

SSTL-135

Abstract: ELPIDA DDR3 , SSTL_135 ©Elpida Memory, Inc. 2002-2009 Die Rev. ECT-TS-1984 Apr. 2009 Part Number Decoder , , SSTL_135 : In case of unbuffered Non-ECC DIMM. Both of "A" and "0" mean without thermal sensor
Elpida Memory
Original
ELPIDA DDR3 ELPIDA mobile DDR ddr2 ram ELPIDA ddr3 so dimm 204 pin FBGA DDR3 x32 DDR3-1600J DDR3-1600K PC1600 166MH 100MH 133MH

HSUL-12

Abstract: jesd79-3d -15 Class I and II DDR3 SDRAM SSTL-15 DDR3 SDRAM SSTL-135 DDR3L SDRAM SSTL-125 DDR3U , interfaces Differential SSTL-15 DDR3 SDRAM Differential SSTL-135 DDR3L SDRAM Differential SSTL , (3) 1.5 2.5 0.75 0.75 SSTL-15 JESD79-3D (3) 1.5 2.5 0.75 (4) SSTL-135 , SSTL-135 - (3) 1.35 2.5 - (4) Differential SSTL-125 - (3) 1.25 2.5 , -12, SSTL-15, SSTL-125, SSTL-135, and HSUL-12. High-Speed Differential I/O with DPA Support Stratix V
Altera
Original
SSTL-18 lpddr2 lpddr2 datasheet DDR3U Datasheet LPDDR2 SDRAM DDR3L lpddr2 DQ calibration HSTL-15
Abstract: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 6 â'" 25 July 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and , ® 2.5 GHz bandwidth Low ON insertion loss Low crosstalk High OFF isolation POD_12, SSTL_12, SSTL_135 , _12 1.2 V Pseudo Open Drain interface SSTL_12 Stub Series Terminated Logic for 1.2 V SSTL_135 NXP Semiconductors
Original
TFBGA48
Abstract: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 5 â'" 28 May 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and , ® 2.5 GHz bandwidth Low ON insertion loss Low crosstalk High OFF isolation POD_12, SSTL_12, SSTL_135 , interface SSTL_12 Stub Series Terminated Logic for 1.2 V SSTL_135 Stub Series Terminated Logic NXP Semiconductors
Original

lpddr2 datasheet

Abstract: lpddr2 -15 Class I and II DDR3 SDRAM SSTL-15 DDR3 SDRAM SSTL-135 DDR3L SDRAM SSTL-125 DDR3U , interfaces Differential SSTL-15 DDR3 SDRAM Differential SSTL-135 DDR3L SDRAM Differential SSTL , (3) 1.5 2.5 0.75 0.75 SSTL-15 JESD79-3D (3) 1.5 2.5 0.75 (4) SSTL-135 , SSTL-135 - (3) 1.35 2.5 - (4) Differential SSTL-125 - (3) 1.25 2.5 , -12, SSTL-15, SSTL-125, SSTL-135, and HSUL-12. High-Speed Differential I/O with DPA Support Stratix V
Altera
Original
UniPHY lpddr2 lpddr2 phy Dual LPDDR2 Datasheet LPDDR2 lpddr2 pcb design lpddr2 pcb layout
Abstract: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 4 â'" 12 August 2013 Product data sheet 1. General description This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL , ® 2.5 GHz bandwidth Low ON insertion loss Low crosstalk High OFF isolation POD_12, SSTL_12, SSTL_135 , interface SSTL_12 Stub Series Terminated Logic for 1.2 V SSTL_135 Stub Series Terminated Logic NXP Semiconductors
Original
Abstract: SSTL15_DCI_S SSTL15_T_DCI_S SSTL135_S SSTL135_DCI_S SSTL135_T_DCI_S SSTL12_S SSTL12_DCI_S SSTL12_T_DCI_S , SSTL135_F SSTL135_DCI_F SSTL135_T_DCI_F SSTL12_F SSTL12_DCI_F SSTL12_T_DCI_F DIFF_SSTL18_I_F , , 12 SSTL135_S SSTL135_II_S SSTL15_S SSTL15_II_S SSTL18_I_S SSTL18_II_S DIFF_SSTL135_S DIFF_SSTL135_II_S DIFF_SSTL15_S DIFF_SSTL15_II_S DIFF_SSTL18_I_S DIFF_SSTL18_II_S SSTL135_F SSTL135_II_F SSTL15_F , HSTL I(8) DIFF HSTL II(8) SSTL135 DIFF SSTL135 SSTL18 I SSTL18 II DIFF SSTL18 I DIFF SSTL18 II SSTL15 Lattice Semiconductor
Original
DS1044
Abstract: SSTL15_T_DCI_S SSTL135_S SSTL135_DCI_S SSTL135_T_DCI_S SSTL12_S SSTL12_DCI_S SSTL12_T_DCI_S DIFF_SSTL18_I_S , SSTL15_T_DCI_F SSTL135_F SSTL135_DCI_F SSTL135_T_DCI_F SSTL12_F SSTL12_DCI_F SSTL12_T_DCI_F DIFF_SSTL18_I_F , (HR) Switching Characteristics (Cont'd) TIOPI I/O Standard -3 SSTL135_F SSTL135_II_F SSTL15_F , LVCMOS12, Slow, 12 mA(1) LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 8 mA LVCMOS12, Fast, 12 SSTL135_S SSTL135_II_S SSTL15_S SSTL15_II_S SSTL18_I_S SSTL18_II_S DIFF_SSTL135_S DIFF_SSTL135_II_S DIFF_SSTL15_S Lattice Semiconductor
Original
TN1260 TN1261 TN1262 TN1263 TN1264 TN1265
Abstract: II SSTL-18 Class I and II SSTL-15 Class I and II SSTL-15 SSTL-135 SSTL-125 SSTL-12 HSTL-18 Class I , Differential HSTL-15 Class I and II Differential HSTL-12 Class I and II Differential SSTL-15 Differential SSTL-135 , -15 Class I SSTL-15 Class II SSTL-15 SSTL-135 SSTL-125 SSTL-12 HSTL-18 Class I HSTL-18 Class II HSTL , SSTL-135 Differential SSTL-125 Differential SSTL-12 Differential HSUL-12 LVDS (6), (7) RSDS (6), (7 , -12, SSTL-15, SSTL-125, SSTL-135, and HSUL-12. High-Speed Differential I/O with DPA Support Stratix V Lattice Semiconductor
Original
TN1266 TN1267

FFG676 xc7k325t

Abstract: xc7k325t SSTL135_S SSTL135_DCI_S SSTL135_T_DCI_S SSTL12_S SSTL12_DCI_S SSTL12_T_DCI_S DIFF_SSTL18_I_S , SSTL18_II_F SSTL18_I_DCI_F SSTL18_II_DCI_F SSTL18_II_T_DCI_F SSTL15_F SSTL15_DCI_F SSTL15_T_DCI_F SSTL135_F SSTL135_DCI_F SSTL135_T_DCI_F SSTL12_F SSTL12_DCI_F SSTL12_T_DCI_F DIFF_SSTL18_I_F DIFF_SSTL18_II_F , mA LVCMOS12, Fast, 12 SSTL135_S SSTL15_S SSTL18_I_S SSTL18_II_S DIFF_SSTL135_S DIFF_SSTL15_S DIFF_SSTL18_I_S DIFF_SSTL18_II_S SSTL135_F SSTL15_F SSTL18_I_F SSTL18_II_F DIFF_SSTL135_F DIFF_SSTL15_F
Xilinx
Original
FFG676 xc7k325t xc7k325t XC7K325T specification XC7K160T ffg676 xc7k160t XC7K410T DS182

XC7K160T

Abstract: XC7K70T 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-135 1.283 1.35 1.418 , '" VREF â'" 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 16 â'"16 SSTL-135 â'" VREF â , (AC) â'" VREF) 2(VREF â'" VIL(AC) VCCIO/2 â'" 0.15 â'" VCCIO/2 + 0.15 SSTL-135
Xilinx
Original
XC7K70T XC7K480T XC7K420T XC7K355T XC7K325T user guide FBG676

hf1932

Abstract: HSUL-12 '"13.00 SSTL135_R â'"0.300 VREF â'" 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 â'" 0.150 VCCO/2 + 0.150 , VPREF + 0.100 VCCO_DDR + 0.300 VCCO_DDR/2 â'" 0.175 VCCO_DDR/2 + 0.175 13.0 â'"13.0 DDR SSTL135 â , % VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.50 â'"0.50 SSTL135 â
Altera
Original
hf1932 rf1517 DIODE CQ 618 lvds cable 20 pins SV51006-1

XC7V585T

Abstract: ds183 virtex7 _18 HSTL_II HSTL_II_18 HSUL_12 LVCMOS12 LVCMOS15 LVCMOS18 LVCMOS25 LVCMOS33 LVTTL MOBILE_DDR PCI33_3 SSTL135 SSTL135_R SSTL15 SSTL15_R SSTL18_I SSTL18_II Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant , DDR SSTL18_I DDR SSTL15 DDR SSTL135 DDR HSUL_12 Notes: 1. ­0.300 VPREF ­ 0.125 VPREF + 0.125
Xilinx
Original
XC7V585T ds183 virtex7 XC7V2000T XC7VX485T XC7v SPARTAN 6 readback DS183
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