NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Class I and II DDR3 SDRAM SSTL-15 SSTL-15 DDR3 SDRAM SSTL-135 SSTL-135 DDR3L SDRAM SSTL-125 DDR3U , SSTL-125 DDR3U SDRAM Differential SSTL-12 SSTL-12 RLDRAM III Differential HSUL-12 HSUL-12 LPDDR2 SDRAM , 0.75 (4) SSTL-135 SSTL-135 - (3) 1.35 2.5 0.675 (4) SSTL-125 - (3) 1.25 , ) Differential SSTL-135 SSTL-135 - (3) 1.35 2.5 - (4) Differential SSTL-125 - (3) 1.25 , , SSTL-15 SSTL-15, SSTL-125, SSTL-135 SSTL-135, and HSUL-12 HSUL-12. High-Speed Differential I/O with DPA Support Stratix V ... | Original |
34 pages, |
Datasheet LPDDR2 LPDDR2 pin information LPDDR2 SDRAM mini-lvds source driver resistor 240 5sgx SSTL-125 SSTL135 SSTL-18 SSTL-15 SSTL-12 lpddr2 DQ calibration DDR3L datasheet abstract |
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| Abstract: Class I and II DDR3 SDRAM SSTL-15 SSTL-15 DDR3 SDRAM SSTL-135 SSTL-135 DDR3L SDRAM SSTL-125 DDR3U , SSTL-125 DDR3U SDRAM Differential SSTL-12 SSTL-12 RLDRAM III Differential HSUL-12 HSUL-12 LPDDR2 SDRAM , 0.75 (4) SSTL-135 SSTL-135 - (3) 1.35 2.5 0.675 (4) SSTL-125 - (3) 1.25 , ) Differential SSTL-135 SSTL-135 - (3) 1.35 2.5 - (4) Differential SSTL-125 - (3) 1.25 , , SSTL-15 SSTL-15, SSTL-125, SSTL-135 SSTL-135, and HSUL-12 HSUL-12. High-Speed Differential I/O with DPA Support Stratix V ... | Original |
96 pages, |
QDR pcb layout UniPHY sstl15 SSTL-18 SSTL-15 lpddr2 pcb design lpddr2 pcb layout DDR3U DDR3L Datasheet LPDDR2 Dual LPDDR2 HSUL-12 lpddr2 DQ calibration lpddr2 phy datasheet abstract |
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| Abstract: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.8 11.1 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective ... | Original |
70 pages, |
RF40-F1517 QSFP 40G transceiver KF40-F1517 KF35-F1152 HF35-F1152 H40-H1517 10G SFP SV53001-2 datasheet abstract |
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| Abstract: Stratix V Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V1-1.0 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service ... | Original |
300 pages, |
lpddr2 pcb layout Dual LPDDR2 DDR3U UniPHY lpddr2 SV51005-1 SV51012-1 "Stratix IV" Package layout footprint DDR3L lpddr2 tutorial Datasheet LPDDR2 SDRAM lpddr2 DQ calibration lpddr2 phy lpddr2 datasheet datasheet abstract |
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| Abstract: 349-333 Differential 1.2-V HSUL SSTL-15 SSTL-15 SSTL-135 SSTL-135 SSTL-125 SSTL-12 SSTL-12" 1.2-V HSUL ... | Original |
30 pages, |
traffic lights project SSTL-15 SSTL-13 Plug-In Upgrade c 3807 altddio_in 34743 vhdl code for traffic light control RN-01058-1 RN-01058-1 abstract |
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| Abstract: 107-1434 1.2-V HSUL SSTL-15 SSTL-15 SSTL-135 SSTL-135 SSTL-125 SSTL-12 SSTL-12" Remove the assignment. ... | Original |
31 pages, |
traffic light controller vhdl coding SSTL-15 receiver altLVDS C101 vhdl code for traffic light control RN-01056-1 RN-01056-1 abstract |
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| Abstract: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 © July 2010 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other cou ... | Original |
503 pages, |
verilog code voltage regulator Chapter 3 Synchronization verilog code 8 bit LFSR SFP sgmii altera SFP LVDS altera jesd79-3d Datasheet LPDDR2 SDRAM gearbox rev QSFP CONNECTOR verilog code for max1619 WD 969 lpddr2 DQ calibration datasheet abstract |
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| Abstract: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.1 © January 2011 Copyright © 2011Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other ... | Original |
516 pages, |
Altera Cyclone III lpddr2 tutorial M20K SFP sgmii altera 10G SFP pcie gen3 QSFP CONNECTOR verilog code 8 bit LFSR in scrambler verilog code 16 bit LFSR UniPHY lpddr2 DDR3L SV51005-1 KF40-F1517 datasheet abstract |
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| Abstract: April 2007 HYS72T1G042ER HYS72T1G042ER5B 240-Pin Dual Die Registered DDR2 SDRAM Modules RDIMM SDRAM RoHS Compliant Internet Data Sheet Rev. 1.0 Internet Data Sheet HYS72T1G042ER HYS72T1G042ER5B Registerd DDR2 SDRAM Module HYS72T1G042ER HYS72T1G042ER5B Revision History: 2007-04, Rev. 1.0 Page Subjects (major changes since last revision) All Adapted internet edition All Final document We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing ... | Original |
31 pages, |
HYS72T1G042ER HYB18T2G402BF DDR2-400B DDR2 SDRAM component data sheet 1024M HYS72T1G042ER abstract |
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| Abstract: December 2006 HYS72T512341HHP HYS72T512341HHP[3.7/5]B HYS72T512341HJP HYS72T512341HJP[3.7/5]B HYS72T512341HKP HYS72T512341HKP[3.7/5]B 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RoHs Compliant Products Internet Data Sheet Rev. 1.0 Internet Data Sheet HYS72T512341H HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules HYS72T512341HHP HYS72T512341HHP[3.7/5]B, HYS72T512341HJP HYS72T512341HJP[3.7/5]B, HYS72T512341HKP HYS72T512341HKP[3.7/5]B Revision History: 2006-12, Rev. 1.0 Page Subjects (major changes since last revision) All Qimonda update Al ... | Original |
32 pages, |
PC2-4200P-444-12-ZZ HYS72T512341HHP HYS672T512341HJP- qimonda PC2-4200P-444 HYS72T512341HJP HYS72T512341HKP HYS72T512341HHP abstract |
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| Abstract: GS30 0.15-um CMOS Standard Cell/Gate Array High-Value ASIC u 0.15-um Leff process (0.18-um drawn) with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O u 4 and 5 levels of metal u 6 million random logic gates plus 6 million equivalent gates in TImeBuilderTM modules and memory u Power supply: 1.1/1.4/1.8 V cores I/Os: 1.8/2.5/2.75/3.3 V (selected combinations), 5 V-tolerant, failsafe u Power dissipation: 0.018 uW/MHz/gate for 1.8 V core u ... | Original |
22 pages, |
NECV850 S8P20 serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM clock tree balancing vhdl code for 4 channel dma controller NEC-V850 datasheet of BGA Staggered pins datasheet abstract |
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| Abstract: GS30 0.15-um CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or org ... | Original |
24 pages, |
vhdl code for watchdog timer of ATM verilog code for 16 bit risc processor Sun Enterprise 250 static SRAM single-port ARM dual port SRAM compiler VHDL CODE FOR HDLC controller datasheet abstract |
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| Abstract: GS30 0.15-um CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or o ... | Original |
24 pages, |
datasheet abstract |
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| Abstract: 1. DC and Switching Characteristics for Stratix V Devices SV53001-1 SV53001-1.0 Electrical Characteristics This chapter covers the electrical and switching characteristics for Stratix ® V devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This chapter also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. f ... | Original |
30 pages, |
SV53001-1 SSTL-18 SSTL-15 M20K HSUL-12 SV53001-1 abstract |
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