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Part Manufacturer Description Datasheet BUY
ISL28113SOT23EVAL1Z Intersil Corporation Single General Purpose Micropower, RRIO Operational Amplifier; Package: Eval Board visit Intersil
ISL28114SOT23EVAL1Z Intersil Corporation Single General Purpose Micropower, RRIO Operational Amplifiers; Package: Eval Board visit Intersil
LMH6704MF Texas Instruments 1 CHANNEL, VIDEO AMPLIFIER, PDSO6, SOT23, 6-PIN visit Texas Instruments
LM8365BALMFX27 Texas Instruments 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, SOT23-5 visit Texas Instruments

SOT23 Y0

Catalog Datasheet MFG & Type PDF Document Tags

SN74AUC1G19DBVR

Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK
Texas Instruments
Original
SN74AUC1G19DBVR SN74AUC1G19 SCES626D A114-A A115-A

SN74AUC1G19DBVR

Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK
Texas Instruments
Original

SN74AUC1G19DBVR

Abstract: A115-A (TOP VIEW) A 1 1 6 Y0 GND A 2 5 VCC E 3 4 Y1 GND 2 5 VCC E 3 4 A 1 6 Y0 GND 2 5 VCC E Y0 6 3 4 Y1 Y1 DRY PACKAGE (TOP VIEW) Y0 EW I GND 2 V5 VCC E Y1 3 4 EPR A 1 6 YZP PACKAGE (BOTTOM VIEW) E 3 4 Y1 GND 2 5 VCC A 1 6 Y0 See mechanical drawings for , -of-2 decoder/demultiplexer. This device buffers the data on input A and passes it to the outputs Y0 (true) and
Texas Instruments
Original
C101

A115-A

Abstract: C101 (TOP VIEW) A 1 1 6 Y0 GND A 2 5 VCC E 3 4 Y1 GND 2 5 VCC E 3 4 A 1 6 Y0 GND 2 5 VCC E Y0 6 3 4 Y1 Y1 DRY PACKAGE (TOP VIEW) Y0 EW I GND 2 V5 VCC E Y1 3 4 EPR A 1 6 YZP PACKAGE (BOTTOM VIEW) E 3 4 Y1 GND 2 5 VCC A 1 6 Y0 See mechanical drawings for , -of-2 decoder/demultiplexer. This device buffers the data on input A and passes it to the outputs Y0 (true) and
Texas Instruments
Original

SN74AUC1G19DBVR

Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK
Texas Instruments
Original
Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK Texas Instruments
Original
ISO/TS16949
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original
SN74LVC1G19 SCES464E
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original

SN74AUC1G19DBVR

Abstract: A115-A (TOP VIEW) A 1 1 6 Y0 GND A 2 5 VCC E 3 4 Y1 GND 2 5 VCC E 3 4 A 1 6 Y0 GND 2 5 VCC E Y0 6 3 4 Y1 Y1 DRY PACKAGE (TOP VIEW) Y0 EW I GND 2 V5 VCC E Y1 3 4 EPR A 1 6 YZP PACKAGE (BOTTOM VIEW) E 3 4 Y1 GND 2 5 VCC A 1 6 Y0 See mechanical drawings for , -of-2 decoder/demultiplexer. This device buffers the data on input A and passes it to the outputs Y0 (true) and
Texas Instruments
Original

SN74AUC1G19DBVR

Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK
Texas Instruments
Original

SN74AUC1G19DBVR

Abstract: ) A A GND 1 6 1 2 3 6 5 4 Y0 GND VCC Y1 Y0 VCC Y1 A GND E 1 2 3 6 5 4 Y0 VCC Y1 2 5 E E 3 4 DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) Y0 W E I VCC GND 2 V5 E Y1 3 4 EPR A 1 6 E GND A 3 4 2 5 1 6 Y1 VCC Y0 See mechanical , outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. NanoFreeTM package , (DSBGA) 0.23-mm Large Bump ­ YZP (Pb-free) SON ­ DRY ­40°C to 85°C SOT (SOT-23) ­ DBV SOT (SC-70) ­ DCK
Texas Instruments
Original
Abstract: ) DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) A 1 1 6 Y0 GND A 2 5 VCC E 3 4 Y1 GND 2 5 VCC E 3 4 A 1 6 Y0 GND 2 5 VCC E Y0 6 3 4 Y1 Y1 DRY PACKAGE (TOP VIEW) Y0 EW I GND 2 V5 VCC E Y1 , 1 6 Y0 See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This 1 , on input A and passes it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input Texas Instruments
Original
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original

A115-A

Abstract: C101 PACKAGE (TOP VIEW) 1 6 2 5 3 4 2 5 Y0 GND VCC E 3 4 2 5 VCC 3 4 Y1 Y1 VCC E 6 A Y0 GND GND 1 E A Y0 6 Y1 DRY PACKAGE (TOP VIEW) A 1 6 Y0 GND 2 5 VCC E 3 4 Y1 YZP PACKAGE (BOTTOM VIEW) E 3 4 GND 2 5 A 1 6 Y1 VCC Y0 See mechanical drawings for , input A and passes it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is
Texas Instruments
Original
Abstract: ) DBV PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW) A 1 1 6 Y0 GND A 2 5 VCC E 3 4 Y1 GND 2 5 VCC E 3 4 A 1 6 Y0 GND 2 5 VCC E Y0 6 3 4 Y1 Y1 DRY PACKAGE (TOP VIEW) Y0 EW I GND 2 V5 VCC E Y1 , 1 6 Y0 See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This 1 , on input A and passes it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input Texas Instruments
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Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
Original
Abstract: (C101) DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A GND E 1 6 Y0 VCC Y1 DRY PACKAGE (TOP VIEW) A 1 2 3 6 5 4 Y0 VCC A 1 2 3 6 5 4 Y0 VCC Y1 GND 2 5 GND E E Y1 3 4 YZP PACKAGE (BOTTOM VIEW) A GND 1 6 Y0 VCC E GND A 3 4 2 5 1 6 2 5 4 Y1 VCC Y0 E 3 Y1 See mechanical drawings for dimensions , it to the outputs Y0 (true) and Y1 (complement) when the enable (E) input signal is low. This device Texas Instruments
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