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SN54/74S533

Catalog Datasheet MFG & Type PDF Document Tags

74ls gate symbols

Abstract: 74LS534 8-Bit Latches, 8-Bit Registers with Inverting Outputs SN54/74LS533 SN54/74S533 SN54/74LS534 SN54/74S534 Features/ Benefits â'¢ Inverting outputs â'¢ Three-state outputs drive bus lines â'¢ 20 , Monolithic Memorias GUSH 12-45 SN54/74LS533 SN54/74LS534 SN54/74S533 SN54/74S534 IEEE Symbols 12-46 , SN54/74LS373/4 or SN54/74S373/4 â'" can be direct replacement when bus polarity must be changed , N,J Mil Com Invert Latch LS 54LS534 74LS534 J,W,L N,J Mil Com Register 54S533 74S533 J,W,L N,J
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OCR Scan
SN54/74S533 74LS533 54S534 74ls gate symbols 74LS series logic gate symbols 74LS53 am290l SN54/74LS533 SN54/74LS534 SN54/74S534 SN54/74LS373/4 SN54/74S373/4

74LS series logic gate symbols

Abstract: 74ls gate symbols 8 -B it Latches, 8 -B it Registers w ith Inverting Outputs SN54/74LS533 SN54/74S533 SN54/74LS534 SN54/74SS34 F ea tu res / Benefits · Inverting outputs · Three-state outputs drive bus lines · 20 , current PNP Inputs reduce loading · Ideal for microprocessor interface · Pin-compatible with SN54/74LS373/4 or SN54/74S373/4 - can be direct replacement when bus polarity must be changed PART NUMBER 54LS533 74LS533 54LS534 74LS534 54S533 74S533 54S534 74S534 PKG J.W.L N,J J.W.L N,J J,W,L N,J J,W,L N,J
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OCR Scan
SN54/74SS34 1N916 1N3064 54/74S 54/74LS
Abstract: PNP Inputs reduce loading 54S533 74S533 J.W.L N,J Mil Com â'¢ Ideal for microprocessor , boundaries â'¢ Pin-compatible with SN54/74LS373/4 or SN54/74S373/4 â'" can be direct replacement when bus -
OCR Scan
S4/74S

Flip-Flops

Abstract: dual schmitt-trigger inverters Contents Page SN54/74AC00 SN54/74ACT00 SN54/74AC04 SN54/74ACT04 SN54/74AC08 SN54/74ACT08 SN54/74AC10 SN54/74ACT10 SN54/74AC11 SN54/74ACT11 SN54/74AC14 SN54/74ACT14 SN54/74AC32 SN54/74ACT32 SN54/74AC74 SN54/74ACT74 SN54/74AC86 SN54/74ACT86 SN54/74AC240 SN54/74ACT240 SN54/74AC241 Quadruple 2 , . 2 -7 7 2 -8 3 2 -8 9 2 -9 3 2 -5 9 2 -6 5 SN54/74ACT241 Octal Buffers/Drivers With 3-State Outputs . 2 -9 9 SN54/74AC244 Octal Buffers
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OCR Scan
Flip-Flops dual schmitt-trigger inverters SN54/74AC00 SN54/74ACT00 SN54/74AC04 SN54/74ACT04 SN54/74AC08 SN54/74ACT08

74LS340

Abstract: 74ls310 8-Bit Buffers with Schmitt Trigger Inputs SN54/74LS310 SN54/74S310 SN54/74LS340 SN54/74S340 SN54/74LS341SN54/74S341 SN54/74LS344 SN54/74S344 Features â'¢ Schmitt-trigger inputs guarantee high , types combine multiplexer and driver functions â'¢ Pin-compatible with SN54/74S210/240/1/4 and SN54 , Lfliuil 12-22 SN54/74LS310/40/41/44 SN54/74S310/40/41/44 IEEE Symbols Monolithic IflJIUI Memories 12-23 SN54/74LS310 SN54/74LS340 SN54/74LS341 SN54/74LS344 Absolute Maximum Ratings Supply voltage Vcc
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OCR Scan
74LS340 74ls310 74ls344 74LS210 74LS341 74L310 SN54/74LS310 SN54/74S310 SN54/74LS340 SN54/74S340 SN54/74LS341SN54/74S341 SN54/74LS344

LS748

Abstract: 74LS147 L from El ,0 EO is changed from 40 to 45 ns. SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 1 SN54 , SN74LSXXXD Ceramic Plastic SOIC SN54/74LS148 SN54/74LS748 (TOP VIEW) OUTPUTS V CC EO GS INPUTS V , SN54/74LS147 · SN54/74LS148 · SN54/74LS748 SN54/74LS148 SN54/74LS748 FUNCTION TABLE OUTPUTS 6 H X X X , A1 H H L L H H L L H H AO H H L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H SN54
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OCR Scan
LS748 74LS147 74lS748 74LS148 LS147 LS148 SN54/74LS147 SN54/74LS148 SN54/74LS748

74LS147

Abstract: 74ls147 pin diagram SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding , Enable Output EO) octal expansion is allowed without needing external circuitry. The SN54 / 74LS748 is , . SN54 / 74LS147 (TOP VIEW) OUTPUT VCC 16 INPUTS 10-LINE-TO-4-LINE AND 8 , OUTPUTS SN54 / 74LS148 SN54 / 74LS748 (TOP VIEW) INPUTS OUTPUTS VCC 16 OUTPUT EO GS
Motorola
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74ls147 pin diagram SN54/74LS147,SN54/74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent

74ls547

Abstract: 74LS566 8-Bit Bus Register Transceivers and Latch Transceivers SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567 Features/ Benefits â'¢ Bidirectional transceivers utilizing registers or latches â , ) 970-9700 TWX: 910-338-2374 lwtCttlOf*lGS 13-14 M SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567 , a7 gnd nc b7 b6 b5 EU Plastic Chip Carrier Monoiìthìo ,-oFjy Memories 13-15 SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567 Logic Diagram SN54/74LS546 REGISTER TRANSCEIVER NON-INVERTING
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OCR Scan
LS546 74ls547 74LS566 SN74LS547 74ls546 SN74LS546 74LS567 SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567 LS546/547/566/567 LS374/373/534/533

74LS341

Abstract: 74LS340 8-Bit Buffers with Schmitt Trigger Inputs SN54/74LS310 SN54/74S310 SN54/74LS340 SN54/74S340 SN54/74LS341SN54/74S341 SN54/74LS344 SN54/74S344 Features â'¢ Schmitt-trigger inputs guarantee high , types combine multiplexer and driver functions â'¢ Pin-compatible with SN54/74S210/240/1/4 and SN54 , Memorias UUHÃI 12-22 SN54/74LS310/40/41/44 SN54/74S310/40/41/44 IEEE Symbols '310 '340 , Monolithic KM Memories 12-23 SN54/74LS310 SN54/74LS340 SN54/74LS341 SN54/74LS344 Absolute Maximum Ratings
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OCR Scan
IA2E 74LS31 LS344 s344 SN54/74S344 SN54/74S210/240/1/4 SN54/74LS210/240/1/4 II500 SN54/74LS310/40/41/44 SN54/74S310/40/41/44

74LS169

Abstract: 74LS168 datasheet pins SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage up/down counters featuring a , control the direction of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary sequence. All state changes, whether in , = PIN 8 FAST AND LS TTL DATA 5-1 15 SN54/74LS168 · SN54/74LS169 STATE DIAGRAMS SN54
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SN54LSXXXJ SN74LSXXXN 74LS168 datasheet pins 74LS168 application note data sheet 74LS169 SN54/74LS168 SN54/74LS169

74ls379

Abstract: FLIP-FLOP WITH ENABLE The SN54/74LS377 is an 8-bit register built using advanced Low Power Schottky , common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54/74LS174, but with common Enable rather than common Master Reset. The SN54/74LS379 Is a 4-Bit Register with buffered common Enable. This device is similar to the SN54/74LS175 but features , Outputs Input Clamp Diodes Limit High Speed Termination Effects SN54/74LS377 SN54/74LS378 SN54/74LS379
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OCR Scan
74ls379 SN54/74LS377 SN54/74LS378 SN54/74LS174 SN54/74LS379 SN54/74LS175

74LS147

Abstract: 74LS148 El to EO is changed from 40 to 45 ns. SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-0S SN54 , SN74LSXXXD Ceramic Plastic SOIC SN54/74LS148 SN54/74LS748 (TOP VIEW) OUTPUTS V cc EO GS 3 INPUTS A , J LiJ OUTPUTS FAST AND LS TTL DATA 5-139 SN54/74LS147 · SN54/74LS148 · SN54/74LS748 SN54/74LS148 SN54/74LS748 FUNCTION TABLE OUTPUTS 6 H X X X L H H H H H 7 H X X L H H H H H H 8 H X L H H H H H
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OCR Scan
ttl 74ls147 6200S ttl 74ls148 LS 74LS147

74LS682

Abstract: (g) MOTOROLA 8-BIT MAGNITUDE COMPARATORS The SN54/74LS682, 684, 688 are 8-bit magnitude , or switch data. CONNECTION DIAGRAMS (TOP VIEW) SN54/74LS682 SN54/74LS684 SN54/74LS688 8 , HIGH Level, L = LOW Level, X = Irrelevant FAST AND LS TTL DATA SN54/74LS682 · SN54/74LS684 · SN54/74LS688 GUARANTEED OPERATING RANGES Symbol VCC Ta Supply Voltage Parameter 54 74 54 74 54 , for more than 1 second. FAST AND LS TTL DATA 5-379 SN54/74LS682 · SN54/74LS684 · SN54/74LS688
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OCR Scan
74LS682 SN54/74LS682 LS682 LS684 LS688 SN54/74LS684 SN54/74LS688

S7001

Abstract: 74S734 u l i i U J 8-51 SN54/74S700/-1 SN54/74S730/-1 SN54/74S731 /-1 SN54/74S734/-1 Function Tables , MonolithiciTJIUMemorias SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74S734/-1 IEEE Symbol S700/-1 , \ ^ 3 -2Y1 -2Y 2 -2 Y 3 -2Y 4 E SMemorias E Monollthia 8-53 SN54/74S700/-1 SN54/74S730/-1 SN54/74S731 /-1 SN54/74S734/-1 Absolute Maximum Ratings Supply voltage Vq q , 8-55 SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74S734/-1 Switching Characteristics
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OCR Scan
S7001 74S734 SN74S731 SN54S700/-1 SN74S700/-1 SN54S730/-1 SN74S730/-1 S700/730/731/734 S210/240/241/244

74ls652

Abstract: 74LS654 8-Bit Bus Front-Loading-Latch SN54/74LS651 SN54/74LS652 SN54/74LS653 SN54/74LS654 Features , 13-46 SN54/74LS651 SN54/74LS652 SN54/74LS653 SN54/74LS654 Logic Diagrams CKA-â'"t> - 21 J^ gba , open-collector. The B bus outputs are 3-state for both devices. Monolithic RE! Memories 13-47 SN54/74LS651 SN54/74LS652 SN54/74LS653 SN54/74LS654 IEEE Symbols L8651 'LS653 en1 [ba] en2 [ab] ⺠c4 g5 »C6 , c4 g5 »C6 g7 X , 21 < 2V IT ^nr 13-48 MonolHhle Memor/as SN54/74LS651 SN54/74LS652 SN54
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OCR Scan
LS652 74ls652 74LS654 74LS653 SN54LS651JS SN74LS654 SN54/74LS651 SN54/74LS652 SN54/74LS653 SN54/74LS654 LS653/4 LS651

74Ls79

Abstract: (M) MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS , C urrent â'" Low 54 74 8.0 16 mA FAST AND LS TTL DATA 5-382 SN54/74LS795 â'¢ SN54/74LS796 SN54/74LS797 â'¢ SN54/74LS798 LOGIC DIAGRAMS ''cc G A8 Y8 A7 Y7 2 Y6 A5 V q c G2 Y5 A8 As Y8 A7 Y7 A6 A7 Y7 A6 Y6 A5 Y5 Y6 A5 Y5 SN54/74LS796 SN54/74LS795 V c c G2 Y8 Y6 A5 Y5 V c c G2 A8 SN54/74LS797 Y8 A7 Y7 A6
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OCR Scan
74Ls79 SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 LS795

74LS163

Abstract: LS163A SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A BCD DECADE COUNTERS/ 4-BIT BINARY , SN54/74LS160A · SN54/74LS161A SN54/74LS162A · SN54/74LS163A STATE DIAGRAM LS160A · LS162A 0 1 , Care SN54/74LS160A · SN54/74LS161A SN54/74LS162A · SN54/74LS163A GUARANTEED OPERATING RANGES , , nor for more than 1 second. FAST AND LS TTL DATA 5-280 SN54/74LS160A · SN54/74LS161A SN54/74LS162A · SN54/74LS163A LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless
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SN54/74LS160A SN54/74LS161A LS161A 74LS163 74LS160 74LS162 74LS161A LS160 SN54/74LS162A SN54/74LS163A LS161

ls378

Abstract: 74LS377 SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low , clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to
Motorola
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74LS175 ls378 751D-03

74LS688

Abstract: 74LS684 SN54/74LS682 SN54/74LS684 SN54/74LS688 8-BIT MAGNITUDE COMPARATORS The SN54 / 74LS682, 684 , 16 15 14 13 12 11 J SUFFIX CERAMIC CASE 732-03 20 1 SN54/74LS682/684 1 , SUFFIX PLASTIC CASE 738-03 11 20 1 1 SN54/74LS688 1 G 2 P0 3 Q0 4 P1 5 , = Irrelevant FAST AND LS TTL DATA 5-1 SN54/74LS682 · SN54/74LS684 · SN54/74LS688 GUARANTEED , second. FAST AND LS TTL DATA 5-2 VCC = MAX VIN = 0 4 V MAX, 0.4 VCC = MAX VCC = MAX SN54
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74LS688 74LS684 SN54/74LS682/684 SN74LSXXXDW

74LS39

Abstract: 74LS393 ® / 3 IS MOTOROLA DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54/74L3390 and SN54/74LS393 each contain a pair« 4-stage ripple counters. Each half of the LS390 is parti , to a ts _ SN54/74LS390 Vcc CP0 MR Q0 CP! 0, 02 Û3 16 15 14 13 12 11 10 CP0 MR Qq CP! Qi Q2 Da GND SN54/74LS393 VCC CP MR Q0 Qi 0 C>2 Q3 NOTE: The Flatp.J version has the sa e , SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER LOW POWER SCHOTTKY 16 n
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OCR Scan
LS393 LS290 LS293 74LS39 74LS393 74LS390 74l3 751A-02 SN54/74L3390 SN54/74LS393 SN54/74LS390
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