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Part Manufacturer Description Datasheet BUY
DLPR910YVA Texas Instruments DLPR910 Configuration PROM for DLPC910 48-DSBGA visit Texas Instruments
PMP7410 Texas Instruments Uses TPS40210 in Sepic configuration to generate 14.4V output visit Texas Instruments
DLPR910AYVA Texas Instruments DLPR910 Configuration PROM for DLPC910 48-DSBGA visit Texas Instruments
SN74ALS996FN3 Texas Instruments ALS SERIES, 8-BIT DRIVER, CONFIGURABLE OUTPUT, PQCC28 visit Texas Instruments
SN74ALS996-1NT3 Texas Instruments ALS SERIES, 8-BIT DRIVER, CONFIGURABLE OUTPUT, PDIP24 visit Texas Instruments
SN74ALS996-1FN3 Texas Instruments ALS SERIES, 8-BIT DRIVER, CONFIGURABLE OUTPUT, PQCC28 visit Texas Instruments

PRIM configuration

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: V or 3.3 V, PCI buses (each running up to 33 M Hz), on the secondary interface. It is prim arily , Little-Endian to the Bus and Internal Configuration Space â'¢ Errors Resulting in A ssertion of S ER R # Are , rites to com plete. â'¢ APB routes INT ACK cycles received on the prim ary bus to either secondary bus, allowing PC-standard south bridges to exist on the secondary bus instead of the prim ary bus , on the secondary bus to a target on the prim ary bus. Equivalent to â'upstream â' . Accesses by a -
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Abstract: from the prim ary bus. When p jd s e l is asserted during the address phase of a Type 0 configuration , clear register state, and configuration registers are still accessible from the prim ary PCI interface , uses a Type 0 configuration header, which presents the entire subsystem as a single â'deviceâ' to , Type 0 configuration header, it does not require hierarchical PCI-to-PCI bridge configuration code , nontransparency of the 21554 is perfectly suited to this kind of configuration, where a transparent PCI-to-PCI -
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parallel port 378H

Abstract: 278-H APPLICATION NOTE 048 SMC FDC 37 C 665 / 666 controller configuration From: RP, MG Customer , . Function Prim. Serial Port Config. Control 1 Prim. Serial Port Config. Control 0 IDE Adress Control Floppy Disk Adress Control Parallel Port Mode Control Parallel Port Configuration Control 0 Parallel Port Configuration Control 1 IDE Configuration Control Floppy Disk Configuration Control Sec. Serial , 0 1 0 1 Prim. Serial Port Add. Disable 3E8h (COM3) 2F8h (COM2) 3F8h (COM1) S1CF1 0 0
DIGITAL-LOGIC
Original

PRIM configuration

Abstract: AN-0004 MICRO SWITCH PRIM (6WRS FEATURES The Emergency stop feature can be accomplished very easily with this configuration. Because the hot power supply wiring is not critical for PRIM to motor , motor drivers. AN-0004 E-STOP ± PRIM 1 SDS NETWORK Do NOT switch out the common ground supply wire because that is required for PRIMs to operate. HONEYWELL Sensing and Control PRIM 2 ± MICRO SWITCH PRIM (6WRS AN-0004 SALES AND SERVICE Honeywell's MICRO SWITCH Division
Honeywell
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PRIM configuration
Abstract: connections for all possible components. Each configuration uses only some of the components. Cal In 1 SCC Dot T3 C6 10nF 5 Prim Dot 1 SCC Dot 2 NC 5 Prim Dot T4 Cal Out 2 NC 3 ETC1-1-13 4 Prim 3 C7 ETC1-1-13 10nF 4 Prim +5V A C3 0 G1 C1 2.2mF , R1A 49.9W R1 25W R2 NC R4 1kW C4 10nF U1 8 1 T1 5 Prim Dot Out A -VS +In B 1 SCC Dot -In A +In A In Diff +VS In B 4 Prim R3 25W -In B R5 Texas Instruments
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SBOU064
Abstract: . REG Configuration registers and corresponding control logic. Accessible from the prim ary interface , information about configuration space registers. â'¢ Chapter 6.0, â'Diagnostics and Test Mechanismsâ , Machine and control logic for all transactions initiated on the prim ary interface, w hether the , primary interface. Used for writes initiated on the secondary PCI bus or reads initiated on the prim ary PCI bus. PSD Data path for data received on the prim ary interface and driven on the secondary -
OCR Scan
Abstract: Prim ary PCI interface allow configuration cycles to occur. Advance Information intei Table 4 , ) PRIM ARY PCI BUS INITIALIZATION DEVICE SELECT is used to select the Tuzigoot during a Configuration , dedicated PCI configuration space accessible through the primary PCI bus. 2.1.2 Private PCI Device , bridge and Address Translation Unit work together to hide private PCI devices from PCI configuration , issues PCI configuration cycles to configure hidden devices. 2.1.3 DMA Controller The DM A -
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80960RN 80960JT 1710H 8710H
Abstract: and the configuration block. Data path for data received on the prim ary interface and driven on the , . 4-14 Configuration Transactions , . 7-2 7.2.1 Configuration Write Transactions to 21152 Configuration Space. 7-2 , . 12-1 Configuration Space Registers. 13-1 13.1 PCI-to-PCI Bridge Standard Configuration R egisters -
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21152-AA 21152-AB
Abstract: are repeated at a voltage Just below the operating threshold of any secondary protectors. 4. Prim , configuration. The second is a 150 0 V 10 x 160ps pulse applied in longitudinal configuration. For AC powered , Polarity 1 .L .M 5000 2/10 500 1 M in. Notes: 1. L = Longitudinal M ode 2. Prim ary , Mode 2. Prim ary protectors removed. 3. Repeated at a voltage just below the operating threshold of , . L = Longitudinal Mode, M = Metallic Mode 2. Prim ary protectors removed. Table 4 - FCC Part 68 -
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AN96-8 TR-NWT-001089 T-001089 AN34REV1

Exar cross

Abstract: XRT94L31 is included for control, configuration and monitoring. REV. P1.0.0 FEATURES · Provides DS3 , ck Prim a ry & Prim a ry & Re du nd a n t Re du nd a n t T x S TS T x STS PEC L P EC L In te rf ace In te rf Blo c k ac e Blo c k Prim a ry & Prim a ry & Re du nd a n t Re du nd a n t Rx ST S Rx ST S TO H TO H Pr o ces s o r Pr o ces s o r Blo c k Blo c k Prim a ry & , Te le c o m Bu s Bu s Blo ck Blo c k Prim a ry & Prim ary & Re du nd a n t Re du nd an t Rx
Exar
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XRT94L31 Exar cross XRT94L31IB
Abstract: Connectors - Specify By Adding B, T O r N Suffix At End O f Model # PORT CONFIGURATION TYPE OUTLINE Prim ary (Dot) Prim ary Prim ary (Ct) Secondary (Dot) Secondary Secondary (Ct) Case Ground -
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TA-01- TA-02- TA-05 TA-04- TA-06- TA-07-

K4143

Abstract: Terminal Functions primary PCI system TERM INAL NAME PCLK NO. 152 I/O TYPE I FUNCTION Prim ary PCI bus clock. P CLK provides timing fo ra li transactions on the prim ary PCI bus. All prim ary PCI signals are sam pled at rising edge of P CLK. PCI reset. W hen the prim ary PCI bus reset is asserted, P RST , address phase of a prim ary bus PCI cycle, P A D 3 1 - P A D 0 contain a 32-bit address or other , DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the prim ary bus, the bridge
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K4143 PCI2031 ACP11 33-MH 176-P

Monopulse

Abstract: split-block configuration. The result is excellent electrical performance that helps the system designer , . A-Band E and H-Plane Prim ary Patterns 1-64 ALPHA INDUSTRIES, INC. · TRQ GR O UP . 20 SYLVAN ROAD , H-Plane Prim ary Patterns W -B m d i-Miw Prim ary Pmttgm W -Band E and H-Plane Secondary
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Monopulse

AZ1008

Abstract: 80960RN the Configuration Cycle Retry bit is cleared in the Extended Bridge Control Register. If low, the Prim , Delayed and Posted Transaction Support I2C Bus Interface Unit - Forwards Memory, I/O, Configuration - , . 16 Jx Core Signals and Configuration S tra p s , supports PCI 64-bit Dual Address Cycle (DAC) addressing. The bridge has dedicated PCI configuration space , work together to hide private PCI devices from PCI configuration cycles and allow these hidden devices
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AZ1008
Abstract: Blocks Avai ailable: (See Chart) Add Suffix To Catalog No. Configuration -F 2 -F 3 GROUP â'˜Aâ'™ THROUGH 500 VA GROUP â'˜Bâ'™ THROUGH 1000 VA Integrall / m ounted 2-p ole prim ary block Integrall / m ounted 3-pole prim a ry and secondary block C onsult factory lor othei size ; available , , Prim ary Fuse Block 5.72 33 .31 x .50 P L-1 12 602 5 amps 5 ., P L -112602 â fy -
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PL-112602 TA-2-81211 PL-112601 L-112601 TA-2-81218

ALPHA INDUSTRIES

Abstract: Monopulse configuration. The result is excellent electrical perform ance that helps the system designer achieve , critical factors. Prim ary Feed C h aracteristics Model Number: Frequency Range (GHz)1 Sum Port 3 dB , e Prim ary Patterns 1-64 ALPHA INDUSTRIES, INC. · TRG GROUP · 20 SYLVAN ROAD, WOBURN, MA 01801 Miniaturized Millimeter Wave Monopulse Comparator Feed Assembly W -Band E and H -P lan e Prim ary Patterns
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ALPHA INDUSTRIES ANTENNA parabolic

micro inverter for cfl lamps

Abstract: of micro inverter for cfl lamps battery life. The high e fficiency is achieved by using a sw itching regulator in a buck configuration , between this pin and B EA-. O scillato r timing capacitor. Zero crossing detector input. Connects to prim , gate of M O SFET in prim ary side of contrast control. Positive power 5 volt input. O utput of M O SFET , . Connects to gate of one side of output M O SFET pair. C ircu it and power com m on. D rives the prim ary of , regulator and a Royer type inverter circu it to drive the lamp. The PW M regulator, in a buck configuration
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L4864 micro inverter for cfl lamps of micro inverter for cfl lamps Royer oscillator inverter lg ig drive cfl LAMP circuit diagram ML4864

quad relay board

Abstract: ) addressing. The bridge has dedicated PCI configuration space that is accessible through the prim ary PCI bus , the 80960R x's internal local bus, not the PCI local bus. · Prim ary and Secondary P C I buses are the , extension not found on the i960 Kx, Sx or Cx processors. Physical and logical configuration registers enable , secondary PCI bus without being detected by PCI configuration software. The bridge and Address Translation Unit work together to hide private devices from PCI configuration cycles and allow these devices to use
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quad relay board 80960RD 80960RP

smps transformer

Abstract: SOFT-START S UPPLY VOLTAGE O UTPUT April 1996 1/6 TDA4605 PIN CONFIGURATION Pin Num ber 1 , , no load) Prim ary current sim ulation : information input regarding the prim ary current. The prim ary current rise in the prim ary winding is sim ulated at Pin 2 as avo lta g e rise by means of , point. Prim ary voltage detector : input for prim ary voltage monitoring. W hen the line voltage is too
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smps transformer 4605D

ICL7675CPA

Abstract: ICL7676CPA in this type o f configuration, th e Harris c o n tro lle r chip se t is trim m ed to provide a regulated 5V o ut put. The tw o chips com prise a prim ary side co n tro lle r and a se condary side controller. R eferring to Figure 3, th e o utp ut o f th e prim ary side co n tro lle r drives th e pow er M O SFET sw itch in the prim ary leg o f th e transform er. The sw itch is alw ays turned o ff a t a , sfo rm e r to th e prim ary side contro lle r, thereby com pleting th e control loop. Power fo r th e
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ICL7675CPA ICL7676CPA IRF FET V180P ICL7675 IRF 640 FET L7675/IC L7676
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